From 3de09011e675a29b5a4d9d8ef4368708642332fa Mon Sep 17 00:00:00 2001 From: hailfinger Date: Sat, 9 May 2009 02:30:21 +0000 Subject: Chips like the SST SST25VF080B can only handle single byte writes outside AAI mode. Change SPI architecture to handle 1-byte chunk chip writing differently from 256-byte chunk chip writing. Annotate SPI chip write functions with _256 or _1 suffix denoting the number of bytes they write at maximum. The 1-byte chunk writing is cut-n-pasted to different SPI drivers right now. A later patch can move them to the generic spi_chip_write_1. Signed-off-by: Carl-Daniel Hailfinger Acked-by: Carl-Daniel Hailfinger git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@485 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- wbsio_spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'wbsio_spi.c') diff --git a/wbsio_spi.c b/wbsio_spi.c index 6ab277a..e2cc4b1 100644 --- a/wbsio_spi.c +++ b/wbsio_spi.c @@ -186,7 +186,7 @@ int wbsio_spi_read(struct flashchip *flash, uint8_t *buf) return 0; } -int wbsio_spi_write(struct flashchip *flash, uint8_t *buf) +int wbsio_spi_write_1(struct flashchip *flash, uint8_t *buf) { int pos, size = flash->total_size * 1024; int result; -- cgit v1.2.1