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authorpierre <pierre@3ad0048d-3df7-0310-abae-a5850022a9f2>2020-12-31 11:18:37 +0000
committerpierre <pierre@3ad0048d-3df7-0310-abae-a5850022a9f2>2020-12-31 11:18:37 +0000
commit7dd257e46acb0bee25364781dc2b2fed69718a84 (patch)
tree9a29d2da1af26d999c523da38a320e0880c50eae
parent0fbd34bfb76c4b073895d03a12058c005972b457 (diff)
downloadfpc-7dd257e46acb0bee25364781dc2b2fed69718a84.tar.gz
Merge of commit #47207
------------------------------------------------------------------------ r47207 | pierre | 2020-10-26 13:40:45 +0000 (Mon, 26 Oct 2020) | 1 line Change CLZ support for arm32 minimal CPU to armv5t according to ARM documentation in arminst.dat ------------------------------------------------------------------------ --- Merging r47207 into '.': U compiler/arm/armins.dat U compiler/arm/armtab.inc --- Recording mergeinfo for merge of r47207 into '.': U . git-svn-id: https://svn.freepascal.org/svn/fpc/branches/fixes_3_2@47923 3ad0048d-3df7-0310-abae-a5850022a9f2
-rw-r--r--compiler/arm/armins.dat2
-rw-r--r--compiler/arm/armtab.inc2
2 files changed, 2 insertions, 2 deletions
diff --git a/compiler/arm/armins.dat b/compiler/arm/armins.dat
index 19624c8949..8d794c4c8b 100644
--- a/compiler/arm/armins.dat
+++ b/compiler/arm/armins.dat
@@ -259,7 +259,7 @@ fpureg,immshifter,memam2 \xA0\xC\x10\x2\x0 ARM32,FPA
[CLZcc]
reg32,reg32 \x80\xFA\xB0\xF0\x80 THUMB32,ARMv6T2
-reg32,reg32 \x32\x01\x6F\xF\x10 ARM32,ARMv4
+reg32,reg32 \x32\x01\x6F\xF\x10 ARM32,ARMv5T
[CPS]
immshifter \x8F\xF3\xAF\x81\x00 THUMB32,ARMv6T2
diff --git a/compiler/arm/armtab.inc b/compiler/arm/armtab.inc
index 7206599323..c241f3b2eb 100644
--- a/compiler/arm/armtab.inc
+++ b/compiler/arm/armtab.inc
@@ -768,7 +768,7 @@
ops : 2;
optypes : (ot_reg32,ot_reg32,ot_none,ot_none,ot_none,ot_none);
code : #50#1#111#15#16;
- flags : if_arm32 or if_armv4
+ flags : if_arm32 or if_armv5t
),
(
opcode : A_CPS;