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authorlaksen <laksen@3ad0048d-3df7-0310-abae-a5850022a9f2>2018-07-22 18:38:07 +0000
committerlaksen <laksen@3ad0048d-3df7-0310-abae-a5850022a9f2>2018-07-22 18:38:07 +0000
commit49f6d7ce440c0512813da152d7278adc506b24d9 (patch)
tree0d7f3a76976854159eb8cf0a1706798ba53b193d
parentf8053ed623ee77f207ca97e05c66b6d1e0919c02 (diff)
downloadfpc-49f6d7ce440c0512813da152d7278adc506b24d9.tar.gz
Added implementation of InstructionLoadsFromReg.
Fixed spilling_get_operation_type_ref, no mem operation modifies ref registers. git-svn-id: https://svn.freepascal.org/svn/fpc/branches/laksen@39487 3ad0048d-3df7-0310-abae-a5850022a9f2
-rw-r--r--riscv_new/compiler/riscv/aasmcpu.pas8
-rw-r--r--riscv_new/compiler/riscv64/aoptcpu.pas30
2 files changed, 29 insertions, 9 deletions
diff --git a/riscv_new/compiler/riscv/aasmcpu.pas b/riscv_new/compiler/riscv/aasmcpu.pas
index c6b1baa5c8..30acbaa154 100644
--- a/riscv_new/compiler/riscv/aasmcpu.pas
+++ b/riscv_new/compiler/riscv/aasmcpu.pas
@@ -527,14 +527,6 @@ uses cutils, cclasses;
function taicpu.spilling_get_operation_type_ref(opnr: longint; reg: tregister): topertype;
begin
result := operand_read;
- case opcode of
-{$ifdef RISCV64}
- A_SD,
-{$endif RISCV64}
- A_SB,A_SH,A_SW:
- if opnr=1 then
- result:=operand_write;
- end;
end;
diff --git a/riscv_new/compiler/riscv64/aoptcpu.pas b/riscv_new/compiler/riscv64/aoptcpu.pas
index 3eb1bd9bbe..5deff9617e 100644
--- a/riscv_new/compiler/riscv64/aoptcpu.pas
+++ b/riscv_new/compiler/riscv64/aoptcpu.pas
@@ -37,7 +37,9 @@ uses
aasmtai, aasmcpu;
type
+
TCpuAsmOptimizer = class(TAsmOptimizer)
+ function InstructionLoadsFromReg(const reg: TRegister; const hp: tai): boolean; override;
function RegLoadedWithNewValue(reg: tregister; hp: tai): boolean; override;
Function GetNextInstructionUsingReg(Current: tai; Out Next: tai; reg: TRegister): Boolean;
{ outputs a debug message into the assembler file }
@@ -63,6 +65,32 @@ implementation
{$endif DEBUG_AOPTCPU}
+ function TCpuAsmOptimizer.InstructionLoadsFromReg(const reg: TRegister; const hp: tai): boolean;
+ var
+ p: taicpu;
+ i: longint;
+ begin
+ result:=false;
+ if not (assigned(hp) and (hp.typ=ait_instruction)) then
+ exit;
+ p:=taicpu(hp);
+
+ i:=0;
+ while(i<p.ops) do
+ begin
+ case p.oper[I]^.typ of
+ top_reg:
+ result:=(p.oper[I]^.reg=reg) and (p.spilling_get_operation_type(i)<>operand_write);
+ top_ref:
+ result:=
+ (p.oper[I]^.ref^.base=reg);
+ end;
+ if result then exit; {Bailout if we found something}
+ Inc(I);
+ end;
+ end;
+
+
function TCpuAsmOptimizer.RegLoadedWithNewValue(reg: tregister; hp: tai): boolean;
begin
result:=
@@ -70,7 +98,7 @@ implementation
(taicpu(hp).ops>1) and
(taicpu(hp).oper[0]^.typ=top_reg) and
(taicpu(hp).oper[0]^.reg=reg) and
- (taicpu(hp).spilling_get_operation_type(0)=operand_write);
+ (taicpu(hp).spilling_get_operation_type(0)<>operand_read);
end;