* integer and float registers do not overlay on Risc-V

git-svn-id: https://svn.freepascal.org/svn/fpc/branches/laksen@39512 3ad0048d-3df7-0310-abae-a5850022a9f2

1 files changed, 6 insertions, 5 deletions

diff --git a/riscv_new/compiler/riscv64/cpupara.pas b/riscv_new/compiler/riscv64/cpupara.pas
index 010e51d3eb..01b7b3586c 100644
--- a/riscv_new/compiler/riscv64/cpupara.pas
+++ b/riscv_new/compiler/riscv64/cpupara.pas
@@ -467,7 +467,6 @@ implementation
 
             paraloc^.register := newreg(R_INTREGISTER, nextintreg, R_SUBNONE);
             inc(nextintreg);
-            inc(nextfloatreg);
             dec(paralen, tcgsize2size[paraloc^.size]);
           end else if (loc = LOC_FPUREGISTER) and
             (nextfloatreg <= RS_F17) then begin
@@ -476,13 +475,15 @@ implementation
             paraloc^.def := locdef;
             paraloc^.register := newreg(R_FPUREGISTER, nextfloatreg, R_SUBWHOLE);
             { the RiscV ABI says that the GPR index is increased for every parameter, no matter
-            which type it is stored in }
-            inc(nextintreg);
+              which type it is stored in
+
+               not really, https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#hardware-floating-point-calling-convention says
+               otherwise, gcc doesn't do it either }
             inc(nextfloatreg);
             dec(paralen, tcgsize2size[paraloc^.size]);
           end else if (loc = LOC_MMREGISTER) then begin
-            { Altivec not supported }
-            internalerror(200510192);
+            { no mm registers }
+            internalerror(2018072601);
           end else begin
             { either LOC_REFERENCE, or one of the above which must be passed on the
             stack because of insufficient registers }