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| author | laksen <laksen@3ad0048d-3df7-0310-abae-a5850022a9f2> | 2018-07-22 19:25:46 +0000 |
|---|---|---|
| committer | laksen <laksen@3ad0048d-3df7-0310-abae-a5850022a9f2> | 2018-07-22 19:25:46 +0000 |
| commit | a6f2e9d3879cc82a49f1e8838b081175c93a8232 (patch) | |
| tree | 4dfd388fac2d7dd9abe35bf339ac306cdfbeaf5d | |
| parent | 17aa99f3c0ce88ea3156ac122314f2701b8d1dba (diff) | |
| download | fpc-a6f2e9d3879cc82a49f1e8838b081175c93a8232.tar.gz | |
Fix shift operations on 32bit operands.
git-svn-id: https://svn.freepascal.org/svn/fpc/branches/laksen@39489 3ad0048d-3df7-0310-abae-a5850022a9f2
| -rw-r--r-- | riscv_new/compiler/riscv/cgrv.pas | 48 |
1 files changed, 46 insertions, 2 deletions
diff --git a/riscv_new/compiler/riscv/cgrv.pas b/riscv_new/compiler/riscv/cgrv.pas index ee739183ad..ed75d2241d 100644 --- a/riscv_new/compiler/riscv/cgrv.pas +++ b/riscv_new/compiler/riscv/cgrv.pas @@ -201,6 +201,27 @@ unit cgrv; a:=-a; end; +{$ifdef RISCV64} + if (op=OP_SHL) and + (size in [OS_32,OS_S32]) then + begin + list.concat(taicpu.op_reg_reg_const(A_SLLIW,dst,src,a)); + maybeadjustresult(list,op,size,dst); + end + else if (op=OP_SHR) and + (size in [OS_32,OS_S32]) then + begin + list.concat(taicpu.op_reg_reg_const(A_SRLIW,dst,src,a)); + maybeadjustresult(list,op,size,dst); + end + else if (op=OP_SAR) and + (size in [OS_32,OS_S32]) then + begin + list.concat(taicpu.op_reg_reg_const(A_SRAIW,dst,src,a)); + maybeadjustresult(list,op,size,dst); + end + else +{$endif RISCV64} if (TOpCG2AsmConstOp[op]<>A_None) and is_imm12(a) then begin @@ -232,8 +253,31 @@ unit cgrv; OP_MOVE: a_load_reg_reg(list,size,size,src1,dst); else - list.concat(taicpu.op_reg_reg_reg(TOpCG2AsmOp[op],dst,src2,src1)); - maybeadjustresult(list,op,size,dst); +{$ifdef RISCV64} + if (op=OP_SHL) and + (size in [OS_32,OS_S32]) then + begin + list.concat(taicpu.op_reg_reg_reg(A_SLLW,dst,src2,src1)); + maybeadjustresult(list,op,size,dst); + end + else if (op=OP_SHR) and + (size in [OS_32,OS_S32]) then + begin + list.concat(taicpu.op_reg_reg_reg(A_SRLW,dst,src2,src1)); + maybeadjustresult(list,op,size,dst); + end + else if (op=OP_SAR) and + (size in [OS_32,OS_S32]) then + begin + list.concat(taicpu.op_reg_reg_reg(A_SRAW,dst,src2,src1)); + maybeadjustresult(list,op,size,dst); + end + else +{$endif RISCV64} + begin + list.concat(taicpu.op_reg_reg_reg(TOpCG2AsmOp[op],dst,src2,src1)); + maybeadjustresult(list,op,size,dst); + end; end; end; |