diff options
| author | laksen <laksen@3ad0048d-3df7-0310-abae-a5850022a9f2> | 2018-09-16 20:51:15 +0000 |
|---|---|---|
| committer | laksen <laksen@3ad0048d-3df7-0310-abae-a5850022a9f2> | 2018-09-16 20:51:15 +0000 |
| commit | c041e65b3d2f03a695b7843aa8446ab1838595f9 (patch) | |
| tree | 9f830362735c900bc23e97042712290c568afbc0 | |
| parent | 6a21f8eb4bcbbe5b2f1d61192484439916a93e89 (diff) | |
| download | fpc-c041e65b3d2f03a695b7843aa8446ab1838595f9.tar.gz | |
Fix bug in lui+addi immediate load for spilling code.
git-svn-id: https://svn.freepascal.org/svn/fpc/branches/laksen@39764 3ad0048d-3df7-0310-abae-a5850022a9f2
| -rw-r--r-- | riscv_new/compiler/riscv/rgcpu.pas | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv_new/compiler/riscv/rgcpu.pas b/riscv_new/compiler/riscv/rgcpu.pas index 3c7047e4db..e24821575a 100644 --- a/riscv_new/compiler/riscv/rgcpu.pas +++ b/riscv_new/compiler/riscv/rgcpu.pas @@ -67,9 +67,9 @@ unit rgcpu; hreg:=cg.getintregister(helplist,OS_ADDR); if (spilltemp.offset and $800)<>0 then - helplist.concat(taicpu.op_reg_const(A_LUI,hreg,(spilltemp.offset shr 12) and $FFFFF)) + helplist.concat(taicpu.op_reg_const(A_LUI,hreg,((spilltemp.offset shr 12)+1) and $FFFFF)) else - helplist.concat(taicpu.op_reg_const(A_LUI,hreg,((spilltemp.offset shr 12)+1) and $FFFFF)); + helplist.concat(taicpu.op_reg_const(A_LUI,hreg,(spilltemp.offset shr 12) and $FFFFF)); helplist.concat(taicpu.op_reg_reg_const(A_ADDI,hreg,hreg,SarSmallint(spilltemp.offset shl 4,4))); helplist.concat(taicpu.op_reg_reg_reg(A_ADD,hreg,hreg,spilltemp.base)); |