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authorflorian <florian@3ad0048d-3df7-0310-abae-a5850022a9f2>2020-04-20 20:08:19 +0000
committerflorian <florian@3ad0048d-3df7-0310-abae-a5850022a9f2>2020-04-20 20:08:19 +0000
commit5bd41b83d1bedae5186d0eb862423ebf6c75b86e (patch)
treef6ab13acb154b1eefd94aeeacc3f28743f1d0449
parentdc0d9f034ab3d674fd9fa59451213e4654b0723c (diff)
downloadfpc-5bd41b83d1bedae5186d0eb862423ebf6c75b86e.tar.gz
+ forgotten files added
git-svn-id: https://svn.freepascal.org/svn/fpc/trunk@44889 3ad0048d-3df7-0310-abae-a5850022a9f2
Diffstat
-rw-r--r--rtl/freertos/arm/cortexm0.pp78
-rw-r--r--rtl/freertos/arm/cortexm0_start.inc75
-rw-r--r--rtl/freertos/arm/cortexm3.pp189
-rw-r--r--rtl/freertos/arm/cortexm3_start.inc65
-rw-r--r--rtl/freertos/arm/cortexm4.pp189
-rw-r--r--rtl/freertos/arm/cortexm4f_start.inc65
-rw-r--r--rtl/freertos/arm/cortexm7.pp256
-rw-r--r--rtl/freertos/arm/stm32f103xe.pp924
-rw-r--r--rtl/freertos/arm/stm32f401xe.pp891
-rw-r--r--rtl/freertos/arm/stm32g071xx.pp760
10 files changed, 3492 insertions, 0 deletions
diff --git a/rtl/freertos/arm/cortexm0.pp b/rtl/freertos/arm/cortexm0.pp
new file mode 100644
index 0000000000..dfa5a44f51
--- /dev/null
+++ b/rtl/freertos/arm/cortexm0.pp
@@ -0,0 +1,78 @@
+{
+ System register definitions and utility code for Cortex-M0
+ Created by Jeppe Johansen 2012 - jeppe@j-software.dk
+ Modified for M0 by Michael Ring 2013 - mail@michael-ring.org
+}
+unit cortexm0;
+
+interface
+
+{$PACKRECORDS 2}
+const
+ SCS_BASE = $E000E000;
+ SysTick_BASE = SCS_BASE+$0010;
+ NVIC_BASE = SCS_BASE+$0100;
+ SCB_BASE = SCS_BASE+$0D00;
+
+ DWT_BASE = $E0001000;
+ FP_BASE = $E0002000;
+ ITM_BASE = $E0000000;
+ TPIU_BASE = $E0040000;
+ ETM_BASE = $E0041000;
+
+type
+
+ TNVICRegisters = record
+ ISER : dword;
+ RESERVED0 : array[0..30] of dword;
+ ICER : dword;
+ RSERVED1 : array[0..30] of dword;
+ ISPR : dword;
+ RESERVED2 : array[0..30] of dword;
+ ICPR : dword;
+ RESERVED3 : array[0..30] of dword;
+ RESERVED4 : array[0..63] of dword;
+ IPR : array[0..7] of dword;
+ end;
+
+ TSCBRegisters = record
+ CPUID, {!< CPU ID Base Register }
+ ICSR, {!< Interrupt Control State Register }
+ RESERVED0,
+ AIRCR, {!< Application Interrupt / Reset Control Register }
+ SCR, {!< System Control Register }
+ CCR: dword; {!< Configuration Control Register }
+ RESERVED1 : dword;
+ SHP: array[0..1] of dword; {!< System Handlers Priority Registers (4-7, 8-11, 12-15) }
+ end;
+
+ TSysTickRegisters = record
+ Ctrl,
+ Load,
+ Val,
+ Calib: dword;
+ end;
+
+ TCoreDebugRegisters = record
+ DHCSR,
+ DCRSR,
+ DCRDR,
+ DEMCR: longword;
+ end;
+
+
+var
+ // System Control
+ InterruptControlType: longword absolute (SCS_BASE+$0004);
+ SCB: TSCBRegisters absolute (SCS_BASE+$0D00);
+ SysTick: TSysTickRegisters absolute (SCS_BASE+$0010);
+ NVIC: TNVICRegisters absolute (SCS_BASE+$0100);
+ SoftwareTriggerInterrupt: longword absolute (SCS_BASE+$0000);
+
+ // Core Debug
+ CoreDebug: TCoreDebugRegisters absolute (SCS_BASE+$0DF0);
+
+
+implementation
+
+end.
diff --git a/rtl/freertos/arm/cortexm0_start.inc b/rtl/freertos/arm/cortexm0_start.inc
new file mode 100644
index 0000000000..c5c84c63de
--- /dev/null
+++ b/rtl/freertos/arm/cortexm0_start.inc
@@ -0,0 +1,75 @@
+var
+ _stack_top: record end; external name '_stack_top';
+ _data: record end; external name '_data';
+ _edata: record end; external name '_edata';
+ _text_start: record end; external name '_text_start';
+ _etext: record end; external name '_etext';
+ _bss_start: record end; external name '_bss_start';
+ _bss_end: record end; external name '_bss_end';
+
+procedure Pascalmain; external name 'PASCALMAIN';
+
+procedure HaltProc; assembler; nostackframe; public name'_haltproc';
+asm
+.Lloop:
+ b .Lloop
+end;
+
+procedure Startup; assembler; nostackframe; [public, alias: '_START'];
+asm
+ ldr r1,.L_etext
+ ldr r2,.L_data
+ ldr r3,.L_edata
+ mov r4,#4
+.Lcopyloop:
+// cmp r2,r3
+// ittt ls
+// ldrls r0,[r1],#4
+// strls r0,[r2],#4
+// bls .Lcopyloop
+ ldr r0,[r1]
+ str r0,[r2]
+ add r1,r1,r4
+ add r2,r2,r4
+ cmp r2,r3
+ bls .Lcopyloop
+ // clear onboard ram
+ ldr r1,.L_bss_start
+ ldr r2,.L_bss_end
+ mov r0,#0
+.Lzeroloop:
+ //cmp r1,r2
+ //itt ls
+ //strls r0,[r1],#4
+ //bls .Lzeroloop
+ str r0,[r1]
+ add r1,r1,r4
+ cmp r1,r2
+ bls .Lzeroloop
+
+{$ifdef REMAP_VECTTAB}
+ ldr r0, .Lvtor
+ ldr r1, .Ltext_start
+ str r1, [r0]
+{$endif REMAP_VECTTAB}
+
+ bl PASCALMAIN
+ b HaltProc
+
+.L_bss_start:
+ .long _bss_start
+.L_bss_end:
+ .long _bss_end
+.L_etext:
+ .long _etext
+.L_data:
+ .long _data
+.L_edata:
+ .long _edata
+{$ifdef REMAP_VECTTAB}
+.Lvtor:
+ .long 0xE000ED08
+.Ltext_start:
+ .long _text_start
+{$endif REMAP_VECTTAB}
+end;
diff --git a/rtl/freertos/arm/cortexm3.pp b/rtl/freertos/arm/cortexm3.pp
new file mode 100644
index 0000000000..9fa76d4cfa
--- /dev/null
+++ b/rtl/freertos/arm/cortexm3.pp
@@ -0,0 +1,189 @@
+{
+ System register definitions and utility code for Cortex-M3
+
+ Created by Jeppe Johansen 2012 - jeppe@j-software.dk
+}
+unit cortexm3;
+
+interface
+
+{$PACKRECORDS 2}
+const
+ SCS_BASE = $E000E000;
+ DWT_BASE = $E0001000;
+ FP_BASE = $E0002000;
+ ITM_BASE = $E0000000;
+ TPIU_BASE = $E0040000;
+ ETM_BASE = $E0041000;
+
+type
+
+ TNVICRegisters = record
+ ISER: array[0..7] of longword;
+ reserved0: array[0..23] of longword;
+ ICER: array[0..7] of longword;
+ reserved1: array[0..23] of longword;
+ ISPR: array[0..7] of longword;
+ reserved2: array[0..23] of longword;
+ ICPR: array[0..7] of longword;
+ reserved3: array[0..23] of longword;
+ IABR: array[0..7] of longword;
+ reserved4: array[0..55] of longword;
+ IP: array[0..239] of byte;
+ reserved5: array[0..643] of longword;
+ STIR: longword;
+ end;
+
+ TSCBRegisters = record
+ CPUID, {!< CPU ID Base Register }
+ ICSR, {!< Interrupt Control State Register }
+ VTOR, {!< Vector Table Offset Register }
+ AIRCR, {!< Application Interrupt / Reset Control Register }
+ SCR, {!< System Control Register }
+ CCR: longword; {!< Configuration Control Register }
+ SHP: array[0..11] of byte; {!< System Handlers Priority Registers (4-7, 8-11, 12-15) }
+ SHCSR, {!< System Handler Control and State Register }
+ CFSR, {!< Configurable Fault Status Register }
+ HFSR, {!< Hard Fault Status Register }
+ DFSR, {!< Debug Fault Status Register }
+ MMFAR, {!< Mem Manage Address Register }
+ BFAR, {!< Bus Fault Address Register }
+ AFSR: longword; {!< Auxiliary Fault Status Register }
+ PFR: array[0..1] of longword; {!< Processor Feature Register }
+ DFR, {!< Debug Feature Register }
+ ADR: longword; {!< Auxiliary Feature Register }
+ MMFR: array[0..3] of longword; {!< Memory Model Feature Register }
+ ISAR: array[0..4] of longword; {!< ISA Feature Register }
+ end;
+
+ TSysTickRegisters = record
+ Ctrl,
+ Load,
+ Val,
+ Calib: longword;
+ end;
+
+ TIDRegisters = record
+ PID4_7: array[0..3] of longword;
+ PID0_3: array[0..3] of longword;
+ CID: array[0..3] of longword;
+ end;
+
+ TCoreDebugRegisters = record
+ DHCSR,
+ DCRSR,
+ DCRDR,
+ DEMCR: longword;
+ end;
+
+ TFPRegisters = record
+ Ctrl,
+ Remap: longword;
+ Comp: array[0..7] of longword;
+ res: array[0..987] of longword;
+ ID: TIDRegisters;
+ end;
+
+ TDWTEntry = record
+ Comp,
+ Mask,
+ Func,
+ res: longword;
+ end;
+
+ TDWTRegisters = record
+ Ctrl,
+ CycCnt,
+ CPICnt,
+ ExcCnt,
+ SleepCnt,
+ LSUCnt,
+ FoldCnt,
+ PCSR: longword;
+ Entries: array[0..3] of TDWTEntry;
+ end;
+
+ TITMRegisters = record
+ Stimulus: array[0..31] of longword;
+ res0: array[0..($E00-$7C-4)-1] of byte;
+ TraceEnable: longword;
+ res1: array[0..($E40-$E00-4)-1] of byte;
+ TracePrivilege: longword;
+ res2: array[0..($E80-$E40-4)-1] of byte;
+ TraceControl: longword;
+ res3: array[0..($EF8-$E80-4)-1] of byte;
+ IntegrationWrite,
+ IntegrationRead,
+ IntegrationModeCtrl: longword;
+ res4: array[0..($FB0-$F00-4)-1] of byte;
+ LockAccess,
+ LockStatus: longword;
+ res5: array[0..($FD0-$FB4-4)-1] of byte;
+ ID: TIDRegisters;
+ end;
+
+ TTPIURegisters = record
+ SupportedSyncPortSizes,
+ CurrentSyncPortSize: longword;
+ res0: array[0..($10-$04-4)-1] of byte;
+ AsyncColckPrescaler: longword;
+ res1: array[0..($F0-$10-4)-1] of byte;
+ SelectedPinProtocol: longword;
+ res2: array[0..($100-$F0-4)-1] of byte;
+ TriggerControl: array[0..2] of longword;
+ res3: array[0..($200-$108-4)-1] of byte;
+ TestPattern: array[0..2] of longword;
+ res4: array[0..($300-$208-4)-1] of byte;
+ FormatFlushStatus,
+ FormatControl,
+ FormatSyncCounter: longword;
+ res5: array[0..($EF0-$308-4)-1] of byte;
+ ITATBCTR2: longword;
+ res6: longword;
+ ITATBCTR0: longword;
+ end;
+
+var
+ // System Control
+ InterruptControlType: longword absolute (SCS_BASE+$0004);
+ SCB: TSCBRegisters absolute (SCS_BASE+$0D00);
+ SysTick: TSysTickRegisters absolute (SCS_BASE+$0010);
+ NVIC: TNVICRegisters absolute (SCS_BASE+$0100);
+ SoftwareTriggerInterrupt: longword absolute (SCS_BASE+$0000);
+ SCBID: TIDRegisters absolute (SCS_BASE+$EFD0);
+
+ // Core Debug
+ CoreDebug: TCoreDebugRegisters absolute (SCS_BASE+$0DF0);
+
+ // Flash Patch
+ FP: TFPRegisters absolute FP_BASE;
+
+ DWT: TDWTRegisters absolute DWT_BASE;
+
+ ITM: TITMRegisters absolute ITM_BASE;
+
+ TPIU: TTPIURegisters absolute TPIU_BASE;
+
+type
+ TITM_Port = 0..31;
+
+procedure ITM_SendData(Port: TITM_Port; Data: longword); inline;
+
+implementation
+
+const
+ CoreDebug_DEMCR_TRCENA = $01000000;
+ ITM_TCR_ITMENA = $00000001;
+
+procedure ITM_SendData(Port: TITM_Port; Data: longword);
+begin
+ if ((CoreDebug.DEMCR and CoreDebug_DEMCR_TRCENA) <> 0) and
+ ((itm.TraceControl and ITM_TCR_ITMENA) <> 0) and
+ ((ITM.TraceEnable and (1 shl Port)) <> 0) then
+ begin
+ while ITM.Stimulus[Port] = 0 do;
+ ITM.Stimulus[Port] := Data;
+ end;
+end;
+
+end.
diff --git a/rtl/freertos/arm/cortexm3_start.inc b/rtl/freertos/arm/cortexm3_start.inc
new file mode 100644
index 0000000000..82202b1565
--- /dev/null
+++ b/rtl/freertos/arm/cortexm3_start.inc
@@ -0,0 +1,65 @@
+var
+ _stack_top: record end; external name '_stack_top';
+ _data: record end; external name '_data';
+ _edata: record end; external name '_edata';
+ _text_start: record end; external name '_text_start';
+ _etext: record end; external name '_etext';
+ _bss_start: record end; external name '_bss_start';
+ _bss_end: record end; external name '_bss_end';
+
+procedure Pascalmain; external name 'PASCALMAIN';
+
+procedure HaltProc; assembler; nostackframe; public name'_haltproc';
+asm
+.Lloop:
+ b .Lloop
+end;
+
+procedure Startup; assembler; nostackframe; [public, alias: '_START'];
+asm
+ ldr r1,.L_etext
+ ldr r2,.L_data
+ ldr r3,.L_edata
+.Lcopyloop:
+ cmp r2,r3
+ ittt ls
+ ldrls r0,[r1],#4
+ strls r0,[r2],#4
+ bls .Lcopyloop
+
+ // clear onboard ram
+ ldr r1,.L_bss_start
+ ldr r2,.L_bss_end
+ mov r0,#0
+.Lzeroloop:
+ cmp r1,r2
+ itt ls
+ strls r0,[r1],#4
+ bls .Lzeroloop
+
+{$ifdef REMAP_VECTTAB}
+ ldr r0, .Lvtor
+ ldr r1, .Ltext_start
+ str r1, [r0]
+{$endif REMAP_VECTTAB}
+
+ bl PASCALMAIN
+ b HaltProc
+
+.L_bss_start:
+ .long _bss_start
+.L_bss_end:
+ .long _bss_end
+.L_etext:
+ .long _etext
+.L_data:
+ .long _data
+.L_edata:
+ .long _edata
+{$ifdef REMAP_VECTTAB}
+.Lvtor:
+ .long 0xE000ED08
+.Ltext_start:
+ .long _text_start
+{$endif REMAP_VECTTAB}
+end; \ No newline at end of file
diff --git a/rtl/freertos/arm/cortexm4.pp b/rtl/freertos/arm/cortexm4.pp
new file mode 100644
index 0000000000..aa4685b249
--- /dev/null
+++ b/rtl/freertos/arm/cortexm4.pp
@@ -0,0 +1,189 @@
+{
+ System register definitions and utility code for Cortex-M4
+
+ Created by Jeppe Johansen 2012 - jeppe@j-software.dk
+}
+unit cortexm4;
+
+interface
+
+{$PACKRECORDS 2}
+const
+ SCS_BASE = $E000E000;
+ DWT_BASE = $E0001000;
+ FP_BASE = $E0002000;
+ ITM_BASE = $E0000000;
+ TPIU_BASE = $E0040000;
+ ETM_BASE = $E0041000;
+
+type
+
+ TNVICRegisters = record
+ ISER: array[0..7] of longword;
+ reserved0: array[0..23] of longword;
+ ICER: array[0..7] of longword;
+ reserved1: array[0..23] of longword;
+ ISPR: array[0..7] of longword;
+ reserved2: array[0..23] of longword;
+ ICPR: array[0..7] of longword;
+ reserved3: array[0..23] of longword;
+ IABR: array[0..7] of longword;
+ reserved4: array[0..55] of longword;
+ IP: array[0..239] of byte;
+ reserved5: array[0..643] of longword;
+ STIR: longword;
+ end;
+
+ TSCBRegisters = record
+ CPUID, {!< CPU ID Base Register }
+ ICSR, {!< Interrupt Control State Register }
+ VTOR, {!< Vector Table Offset Register }
+ AIRCR, {!< Application Interrupt / Reset Control Register }
+ SCR, {!< System Control Register }
+ CCR: longword; {!< Configuration Control Register }
+ SHP: array[0..11] of byte; {!< System Handlers Priority Registers (4-7, 8-11, 12-15) }
+ SHCSR, {!< System Handler Control and State Register }
+ CFSR, {!< Configurable Fault Status Register }
+ HFSR, {!< Hard Fault Status Register }
+ DFSR, {!< Debug Fault Status Register }
+ MMFAR, {!< Mem Manage Address Register }
+ BFAR, {!< Bus Fault Address Register }
+ AFSR: longword; {!< Auxiliary Fault Status Register }
+ PFR: array[0..1] of longword; {!< Processor Feature Register }
+ DFR, {!< Debug Feature Register }
+ ADR: longword; {!< Auxiliary Feature Register }
+ MMFR: array[0..3] of longword; {!< Memory Model Feature Register }
+ ISAR: array[0..4] of longword; {!< ISA Feature Register }
+ end;
+
+ TSysTickRegisters = record
+ Ctrl,
+ Load,
+ Val,
+ Calib: longword;
+ end;
+
+ TIDRegisters = record
+ PID4_7: array[0..3] of longword;
+ PID0_3: array[0..3] of longword;
+ CID: array[0..3] of longword;
+ end;
+
+ TCoreDebugRegisters = record
+ DHCSR,
+ DCRSR,
+ DCRDR,
+ DEMCR: longword;
+ end;
+
+ TFPRegisters = record
+ Ctrl,
+ Remap: longword;
+ Comp: array[0..7] of longword;
+ res: array[0..987] of longword;
+ ID: TIDRegisters;
+ end;
+
+ TDWTEntry = record
+ Comp,
+ Mask,
+ Func,
+ res: longword;
+ end;
+
+ TDWTRegisters = record
+ Ctrl,
+ CycCnt,
+ CPICnt,
+ ExcCnt,
+ SleepCnt,
+ LSUCnt,
+ FoldCnt,
+ PCSR: longword;
+ Entries: array[0..3] of TDWTEntry;
+ end;
+
+ TITMRegisters = record
+ Stimulus: array[0..31] of longword;
+ res0: array[0..($E00-$7C-4)-1] of byte;
+ TraceEnable: longword;
+ res1: array[0..($E40-$E00-4)-1] of byte;
+ TracePrivilege: longword;
+ res2: array[0..($E80-$E40-4)-1] of byte;
+ TraceControl: longword;
+ res3: array[0..($EF8-$E80-4)-1] of byte;
+ IntegrationWrite,
+ IntegrationRead,
+ IntegrationModeCtrl: longword;
+ res4: array[0..($FB0-$F00-4)-1] of byte;
+ LockAccess,
+ LockStatus: longword;
+ res5: array[0..($FD0-$FB4-4)-1] of byte;
+ ID: TIDRegisters;
+ end;
+
+ TTPIURegisters = record
+ SupportedSyncPortSizes,
+ CurrentSyncPortSize: longword;
+ res0: array[0..($10-$04-4)-1] of byte;
+ AsyncColckPrescaler: longword;
+ res1: array[0..($F0-$10-4)-1] of byte;
+ SelectedPinProtocol: longword;
+ res2: array[0..($100-$F0-4)-1] of byte;
+ TriggerControl: array[0..2] of longword;
+ res3: array[0..($200-$108-4)-1] of byte;
+ TestPattern: array[0..2] of longword;
+ res4: array[0..($300-$208-4)-1] of byte;
+ FormatFlushStatus,
+ FormatControl,
+ FormatSyncCounter: longword;
+ res5: array[0..($EF0-$308-4)-1] of byte;
+ ITATBCTR2: longword;
+ res6: longword;
+ ITATBCTR0: longword;
+ end;
+
+var
+ // System Control
+ InterruptControlType: longword absolute (SCS_BASE+$0004);
+ SCB: TSCBRegisters absolute (SCS_BASE+$0D00);
+ SysTick: TSysTickRegisters absolute (SCS_BASE+$0010);
+ NVIC: TNVICRegisters absolute (SCS_BASE+$0100);
+ SoftwareTriggerInterrupt: longword absolute (SCS_BASE+$0000);
+ SCBID: TIDRegisters absolute (SCS_BASE+$EFD0);
+
+ // Core Debug
+ CoreDebug: TCoreDebugRegisters absolute (SCS_BASE+$0DF0);
+
+ // Flash Patch
+ FP: TFPRegisters absolute FP_BASE;
+
+ DWT: TDWTRegisters absolute DWT_BASE;
+
+ ITM: TITMRegisters absolute ITM_BASE;
+
+ TPIU: TTPIURegisters absolute TPIU_BASE;
+
+type
+ TITM_Port = 0..31;
+
+procedure ITM_SendData(Port: TITM_Port; Data: longword); inline;
+
+implementation
+
+const
+ CoreDebug_DEMCR_TRCENA = $01000000;
+ ITM_TCR_ITMENA = $00000001;
+
+procedure ITM_SendData(Port: TITM_Port; Data: longword);
+begin
+ if ((CoreDebug.DEMCR and CoreDebug_DEMCR_TRCENA) <> 0) and
+ ((itm.TraceControl and ITM_TCR_ITMENA) <> 0) and
+ ((ITM.TraceEnable and (1 shl Port)) <> 0) then
+ begin
+ while ITM.Stimulus[Port] = 0 do;
+ ITM.Stimulus[Port] := Data;
+ end;
+end;
+
+end.
diff --git a/rtl/freertos/arm/cortexm4f_start.inc b/rtl/freertos/arm/cortexm4f_start.inc
new file mode 100644
index 0000000000..82202b1565
--- /dev/null
+++ b/rtl/freertos/arm/cortexm4f_start.inc
@@ -0,0 +1,65 @@
+var
+ _stack_top: record end; external name '_stack_top';
+ _data: record end; external name '_data';
+ _edata: record end; external name '_edata';
+ _text_start: record end; external name '_text_start';
+ _etext: record end; external name '_etext';
+ _bss_start: record end; external name '_bss_start';
+ _bss_end: record end; external name '_bss_end';
+
+procedure Pascalmain; external name 'PASCALMAIN';
+
+procedure HaltProc; assembler; nostackframe; public name'_haltproc';
+asm
+.Lloop:
+ b .Lloop
+end;
+
+procedure Startup; assembler; nostackframe; [public, alias: '_START'];
+asm
+ ldr r1,.L_etext
+ ldr r2,.L_data
+ ldr r3,.L_edata
+.Lcopyloop:
+ cmp r2,r3
+ ittt ls
+ ldrls r0,[r1],#4
+ strls r0,[r2],#4
+ bls .Lcopyloop
+
+ // clear onboard ram
+ ldr r1,.L_bss_start
+ ldr r2,.L_bss_end
+ mov r0,#0
+.Lzeroloop:
+ cmp r1,r2
+ itt ls
+ strls r0,[r1],#4
+ bls .Lzeroloop
+
+{$ifdef REMAP_VECTTAB}
+ ldr r0, .Lvtor
+ ldr r1, .Ltext_start
+ str r1, [r0]
+{$endif REMAP_VECTTAB}
+
+ bl PASCALMAIN
+ b HaltProc
+
+.L_bss_start:
+ .long _bss_start
+.L_bss_end:
+ .long _bss_end
+.L_etext:
+ .long _etext
+.L_data:
+ .long _data
+.L_edata:
+ .long _edata
+{$ifdef REMAP_VECTTAB}
+.Lvtor:
+ .long 0xE000ED08
+.Ltext_start:
+ .long _text_start
+{$endif REMAP_VECTTAB}
+end; \ No newline at end of file
diff --git a/rtl/freertos/arm/cortexm7.pp b/rtl/freertos/arm/cortexm7.pp
new file mode 100644
index 0000000000..db3c789587
--- /dev/null
+++ b/rtl/freertos/arm/cortexm7.pp
@@ -0,0 +1,256 @@
+{
+ System register definitions and utility code for Cortex-M7
+
+ Created by Jeppe Johansen 2015 - jeppe@j-software.dk
+}
+unit cortexm7;
+
+interface
+
+{$PACKRECORDS C}
+type
+ NVIC_Type = record
+ ISER: array [0..7] of longword; (*!< Offset: 0x000 (R/W) Interrupt Set Enable Register *)
+ RESERVED0: array [0..23] of longword;
+ ICER: array [0..7] of longword; (*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register *)
+ RSERVED1: array [0..23] of longword;
+ ISPR: array [0..7] of longword; (*!< Offset: 0x100 (R/W) Interrupt Set Pending Register *)
+ RESERVED2: array [0..23] of longword;
+ ICPR: array [0..7] of longword; (*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register *)
+ RESERVED3: array [0..23] of longword;
+ IABR: array [0..7] of longword; (*!< Offset: 0x200 (R/W) Interrupt Active bit Register *)
+ RESERVED4: array [0..55] of longword;
+ IP: array [0..239] of byte; (*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) *)
+ RESERVED5: array [0..643] of longword;
+ STIR: longword; (*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register *)
+ end;
+
+ SCB_Type = record
+ CPUID: longword; (*!< Offset: 0x000 (R/ ) CPUID Base Register *)
+ ICSR: longword; (*!< Offset: 0x004 (R/W) Interrupt Control and State Register *)
+ VTOR: longword; (*!< Offset: 0x008 (R/W) Vector Table Offset Register *)
+ AIRCR: longword; (*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register *)
+ SCR: longword; (*!< Offset: 0x010 (R/W) System Control Register *)
+ CCR: longword; (*!< Offset: 0x014 (R/W) Configuration Control Register *)
+ SHPR: array [0..11] of byte; (*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) *)
+ SHCSR: longword; (*!< Offset: 0x024 (R/W) System Handler Control and State Register *)
+ CFSR: longword; (*!< Offset: 0x028 (R/W) Configurable Fault Status Register *)
+ HFSR: longword; (*!< Offset: 0x02C (R/W) HardFault Status Register *)
+ DFSR: longword; (*!< Offset: 0x030 (R/W) Debug Fault Status Register *)
+ MMFAR: longword; (*!< Offset: 0x034 (R/W) MemManage Fault Address Register *)
+ BFAR: longword; (*!< Offset: 0x038 (R/W) BusFault Address Register *)
+ AFSR: longword; (*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register *)
+ ID_PFR: array [0..1] of longword; (*!< Offset: 0x040 (R/ ) Processor Feature Register *)
+ ID_DFR: longword; (*!< Offset: 0x048 (R/ ) Debug Feature Register *)
+ ID_AFR: longword; (*!< Offset: 0x04C (R/ ) Auxiliary Feature Register *)
+ ID_MFR: array [0..3] of longword; (*!< Offset: 0x050 (R/ ) Memory Model Feature Register *)
+ ID_ISAR: array [0..4] of longword; (*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register *)
+ RESERVED0: array [0..0] of longword;
+ CLIDR: longword; (*!< Offset: 0x078 (R/ ) Cache Level ID register *)
+ CTR: longword; (*!< Offset: 0x07C (R/ ) Cache Type register *)
+ CCSIDR: longword; (*!< Offset: 0x080 (R/ ) Cache Size ID Register *)
+ CSSELR: longword; (*!< Offset: 0x084 (R/W) Cache Size Selection Register *)
+ CPACR: longword; (*!< Offset: 0x088 (R/W) Coprocessor Access Control Register *)
+ RESERVED3: array [0..92] of longword;
+ STIR: longword; (*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register *)
+ RESERVED4: array [0..14] of longword;
+ MVFR0: longword; (*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 *)
+ MVFR1: longword; (*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 *)
+ MVFR2: longword; (*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 *)
+ RESERVED5: array [0..0] of longword;
+ ICIALLU: longword; (*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU *)
+ RESERVED6: array [0..0] of longword;
+ ICIMVAU: longword; (*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU *)
+ DCIMVAC: longword; (*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC *)
+ DCISW: longword; (*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way *)
+ DCCMVAU: longword; (*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU *)
+ DCCMVAC: longword; (*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC *)
+ DCCSW: longword; (*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way *)
+ DCCIMVAC: longword; (*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC *)
+ DCCISW: longword; (*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way *)
+ RESERVED7: array [0..5] of longword;
+ ITCMCR: longword; (*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register *)
+ DTCMCR: longword; (*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers *)
+ AHBPCR: longword; (*!< Offset: 0x298 (R/W) AHBP Control Register *)
+ CACR: longword; (*!< Offset: 0x29C (R/W) L1 Cache Control Register *)
+ AHBSCR: longword; (*!< Offset: 0x2A0 (R/W) AHB Slave Control Register *)
+ RESERVED8: array [0..0] of longword;
+ ABFSR: longword; (*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register *)
+ end;
+
+ SCnSCB_Type = record
+ RESERVED0: array [0..0] of longword;
+ ICTR: longword; (*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register *)
+ ACTLR: longword; (*!< Offset: 0x008 (R/W) Auxiliary Control Register *)
+ end;
+
+ SysTick_Type = record
+ CTRL: longword; (*!< Offset: 0x000 (R/W) SysTick Control and Status Register *)
+ LOAD: longword; (*!< Offset: 0x004 (R/W) SysTick Reload Value Register *)
+ VAL: longword; (*!< Offset: 0x008 (R/W) SysTick Current Value Register *)
+ CALIB: longword; (*!< Offset: 0x00C (R/ ) SysTick Calibration Register *)
+ end;
+
+ ITM_Type = record
+ PORT: array [0..31] of record
+ case integer of
+ 0: (u8: byte;); (*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit *)
+ 1: (u16: word;); (*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit *)
+ 2: (u32: longword;); (*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit *)
+ end;
+ (*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers *)
+ RESERVED0: array [0..863] of longword;
+ TER: longword; (*!< Offset: 0xE00 (R/W) ITM Trace Enable Register *)
+ RESERVED1: array [0..14] of longword;
+ TPR: longword; (*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register *)
+ RESERVED2: array [0..14] of longword;
+ TCR: longword; (*!< Offset: 0xE80 (R/W) ITM Trace Control Register *)
+ RESERVED3: array [0..28] of longword;
+ IWR: longword; (*!< Offset: 0xEF8 ( /W) ITM Integration Write Register *)
+ IRR: longword; (*!< Offset: 0xEFC (R/ ) ITM Integration Read Register *)
+ IMCR: longword; (*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register *)
+ RESERVED4: array [0..42] of longword;
+ LAR: longword; (*!< Offset: 0xFB0 ( /W) ITM Lock Access Register *)
+ LSR: longword; (*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register *)
+ RESERVED5: array [0..5] of longword;
+ PID4: longword; (*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 *)
+ PID5: longword; (*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 *)
+ PID6: longword; (*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 *)
+ PID7: longword; (*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 *)
+ PID0: longword; (*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 *)
+ PID1: longword; (*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 *)
+ PID2: longword; (*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 *)
+ PID3: longword; (*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 *)
+ CID0: longword; (*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 *)
+ CID1: longword; (*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 *)
+ CID2: longword; (*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 *)
+ CID3: longword; (*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 *)
+ end;
+
+ DWT_Type = record
+ CTRL: longword; (*!< Offset: 0x000 (R/W) Control Register *)
+ CYCCNT: longword; (*!< Offset: 0x004 (R/W) Cycle Count Register *)
+ CPICNT: longword; (*!< Offset: 0x008 (R/W) CPI Count Register *)
+ EXCCNT: longword; (*!< Offset: 0x00C (R/W) Exception Overhead Count Register *)
+ SLEEPCNT: longword; (*!< Offset: 0x010 (R/W) Sleep Count Register *)
+ LSUCNT: longword; (*!< Offset: 0x014 (R/W) LSU Count Register *)
+ FOLDCNT: longword; (*!< Offset: 0x018 (R/W) Folded-instruction Count Register *)
+ PCSR: longword; (*!< Offset: 0x01C (R/ ) Program Counter Sample Register *)
+ COMP0: longword; (*!< Offset: 0x020 (R/W) Comparator Register 0 *)
+ MASK0: longword; (*!< Offset: 0x024 (R/W) Mask Register 0 *)
+ FUNCTION0: longword; (*!< Offset: 0x028 (R/W) Function Register 0 *)
+ RESERVED0: array [0..0] of longword;
+ COMP1: longword; (*!< Offset: 0x030 (R/W) Comparator Register 1 *)
+ MASK1: longword; (*!< Offset: 0x034 (R/W) Mask Register 1 *)
+ FUNCTION1: longword; (*!< Offset: 0x038 (R/W) Function Register 1 *)
+ RESERVED1: array [0..0] of longword;
+ COMP2: longword; (*!< Offset: 0x040 (R/W) Comparator Register 2 *)
+ MASK2: longword; (*!< Offset: 0x044 (R/W) Mask Register 2 *)
+ FUNCTION2: longword; (*!< Offset: 0x048 (R/W) Function Register 2 *)
+ RESERVED2: array [0..0] of longword;
+ COMP3: longword; (*!< Offset: 0x050 (R/W) Comparator Register 3 *)
+ MASK3: longword; (*!< Offset: 0x054 (R/W) Mask Register 3 *)
+ FUNCTION3: longword; (*!< Offset: 0x058 (R/W) Function Register 3 *)
+ RESERVED3: array [0..980] of longword;
+ LAR: longword; (*!< Offset: 0xFB0 ( W) Lock Access Register *)
+ LSR: longword; (*!< Offset: 0xFB4 (R ) Lock Status Register *)
+ end;
+
+ TPI_Type = record
+ SSPSR: longword; (*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register *)
+ CSPSR: longword; (*!< Offset: 0x004 (R/W) Current Parallel Port Size Register *)
+ RESERVED0: array [0..1] of longword;
+ ACPR: longword; (*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register *)
+ RESERVED1: array [0..54] of longword;
+ SPPR: longword; (*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register *)
+ RESERVED2: array [0..130] of longword;
+ FFSR: longword; (*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register *)
+ FFCR: longword; (*!< Offset: 0x304 (R/W) Formatter and Flush Control Register *)
+ FSCR: longword; (*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register *)
+ RESERVED3: array [0..758] of longword;
+ TRIGGER: longword; (*!< Offset: 0xEE8 (R/ ) TRIGGER *)
+ FIFO0: longword; (*!< Offset: 0xEEC (R/ ) Integration ETM Data *)
+ ITATBCTR2: longword; (*!< Offset: 0xEF0 (R/ ) ITATBCTR2 *)
+ RESERVED4: array [0..0] of longword;
+ ITATBCTR0: longword; (*!< Offset: 0xEF8 (R/ ) ITATBCTR0 *)
+ FIFO1: longword; (*!< Offset: 0xEFC (R/ ) Integration ITM Data *)
+ ITCTRL: longword; (*!< Offset: 0xF00 (R/W) Integration Mode Control *)
+ RESERVED5: array [0..38] of longword;
+ CLAIMSET: longword; (*!< Offset: 0xFA0 (R/W) Claim tag set *)
+ CLAIMCLR: longword; (*!< Offset: 0xFA4 (R/W) Claim tag clear *)
+ RESERVED7: array [0..7] of longword;
+ DEVID: longword; (*!< Offset: 0xFC8 (R/ ) TPIU_DEVID *)
+ DEVTYPE: longword; (*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE *)
+ end;
+
+ MPU_Type = record
+ TYPE_: longword; (*!< Offset: 0x000 (R/ ) MPU Type Register *)
+ CTRL: longword; (*!< Offset: 0x004 (R/W) MPU Control Register *)
+ RNR: longword; (*!< Offset: 0x008 (R/W) MPU Region RNRber Register *)
+ RBAR: longword; (*!< Offset: 0x00C (R/W) MPU Region Base Address Register *)
+ RASR: longword; (*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register *)
+ RBAR_A1: longword; (*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register *)
+ RASR_A1: longword; (*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register *)
+ RBAR_A2: longword; (*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register *)
+ RASR_A2: longword; (*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register *)
+ RBAR_A3: longword; (*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register *)
+ RASR_A3: longword; (*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register *)
+ end;
+
+ FPU_Type = record
+ RESERVED0: array [0..0] of longword;
+ FPCCR: longword; (*!< Offset: 0x004 (R/W) Floating-Point Context Control Register *)
+ FPCAR: longword; (*!< Offset: 0x008 (R/W) Floating-Point Context Address Register *)
+ FPDSCR: longword; (*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register *)
+ MVFR0: longword; (*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 *)
+ MVFR1: longword; (*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 *)
+ MVFR2: longword; (*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 *)
+ end;
+
+ CoreDebug_Type = record
+ DHCSR: longword; (*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register *)
+ DCRSR: longword; (*!< Offset: 0x004 ( /W) Debug Core Register Selector Register *)
+ DCRDR: longword; (*!< Offset: 0x008 (R/W) Debug Core Register Data Register *)
+ DEMCR: longword; (*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register *)
+ end;
+
+(* Memory mapping of Cortex-M4 Hardware *)
+
+const
+ SCS_BASE = $E000E000; (*!< System Control Space Base Address *)
+ ITM_BASE = $E0000000; (*!< ITM Base Address *)
+ DWT_BASE = $E0001000; (*!< DWT Base Address *)
+ TPI_BASE = $E0040000; (*!< TPI Base Address *)
+ CoreDebug_BASE = $E000EDF0; (*!< Core Debug Base Address *)
+ SysTick_BASE = SCS_BASE + $0010; (*!< SysTick Base Address *)
+ NVIC_BASE = SCS_BASE + $0100; (*!< NVIC Base Address *)
+ SCB_BASE = SCS_BASE + $0D00; (*!< System Control Block Base Address *)
+
+var
+ SCnSCB: SCnSCB_Type absolute SCS_BASE; (*!< System control Register not in SCB *)
+ SCB: SCB_Type absolute SCB_BASE; (*!< SCB configuration struct *)
+ SysTick: SysTick_Type absolute SysTick_BASE; (*!< SysTick configuration struct *)
+ NVIC: NVIC_Type absolute NVIC_BASE; (*!< NVIC configuration struct *)
+ ITM: ITM_Type absolute ITM_BASE; (*!< ITM configuration struct *)
+ DWT: DWT_Type absolute DWT_BASE; (*!< DWT configuration struct *)
+ TPI: TPI_Type absolute TPI_BASE; (*!< TPI configuration struct *)
+ CoreDebug: CoreDebug_Type absolute CoreDebug_BASE; (*!< Core Debug configuration struct *)
+
+type
+ TITM_Port = 0..31;
+
+
+procedure ITM_SendData(Port: TITM_Port; Data: char); inline;
+
+implementation
+
+procedure ITM_SendData(Port: TITM_Port; Data: char);
+begin
+ if (((ITM.TCR and 1) <> 0) and ((ITM.TER and 1) <> 0)) then
+ begin
+ while (ITM.PORT[integer(Port)].u32 = 0) do ;
+ ITM.PORT[integer(Port)].u8 := byte(Data);
+ end;
+end;
+
+end.
diff --git a/rtl/freertos/arm/stm32f103xe.pp b/rtl/freertos/arm/stm32f103xe.pp
new file mode 100644
index 0000000000..a7ed045a2b
--- /dev/null
+++ b/rtl/freertos/arm/stm32f103xe.pp
@@ -0,0 +1,924 @@
+unit stm32f103xe;
+interface
+{$PACKRECORDS C}
+{$GOTO ON}
+{$SCOPEDENUMS ON}
+
+type
+ TIRQn_Enum = (
+ NonMaskableInt_IRQn = -14,
+ HardFault_IRQn = -13,
+ MemoryManagement_IRQn = -12,
+ BusFault_IRQn = -11,
+ UsageFault_IRQn = -10,
+ SVCall_IRQn = -5,
+ DebugMonitor_IRQn = -4,
+ PendSV_IRQn = -2,
+ SysTick_IRQn = -1,
+ WWDG_IRQn = 0,
+ PVD_IRQn = 1,
+ TAMPER_IRQn = 2,
+ RTC_IRQn = 3,
+ FLASH_IRQn = 4,
+ RCC_IRQn = 5,
+ EXTI0_IRQn = 6,
+ EXTI1_IRQn = 7,
+ EXTI2_IRQn = 8,
+ EXTI3_IRQn = 9,
+ EXTI4_IRQn = 10,
+ DMA1_Channel1_IRQn = 11,
+ DMA1_Channel2_IRQn = 12,
+ DMA1_Channel3_IRQn = 13,
+ DMA1_Channel4_IRQn = 14,
+ DMA1_Channel5_IRQn = 15,
+ DMA1_Channel6_IRQn = 16,
+ DMA1_Channel7_IRQn = 17,
+ ADC1_2_IRQn = 18,
+ USB_HP_CAN1_TX_IRQn = 19,
+ USB_LP_CAN1_RX0_IRQn = 20,
+ CAN1_RX1_IRQn = 21,
+ CAN1_SCE_IRQn = 22,
+ EXTI9_5_IRQn = 23,
+ TIM1_BRK_IRQn = 24,
+ TIM1_UP_IRQn = 25,
+ TIM1_TRG_COM_IRQn = 26,
+ TIM1_CC_IRQn = 27,
+ TIM2_IRQn = 28,
+ TIM3_IRQn = 29,
+ TIM4_IRQn = 30,
+ I2C1_EV_IRQn = 31,
+ I2C1_ER_IRQn = 32,
+ I2C2_EV_IRQn = 33,
+ I2C2_ER_IRQn = 34,
+ SPI1_IRQn = 35,
+ SPI2_IRQn = 36,
+ USART1_IRQn = 37,
+ USART2_IRQn = 38,
+ USART3_IRQn = 39,
+ EXTI15_10_IRQn = 40,
+ RTC_Alarm_IRQn = 41,
+ USBWakeUp_IRQn = 42,
+ TIM8_BRK_IRQn = 43,
+ TIM8_UP_IRQn = 44,
+ TIM8_TRG_COM_IRQn = 45,
+ TIM8_CC_IRQn = 46,
+ ADC3_IRQn = 47,
+ FSMC_IRQn = 48,
+ SDIO_IRQn = 49,
+ TIM5_IRQn = 50,
+ SPI3_IRQn = 51,
+ UART4_IRQn = 52,
+ UART5_IRQn = 53,
+ TIM6_IRQn = 54,
+ TIM7_IRQn = 55,
+ DMA2_Channel1_IRQn = 56,
+ DMA2_Channel2_IRQn = 57,
+ DMA2_Channel3_IRQn = 58,
+ DMA2_Channel4_5_IRQn = 59
+ );
+
+ TADC_Registers = record
+ SR : longword;
+ CR1 : longword;
+ CR2 : longword;
+ SMPR1 : longword;
+ SMPR2 : longword;
+ JOFR1 : longword;
+ JOFR2 : longword;
+ JOFR3 : longword;
+ JOFR4 : longword;
+ HTR : longword;
+ LTR : longword;
+ SQR1 : longword;
+ SQR2 : longword;
+ SQR3 : longword;
+ JSQR : longword;
+ JDR1 : longword;
+ JDR2 : longword;
+ JDR3 : longword;
+ JDR4 : longword;
+ DR : longword;
+ end;
+
+ TADC_Common_Registers = record
+ SR : longword;
+ CR1 : longword;
+ CR2 : longword;
+ RESERVED : array[0..15] of longword;
+ DR : longword;
+ end;
+
+ TBKP_Registers = record
+ RESERVED0 : longword;
+ DR1 : longword;
+ DR2 : longword;
+ DR3 : longword;
+ DR4 : longword;
+ DR5 : longword;
+ DR6 : longword;
+ DR7 : longword;
+ DR8 : longword;
+ DR9 : longword;
+ DR10 : longword;
+ RTCCR : longword;
+ CR : longword;
+ CSR : longword;
+ RESERVED13 : array[0..1] of longword;
+ DR11 : longword;
+ DR12 : longword;
+ DR13 : longword;
+ DR14 : longword;
+ DR15 : longword;
+ DR16 : longword;
+ DR17 : longword;
+ DR18 : longword;
+ DR19 : longword;
+ DR20 : longword;
+ DR21 : longword;
+ DR22 : longword;
+ DR23 : longword;
+ DR24 : longword;
+ DR25 : longword;
+ DR26 : longword;
+ DR27 : longword;
+ DR28 : longword;
+ DR29 : longword;
+ DR30 : longword;
+ DR31 : longword;
+ DR32 : longword;
+ DR33 : longword;
+ DR34 : longword;
+ DR35 : longword;
+ DR36 : longword;
+ DR37 : longword;
+ DR38 : longword;
+ DR39 : longword;
+ DR40 : longword;
+ DR41 : longword;
+ DR42 : longword;
+ end;
+
+ TCAN_TxMailBox_Registers = record
+ TIR : longword;
+ TDTR : longword;
+ TDLR : longword;
+ TDHR : longword;
+ end;
+
+ TCAN_FIFOMailBox_Registers = record
+ RIR : longword;
+ RDTR : longword;
+ RDLR : longword;
+ RDHR : longword;
+ end;
+
+ TCAN_FilterRegister_Registers = record
+ FR1 : longword;
+ FR2 : longword;
+ end;
+
+ TCAN_Registers = record
+ MCR : longword;
+ MSR : longword;
+ TSR : longword;
+ RF0R : longword;
+ RF1R : longword;
+ IER : longword;
+ ESR : longword;
+ BTR : longword;
+ RESERVED0 : array[0..87] of longword;
+ sTxMailBox : array[0..2] of TCAN_TxMailBox_Registers;
+ sFIFOMailBox : array[0..1] of TCAN_FIFOMailBox_Registers;
+ RESERVED1 : array[0..11] of longword;
+ FMR : longword;
+ FM1R : longword;
+ RESERVED2 : longword;
+ FS1R : longword;
+ RESERVED3 : longword;
+ FFA1R : longword;
+ RESERVED4 : longword;
+ FA1R : longword;
+ RESERVED5 : array[0..7] of longword;
+ sFilterRegister : array[0..13] of TCAN_FilterRegister_Registers;
+ end;
+
+ TCRC_Registers = record
+ DR : longword;
+ IDR : byte;
+ RESERVED0 : byte;
+ RESERVED1 : word;
+ CR : longword;
+ end;
+
+ TDAC_Registers = record
+ CR : longword;
+ SWTRIGR : longword;
+ DHR12R1 : longword;
+ DHR12L1 : longword;
+ DHR8R1 : longword;
+ DHR12R2 : longword;
+ DHR12L2 : longword;
+ DHR8R2 : longword;
+ DHR12RD : longword;
+ DHR12LD : longword;
+ DHR8RD : longword;
+ DOR1 : longword;
+ DOR2 : longword;
+ end;
+
+ TDBGMCU_Registers = record
+ IDCODE : longword;
+ CR : longword;
+ end;
+
+ TDMA_Channel_Registers = record
+ CCR : longword;
+ CNDTR : longword;
+ CPAR : longword;
+ CMAR : longword;
+ end;
+
+ TDMA_Registers = record
+ ISR : longword;
+ IFCR : longword;
+ end;
+
+ TEXTI_Registers = record
+ IMR : longword;
+ EMR : longword;
+ RTSR : longword;
+ FTSR : longword;
+ SWIER : longword;
+ PR : longword;
+ end;
+
+ TFLASH_Registers = record
+ ACR : longword;
+ KEYR : longword;
+ OPTKEYR : longword;
+ SR : longword;
+ CR : longword;
+ AR : longword;
+ RESERVED : longword;
+ OBR : longword;
+ WRPR : longword;
+ end;
+
+ TOB_Registers = record
+ RDP : word;
+ USER : word;
+ Data0 : word;
+ Data1 : word;
+ WRP0 : word;
+ WRP1 : word;
+ WRP2 : word;
+ WRP3 : word;
+ end;
+
+ TFSMC_Bank1_Registers = record
+ BTCR : array[0..7] of longword;
+ end;
+
+ TFSMC_Bank1E_Registers = record
+ BWTR : array[0..6] of longword;
+ end;
+
+ TFSMC_Bank2_3_Registers = record
+ PCR2 : longword;
+ SR2 : longword;
+ PMEM2 : longword;
+ PATT2 : longword;
+ RESERVED0 : longword;
+ ECCR2 : longword;
+ RESERVED1 : longword;
+ RESERVED2 : longword;
+ PCR3 : longword;
+ SR3 : longword;
+ PMEM3 : longword;
+ PATT3 : longword;
+ RESERVED3 : longword;
+ ECCR3 : longword;
+ end;
+
+ TFSMC_Bank4_Registers = record
+ PCR4 : longword;
+ SR4 : longword;
+ PMEM4 : longword;
+ PATT4 : longword;
+ PIO4 : longword;
+ end;
+
+ TGPIO_Registers = record
+ CRL : longword;
+ CRH : longword;
+ IDR : longword;
+ ODR : longword;
+ BSRR : longword;
+ BRR : longword;
+ LCKR : longword;
+ end;
+
+ TAFIO_Registers = record
+ EVCR : longword;
+ MAPR : longword;
+ EXTICR : array[0..3] of longword;
+ RESERVED0 : longword;
+ MAPR2 : longword;
+ end;
+
+ TI2C_Registers = record
+ CR1 : longword;
+ CR2 : longword;
+ OAR1 : longword;
+ OAR2 : longword;
+ DR : longword;
+ SR1 : longword;
+ SR2 : longword;
+ CCR : longword;
+ TRISE : longword;
+ end;
+
+ TIWDG_Registers = record
+ KR : longword;
+ PR : longword;
+ RLR : longword;
+ SR : longword;
+ end;
+
+ TPWR_Registers = record
+ CR : longword;
+ CSR : longword;
+ end;
+
+ TRCC_Registers = record
+ CR : longword;
+ CFGR : longword;
+ CIR : longword;
+ APB2RSTR : longword;
+ APB1RSTR : longword;
+ AHBENR : longword;
+ APB2ENR : longword;
+ APB1ENR : longword;
+ BDCR : longword;
+ CSR : longword;
+ end;
+
+ TRTC_Registers = record
+ CRH : longword;
+ CRL : longword;
+ PRLH : longword;
+ PRLL : longword;
+ DIVH : longword;
+ DIVL : longword;
+ CNTH : longword;
+ CNTL : longword;
+ ALRH : longword;
+ ALRL : longword;
+ end;
+
+ TSDIO_Registers = record
+ POWER : longword;
+ CLKCR : longword;
+ ARG : longword;
+ CMD : longword;
+ RESPCMD : longword;
+ RESP1 : longword;
+ RESP2 : longword;
+ RESP3 : longword;
+ RESP4 : longword;
+ DTIMER : longword;
+ DLEN : longword;
+ DCTRL : longword;
+ DCOUNT : longword;
+ STA : longword;
+ ICR : longword;
+ MASK : longword;
+ RESERVED0 : array[0..1] of longword;
+ FIFOCNT : longword;
+ RESERVED1 : array[0..12] of longword;
+ FIFO : longword;
+ end;
+
+ TSPI_Registers = record
+ CR1 : longword;
+ CR2 : longword;
+ SR : longword;
+ DR : longword;
+ CRCPR : longword;
+ RXCRCR : longword;
+ TXCRCR : longword;
+ I2SCFGR : longword;
+ I2SPR : longword;
+ end;
+
+ TTIM_Registers = record
+ CR1 : longword;
+ CR2 : longword;
+ SMCR : longword;
+ DIER : longword;
+ SR : longword;
+ EGR : longword;
+ CCMR1 : longword;
+ CCMR2 : longword;
+ CCER : longword;
+ CNT : longword;
+ PSC : longword;
+ ARR : longword;
+ RCR : longword;
+ CCR1 : longword;
+ CCR2 : longword;
+ CCR3 : longword;
+ CCR4 : longword;
+ BDTR : longword;
+ DCR : longword;
+ DMAR : longword;
+ &OR : longword;
+ end;
+
+ TUSART_Registers = record
+ SR : longword;
+ DR : longword;
+ BRR : longword;
+ CR1 : longword;
+ CR2 : longword;
+ CR3 : longword;
+ GTPR : longword;
+ end;
+
+ TUSB_Registers = record
+ EP0R : word;
+ RESERVED0 : word;
+ EP1R : word;
+ RESERVED1 : word;
+ EP2R : word;
+ RESERVED2 : word;
+ EP3R : word;
+ RESERVED3 : word;
+ EP4R : word;
+ RESERVED4 : word;
+ EP5R : word;
+ RESERVED5 : word;
+ EP6R : word;
+ RESERVED6 : word;
+ EP7R : word;
+ RESERVED7 : array[0..16] of word;
+ CNTR : word;
+ RESERVED8 : word;
+ ISTR : word;
+ RESERVED9 : word;
+ FNR : word;
+ RESERVEDA : word;
+ DADDR : word;
+ RESERVEDB : word;
+ BTABLE : word;
+ RESERVEDC : word;
+ end;
+
+ TWWDG_Registers = record
+ CR : longword;
+ CFR : longword;
+ SR : longword;
+ end;
+
+const
+ FLASH_BASE = $08000000;
+ SRAM_BASE = $20000000;
+ PERIPH_BASE = $40000000;
+ SRAM_BB_BASE = $22000000;
+ PERIPH_BB_BASE= $42000000;
+ FSMC_BASE = $60000000;
+ FSMC_R_BASE = $A0000000;
+ APB1PERIPH_BASE= PERIPH_BASE;
+ APB2PERIPH_BASE= PERIPH_BASE + $00010000;
+ AHBPERIPH_BASE= PERIPH_BASE + $00020000;
+ TIM2_BASE = APB1PERIPH_BASE + $00000000;
+ TIM3_BASE = APB1PERIPH_BASE + $00000400;
+ TIM4_BASE = APB1PERIPH_BASE + $00000800;
+ TIM5_BASE = APB1PERIPH_BASE + $00000C00;
+ TIM6_BASE = APB1PERIPH_BASE + $00001000;
+ TIM7_BASE = APB1PERIPH_BASE + $00001400;
+ RTC_BASE = APB1PERIPH_BASE + $00002800;
+ WWDG_BASE = APB1PERIPH_BASE + $00002C00;
+ IWDG_BASE = APB1PERIPH_BASE + $00003000;
+ SPI2_BASE = APB1PERIPH_BASE + $00003800;
+ SPI3_BASE = APB1PERIPH_BASE + $00003C00;
+ USART2_BASE = APB1PERIPH_BASE + $00004400;
+ USART3_BASE = APB1PERIPH_BASE + $00004800;
+ UART4_BASE = APB1PERIPH_BASE + $00004C00;
+ UART5_BASE = APB1PERIPH_BASE + $00005000;
+ I2C1_BASE = APB1PERIPH_BASE + $00005400;
+ I2C2_BASE = APB1PERIPH_BASE + $00005800;
+ CAN1_BASE = APB1PERIPH_BASE + $00006400;
+ BKP_BASE = APB1PERIPH_BASE + $00006C00;
+ PWR_BASE = APB1PERIPH_BASE + $00007000;
+ DAC_BASE = APB1PERIPH_BASE + $00007400;
+ AFIO_BASE = APB2PERIPH_BASE + $00000000;
+ EXTI_BASE = APB2PERIPH_BASE + $00000400;
+ GPIOA_BASE = APB2PERIPH_BASE + $00000800;
+ GPIOB_BASE = APB2PERIPH_BASE + $00000C00;
+ GPIOC_BASE = APB2PERIPH_BASE + $00001000;
+ GPIOD_BASE = APB2PERIPH_BASE + $00001400;
+ GPIOE_BASE = APB2PERIPH_BASE + $00001800;
+ GPIOF_BASE = APB2PERIPH_BASE + $00001C00;
+ GPIOG_BASE = APB2PERIPH_BASE + $00002000;
+ ADC1_BASE = APB2PERIPH_BASE + $00002400;
+ ADC2_BASE = APB2PERIPH_BASE + $00002800;
+ TIM1_BASE = APB2PERIPH_BASE + $00002C00;
+ SPI1_BASE = APB2PERIPH_BASE + $00003000;
+ TIM8_BASE = APB2PERIPH_BASE + $00003400;
+ USART1_BASE = APB2PERIPH_BASE + $00003800;
+ ADC3_BASE = APB2PERIPH_BASE + $00003C00;
+ SDIO_BASE = PERIPH_BASE + $00018000;
+ DMA1_BASE = AHBPERIPH_BASE + $00000000;
+ DMA1_Channel1_BASE= AHBPERIPH_BASE + $00000008;
+ DMA1_Channel2_BASE= AHBPERIPH_BASE + $0000001C;
+ DMA1_Channel3_BASE= AHBPERIPH_BASE + $00000030;
+ DMA1_Channel4_BASE= AHBPERIPH_BASE + $00000044;
+ DMA1_Channel5_BASE= AHBPERIPH_BASE + $00000058;
+ DMA1_Channel6_BASE= AHBPERIPH_BASE + $0000006C;
+ DMA1_Channel7_BASE= AHBPERIPH_BASE + $00000080;
+ DMA2_BASE = AHBPERIPH_BASE + $00000400;
+ DMA2_Channel1_BASE= AHBPERIPH_BASE + $00000408;
+ DMA2_Channel2_BASE= AHBPERIPH_BASE + $0000041C;
+ DMA2_Channel3_BASE= AHBPERIPH_BASE + $00000430;
+ DMA2_Channel4_BASE= AHBPERIPH_BASE + $00000444;
+ DMA2_Channel5_BASE= AHBPERIPH_BASE + $00000458;
+ RCC_BASE = AHBPERIPH_BASE + $00001000;
+ CRC_BASE = AHBPERIPH_BASE + $00003000;
+ FLASH_R_BASE = AHBPERIPH_BASE + $00002000;
+ FLASHSIZE_BASE= $1FFFF7E0;
+ UID_BASE = $1FFFF7E8;
+ OB_BASE = $1FFFF800;
+ FSMC_BANK1_R_BASE= FSMC_R_BASE + $00000000;
+ FSMC_BANK1E_R_BASE= FSMC_R_BASE + $00000104;
+ FSMC_BANK2_3_R_BASE= FSMC_R_BASE + $00000060;
+ FSMC_BANK4_R_BASE= FSMC_R_BASE + $000000A0;
+ DBGMCU_BASE = $E0042000;
+ USB_BASE = APB1PERIPH_BASE + $00005C00;
+
+var
+ TIM2 : TTIM_Registers absolute TIM2_BASE;
+ TIM3 : TTIM_Registers absolute TIM3_BASE;
+ TIM4 : TTIM_Registers absolute TIM4_BASE;
+ TIM5 : TTIM_Registers absolute TIM5_BASE;
+ TIM6 : TTIM_Registers absolute TIM6_BASE;
+ TIM7 : TTIM_Registers absolute TIM7_BASE;
+ RTC : TRTC_Registers absolute RTC_BASE;
+ WWDG : TWWDG_Registers absolute WWDG_BASE;
+ IWDG : TIWDG_Registers absolute IWDG_BASE;
+ SPI2 : TSPI_Registers absolute SPI2_BASE;
+ SPI3 : TSPI_Registers absolute SPI3_BASE;
+ USART2 : TUSART_Registers absolute USART2_BASE;
+ USART3 : TUSART_Registers absolute USART3_BASE;
+ UART4 : TUSART_Registers absolute UART4_BASE;
+ UART5 : TUSART_Registers absolute UART5_BASE;
+ I2C1 : TI2C_Registers absolute I2C1_BASE;
+ I2C2 : TI2C_Registers absolute I2C2_BASE;
+ USB : TUSB_Registers absolute USB_BASE;
+ CAN1 : TCAN_Registers absolute CAN1_BASE;
+ BKP : TBKP_Registers absolute BKP_BASE;
+ PWR : TPWR_Registers absolute PWR_BASE;
+ DAC1 : TDAC_Registers absolute DAC_BASE;
+ DAC : TDAC_Registers absolute DAC_BASE;
+ AFIO : TAFIO_Registers absolute AFIO_BASE;
+ EXTI : TEXTI_Registers absolute EXTI_BASE;
+ GPIOA : TGPIO_Registers absolute GPIOA_BASE;
+ GPIOB : TGPIO_Registers absolute GPIOB_BASE;
+ GPIOC : TGPIO_Registers absolute GPIOC_BASE;
+ GPIOD : TGPIO_Registers absolute GPIOD_BASE;
+ GPIOE : TGPIO_Registers absolute GPIOE_BASE;
+ GPIOF : TGPIO_Registers absolute GPIOF_BASE;
+ GPIOG : TGPIO_Registers absolute GPIOG_BASE;
+ ADC1 : TADC_Registers absolute ADC1_BASE;
+ ADC2 : TADC_Registers absolute ADC2_BASE;
+ ADC3 : TADC_Registers absolute ADC3_BASE;
+ ADC12_COMMON : TADC_Common_Registers absolute ADC1_BASE;
+ TIM1 : TTIM_Registers absolute TIM1_BASE;
+ SPI1 : TSPI_Registers absolute SPI1_BASE;
+ TIM8 : TTIM_Registers absolute TIM8_BASE;
+ USART1 : TUSART_Registers absolute USART1_BASE;
+ SDIO : TSDIO_Registers absolute SDIO_BASE;
+ DMA1 : TDMA_Registers absolute DMA1_BASE;
+ DMA2 : TDMA_Registers absolute DMA2_BASE;
+ DMA1_Channel1 : TDMA_Channel_Registers absolute DMA1_Channel1_BASE;
+ DMA1_Channel2 : TDMA_Channel_Registers absolute DMA1_Channel2_BASE;
+ DMA1_Channel3 : TDMA_Channel_Registers absolute DMA1_Channel3_BASE;
+ DMA1_Channel4 : TDMA_Channel_Registers absolute DMA1_Channel4_BASE;
+ DMA1_Channel5 : TDMA_Channel_Registers absolute DMA1_Channel5_BASE;
+ DMA1_Channel6 : TDMA_Channel_Registers absolute DMA1_Channel6_BASE;
+ DMA1_Channel7 : TDMA_Channel_Registers absolute DMA1_Channel7_BASE;
+ DMA2_Channel1 : TDMA_Channel_Registers absolute DMA2_Channel1_BASE;
+ DMA2_Channel2 : TDMA_Channel_Registers absolute DMA2_Channel2_BASE;
+ DMA2_Channel3 : TDMA_Channel_Registers absolute DMA2_Channel3_BASE;
+ DMA2_Channel4 : TDMA_Channel_Registers absolute DMA2_Channel4_BASE;
+ DMA2_Channel5 : TDMA_Channel_Registers absolute DMA2_Channel5_BASE;
+ RCC : TRCC_Registers absolute RCC_BASE;
+ CRC : TCRC_Registers absolute CRC_BASE;
+ FLASH : TFLASH_Registers absolute FLASH_R_BASE;
+ OB : TOB_Registers absolute OB_BASE;
+ FSMC_Bank1 : TFSMC_Bank1_Registers absolute FSMC_BANK1_R_BASE;
+ FSMC_Bank1E : TFSMC_Bank1E_Registers absolute FSMC_BANK1E_R_BASE;
+ FSMC_Bank2_3 : TFSMC_Bank2_3_Registers absolute FSMC_BANK2_3_R_BASE;
+ FSMC_Bank4 : TFSMC_Bank4_Registers absolute FSMC_BANK4_R_BASE;
+ DBGMCU : TDBGMCU_Registers absolute DBGMCU_BASE;
+
+implementation
+
+procedure NonMaskableInt_interrupt; external name 'NonMaskableInt_interrupt';
+procedure HardFault_interrupt; external name 'HardFault_interrupt';
+procedure MemoryManagement_interrupt; external name 'MemoryManagement_interrupt';
+procedure BusFault_interrupt; external name 'BusFault_interrupt';
+procedure UsageFault_interrupt; external name 'UsageFault_interrupt';
+procedure SVCall_interrupt; external name 'SVCall_interrupt';
+procedure DebugMonitor_interrupt; external name 'DebugMonitor_interrupt';
+procedure PendSV_interrupt; external name 'PendSV_interrupt';
+procedure SysTick_interrupt; external name 'SysTick_interrupt';
+procedure WWDG_interrupt; external name 'WWDG_interrupt';
+procedure PVD_interrupt; external name 'PVD_interrupt';
+procedure TAMPER_interrupt; external name 'TAMPER_interrupt';
+procedure RTC_interrupt; external name 'RTC_interrupt';
+procedure FLASH_interrupt; external name 'FLASH_interrupt';
+procedure RCC_interrupt; external name 'RCC_interrupt';
+procedure EXTI0_interrupt; external name 'EXTI0_interrupt';
+procedure EXTI1_interrupt; external name 'EXTI1_interrupt';
+procedure EXTI2_interrupt; external name 'EXTI2_interrupt';
+procedure EXTI3_interrupt; external name 'EXTI3_interrupt';
+procedure EXTI4_interrupt; external name 'EXTI4_interrupt';
+procedure DMA1_Channel1_interrupt; external name 'DMA1_Channel1_interrupt';
+procedure DMA1_Channel2_interrupt; external name 'DMA1_Channel2_interrupt';
+procedure DMA1_Channel3_interrupt; external name 'DMA1_Channel3_interrupt';
+procedure DMA1_Channel4_interrupt; external name 'DMA1_Channel4_interrupt';
+procedure DMA1_Channel5_interrupt; external name 'DMA1_Channel5_interrupt';
+procedure DMA1_Channel6_interrupt; external name 'DMA1_Channel6_interrupt';
+procedure DMA1_Channel7_interrupt; external name 'DMA1_Channel7_interrupt';
+procedure ADC1_2_interrupt; external name 'ADC1_2_interrupt';
+procedure USB_HP_CAN1_TX_interrupt; external name 'USB_HP_CAN1_TX_interrupt';
+procedure USB_LP_CAN1_RX0_interrupt; external name 'USB_LP_CAN1_RX0_interrupt';
+procedure CAN1_RX1_interrupt; external name 'CAN1_RX1_interrupt';
+procedure CAN1_SCE_interrupt; external name 'CAN1_SCE_interrupt';
+procedure EXTI9_5_interrupt; external name 'EXTI9_5_interrupt';
+procedure TIM1_BRK_interrupt; external name 'TIM1_BRK_interrupt';
+procedure TIM1_UP_interrupt; external name 'TIM1_UP_interrupt';
+procedure TIM1_TRG_COM_interrupt; external name 'TIM1_TRG_COM_interrupt';
+procedure TIM1_CC_interrupt; external name 'TIM1_CC_interrupt';
+procedure TIM2_interrupt; external name 'TIM2_interrupt';
+procedure TIM3_interrupt; external name 'TIM3_interrupt';
+procedure TIM4_interrupt; external name 'TIM4_interrupt';
+procedure I2C1_EV_interrupt; external name 'I2C1_EV_interrupt';
+procedure I2C1_ER_interrupt; external name 'I2C1_ER_interrupt';
+procedure I2C2_EV_interrupt; external name 'I2C2_EV_interrupt';
+procedure I2C2_ER_interrupt; external name 'I2C2_ER_interrupt';
+procedure SPI1_interrupt; external name 'SPI1_interrupt';
+procedure SPI2_interrupt; external name 'SPI2_interrupt';
+procedure USART1_interrupt; external name 'USART1_interrupt';
+procedure USART2_interrupt; external name 'USART2_interrupt';
+procedure USART3_interrupt; external name 'USART3_interrupt';
+procedure EXTI15_10_interrupt; external name 'EXTI15_10_interrupt';
+procedure RTC_Alarm_interrupt; external name 'RTC_Alarm_interrupt';
+procedure USBWakeUp_interrupt; external name 'USBWakeUp_interrupt';
+procedure TIM8_BRK_interrupt; external name 'TIM8_BRK_interrupt';
+procedure TIM8_UP_interrupt; external name 'TIM8_UP_interrupt';
+procedure TIM8_TRG_COM_interrupt; external name 'TIM8_TRG_COM_interrupt';
+procedure TIM8_CC_interrupt; external name 'TIM8_CC_interrupt';
+procedure ADC3_interrupt; external name 'ADC3_interrupt';
+procedure FSMC_interrupt; external name 'FSMC_interrupt';
+procedure SDIO_interrupt; external name 'SDIO_interrupt';
+procedure TIM5_interrupt; external name 'TIM5_interrupt';
+procedure SPI3_interrupt; external name 'SPI3_interrupt';
+procedure UART4_interrupt; external name 'UART4_interrupt';
+procedure UART5_interrupt; external name 'UART5_interrupt';
+procedure TIM6_interrupt; external name 'TIM6_interrupt';
+procedure TIM7_interrupt; external name 'TIM7_interrupt';
+procedure DMA2_Channel1_interrupt; external name 'DMA2_Channel1_interrupt';
+procedure DMA2_Channel2_interrupt; external name 'DMA2_Channel2_interrupt';
+procedure DMA2_Channel3_interrupt; external name 'DMA2_Channel3_interrupt';
+procedure DMA2_Channel4_5_interrupt; external name 'DMA2_Channel4_5_interrupt';
+
+
+{$i cortexm3_start.inc}
+
+procedure Vectors; assembler; nostackframe;
+label interrupt_vectors;
+asm
+ .section ".init.interrupt_vectors"
+ interrupt_vectors:
+ .long _stack_top
+ .long Startup
+ .long NonMaskableInt_interrupt
+ .long HardFault_interrupt
+ .long MemoryManagement_interrupt
+ .long BusFault_interrupt
+ .long UsageFault_interrupt
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long SVCall_interrupt
+ .long DebugMonitor_interrupt
+ .long 0
+ .long PendSV_interrupt
+ .long SysTick_interrupt
+ .long WWDG_interrupt
+ .long PVD_interrupt
+ .long TAMPER_interrupt
+ .long RTC_interrupt
+ .long FLASH_interrupt
+ .long RCC_interrupt
+ .long EXTI0_interrupt
+ .long EXTI1_interrupt
+ .long EXTI2_interrupt
+ .long EXTI3_interrupt
+ .long EXTI4_interrupt
+ .long DMA1_Channel1_interrupt
+ .long DMA1_Channel2_interrupt
+ .long DMA1_Channel3_interrupt
+ .long DMA1_Channel4_interrupt
+ .long DMA1_Channel5_interrupt
+ .long DMA1_Channel6_interrupt
+ .long DMA1_Channel7_interrupt
+ .long ADC1_2_interrupt
+ .long USB_HP_CAN1_TX_interrupt
+ .long USB_LP_CAN1_RX0_interrupt
+ .long CAN1_RX1_interrupt
+ .long CAN1_SCE_interrupt
+ .long EXTI9_5_interrupt
+ .long TIM1_BRK_interrupt
+ .long TIM1_UP_interrupt
+ .long TIM1_TRG_COM_interrupt
+ .long TIM1_CC_interrupt
+ .long TIM2_interrupt
+ .long TIM3_interrupt
+ .long TIM4_interrupt
+ .long I2C1_EV_interrupt
+ .long I2C1_ER_interrupt
+ .long I2C2_EV_interrupt
+ .long I2C2_ER_interrupt
+ .long SPI1_interrupt
+ .long SPI2_interrupt
+ .long USART1_interrupt
+ .long USART2_interrupt
+ .long USART3_interrupt
+ .long EXTI15_10_interrupt
+ .long RTC_Alarm_interrupt
+ .long USBWakeUp_interrupt
+ .long TIM8_BRK_interrupt
+ .long TIM8_UP_interrupt
+ .long TIM8_TRG_COM_interrupt
+ .long TIM8_CC_interrupt
+ .long ADC3_interrupt
+ .long FSMC_interrupt
+ .long SDIO_interrupt
+ .long TIM5_interrupt
+ .long SPI3_interrupt
+ .long UART4_interrupt
+ .long UART5_interrupt
+ .long TIM6_interrupt
+ .long TIM7_interrupt
+ .long DMA2_Channel1_interrupt
+ .long DMA2_Channel2_interrupt
+ .long DMA2_Channel3_interrupt
+ .long DMA2_Channel4_5_interrupt
+
+ .weak NonMaskableInt_interrupt
+ .weak HardFault_interrupt
+ .weak MemoryManagement_interrupt
+ .weak BusFault_interrupt
+ .weak UsageFault_interrupt
+ .weak SVCall_interrupt
+ .weak DebugMonitor_interrupt
+ .weak PendSV_interrupt
+ .weak SysTick_interrupt
+ .weak WWDG_interrupt
+ .weak PVD_interrupt
+ .weak TAMPER_interrupt
+ .weak RTC_interrupt
+ .weak FLASH_interrupt
+ .weak RCC_interrupt
+ .weak EXTI0_interrupt
+ .weak EXTI1_interrupt
+ .weak EXTI2_interrupt
+ .weak EXTI3_interrupt
+ .weak EXTI4_interrupt
+ .weak DMA1_Channel1_interrupt
+ .weak DMA1_Channel2_interrupt
+ .weak DMA1_Channel3_interrupt
+ .weak DMA1_Channel4_interrupt
+ .weak DMA1_Channel5_interrupt
+ .weak DMA1_Channel6_interrupt
+ .weak DMA1_Channel7_interrupt
+ .weak ADC1_2_interrupt
+ .weak USB_HP_CAN1_TX_interrupt
+ .weak USB_LP_CAN1_RX0_interrupt
+ .weak CAN1_RX1_interrupt
+ .weak CAN1_SCE_interrupt
+ .weak EXTI9_5_interrupt
+ .weak TIM1_BRK_interrupt
+ .weak TIM1_UP_interrupt
+ .weak TIM1_TRG_COM_interrupt
+ .weak TIM1_CC_interrupt
+ .weak TIM2_interrupt
+ .weak TIM3_interrupt
+ .weak TIM4_interrupt
+ .weak I2C1_EV_interrupt
+ .weak I2C1_ER_interrupt
+ .weak I2C2_EV_interrupt
+ .weak I2C2_ER_interrupt
+ .weak SPI1_interrupt
+ .weak SPI2_interrupt
+ .weak USART1_interrupt
+ .weak USART2_interrupt
+ .weak USART3_interrupt
+ .weak EXTI15_10_interrupt
+ .weak RTC_Alarm_interrupt
+ .weak USBWakeUp_interrupt
+ .weak TIM8_BRK_interrupt
+ .weak TIM8_UP_interrupt
+ .weak TIM8_TRG_COM_interrupt
+ .weak TIM8_CC_interrupt
+ .weak ADC3_interrupt
+ .weak FSMC_interrupt
+ .weak SDIO_interrupt
+ .weak TIM5_interrupt
+ .weak SPI3_interrupt
+ .weak UART4_interrupt
+ .weak UART5_interrupt
+ .weak TIM6_interrupt
+ .weak TIM7_interrupt
+ .weak DMA2_Channel1_interrupt
+ .weak DMA2_Channel2_interrupt
+ .weak DMA2_Channel3_interrupt
+ .weak DMA2_Channel4_5_interrupt
+
+ .set NonMaskableInt_interrupt, Haltproc
+ .set HardFault_interrupt, Haltproc
+ .set MemoryManagement_interrupt, Haltproc
+ .set BusFault_interrupt, Haltproc
+ .set UsageFault_interrupt, Haltproc
+ .set SVCall_interrupt, Haltproc
+ .set DebugMonitor_interrupt, Haltproc
+ .set PendSV_interrupt, Haltproc
+ .set SysTick_interrupt, Haltproc
+ .set WWDG_interrupt, Haltproc
+ .set PVD_interrupt, Haltproc
+ .set TAMPER_interrupt, Haltproc
+ .set RTC_interrupt, Haltproc
+ .set FLASH_interrupt, Haltproc
+ .set RCC_interrupt, Haltproc
+ .set EXTI0_interrupt, Haltproc
+ .set EXTI1_interrupt, Haltproc
+ .set EXTI2_interrupt, Haltproc
+ .set EXTI3_interrupt, Haltproc
+ .set EXTI4_interrupt, Haltproc
+ .set DMA1_Channel1_interrupt, Haltproc
+ .set DMA1_Channel2_interrupt, Haltproc
+ .set DMA1_Channel3_interrupt, Haltproc
+ .set DMA1_Channel4_interrupt, Haltproc
+ .set DMA1_Channel5_interrupt, Haltproc
+ .set DMA1_Channel6_interrupt, Haltproc
+ .set DMA1_Channel7_interrupt, Haltproc
+ .set ADC1_2_interrupt, Haltproc
+ .set USB_HP_CAN1_TX_interrupt, Haltproc
+ .set USB_LP_CAN1_RX0_interrupt, Haltproc
+ .set CAN1_RX1_interrupt, Haltproc
+ .set CAN1_SCE_interrupt, Haltproc
+ .set EXTI9_5_interrupt, Haltproc
+ .set TIM1_BRK_interrupt, Haltproc
+ .set TIM1_UP_interrupt, Haltproc
+ .set TIM1_TRG_COM_interrupt, Haltproc
+ .set TIM1_CC_interrupt, Haltproc
+ .set TIM2_interrupt, Haltproc
+ .set TIM3_interrupt, Haltproc
+ .set TIM4_interrupt, Haltproc
+ .set I2C1_EV_interrupt, Haltproc
+ .set I2C1_ER_interrupt, Haltproc
+ .set I2C2_EV_interrupt, Haltproc
+ .set I2C2_ER_interrupt, Haltproc
+ .set SPI1_interrupt, Haltproc
+ .set SPI2_interrupt, Haltproc
+ .set USART1_interrupt, Haltproc
+ .set USART2_interrupt, Haltproc
+ .set USART3_interrupt, Haltproc
+ .set EXTI15_10_interrupt, Haltproc
+ .set RTC_Alarm_interrupt, Haltproc
+ .set USBWakeUp_interrupt, Haltproc
+ .set TIM8_BRK_interrupt, Haltproc
+ .set TIM8_UP_interrupt, Haltproc
+ .set TIM8_TRG_COM_interrupt, Haltproc
+ .set TIM8_CC_interrupt, Haltproc
+ .set ADC3_interrupt, Haltproc
+ .set FSMC_interrupt, Haltproc
+ .set SDIO_interrupt, Haltproc
+ .set TIM5_interrupt, Haltproc
+ .set SPI3_interrupt, Haltproc
+ .set UART4_interrupt, Haltproc
+ .set UART5_interrupt, Haltproc
+ .set TIM6_interrupt, Haltproc
+ .set TIM7_interrupt, Haltproc
+ .set DMA2_Channel1_interrupt, Haltproc
+ .set DMA2_Channel2_interrupt, Haltproc
+ .set DMA2_Channel3_interrupt, Haltproc
+ .set DMA2_Channel4_5_interrupt, Haltproc
+
+ .text
+ end;
+end.
diff --git a/rtl/freertos/arm/stm32f401xe.pp b/rtl/freertos/arm/stm32f401xe.pp
new file mode 100644
index 0000000000..a55da0b5ae
--- /dev/null
+++ b/rtl/freertos/arm/stm32f401xe.pp
@@ -0,0 +1,891 @@
+unit stm32f401xe;
+interface
+{$PACKRECORDS C}
+{$GOTO ON}
+{$SCOPEDENUMS ON}
+
+type
+ TIRQn_Enum = (
+ NonMaskableInt_IRQn = -14,
+ MemoryManagement_IRQn = -12,
+ BusFault_IRQn = -11,
+ UsageFault_IRQn = -10,
+ SVCall_IRQn = -5,
+ DebugMonitor_IRQn = -4,
+ PendSV_IRQn = -2,
+ SysTick_IRQn = -1,
+ WWDG_IRQn = 0,
+ PVD_IRQn = 1,
+ TAMP_STAMP_IRQn = 2,
+ RTC_WKUP_IRQn = 3,
+ FLASH_IRQn = 4,
+ RCC_IRQn = 5,
+ EXTI0_IRQn = 6,
+ EXTI1_IRQn = 7,
+ EXTI2_IRQn = 8,
+ EXTI3_IRQn = 9,
+ EXTI4_IRQn = 10,
+ DMA1_Stream0_IRQn = 11,
+ DMA1_Stream1_IRQn = 12,
+ DMA1_Stream2_IRQn = 13,
+ DMA1_Stream3_IRQn = 14,
+ DMA1_Stream4_IRQn = 15,
+ DMA1_Stream5_IRQn = 16,
+ DMA1_Stream6_IRQn = 17,
+ ADC_IRQn = 18,
+ EXTI9_5_IRQn = 23,
+ TIM1_BRK_TIM9_IRQn = 24,
+ TIM1_UP_TIM10_IRQn = 25,
+ TIM1_TRG_COM_TIM11_IRQn = 26,
+ TIM1_CC_IRQn = 27,
+ TIM2_IRQn = 28,
+ TIM3_IRQn = 29,
+ TIM4_IRQn = 30,
+ I2C1_EV_IRQn = 31,
+ I2C1_ER_IRQn = 32,
+ I2C2_EV_IRQn = 33,
+ I2C2_ER_IRQn = 34,
+ SPI1_IRQn = 35,
+ SPI2_IRQn = 36,
+ USART1_IRQn = 37,
+ USART2_IRQn = 38,
+ EXTI15_10_IRQn = 40,
+ RTC_Alarm_IRQn = 41,
+ OTG_FS_WKUP_IRQn = 42,
+ DMA1_Stream7_IRQn = 47,
+ SDIO_IRQn = 49,
+ TIM5_IRQn = 50,
+ SPI3_IRQn = 51,
+ DMA2_Stream0_IRQn = 56,
+ DMA2_Stream1_IRQn = 57,
+ DMA2_Stream2_IRQn = 58,
+ DMA2_Stream3_IRQn = 59,
+ DMA2_Stream4_IRQn = 60,
+ OTG_FS_IRQn = 67,
+ DMA2_Stream5_IRQn = 68,
+ DMA2_Stream6_IRQn = 69,
+ DMA2_Stream7_IRQn = 70,
+ USART6_IRQn = 71,
+ I2C3_EV_IRQn = 72,
+ I2C3_ER_IRQn = 73,
+ FPU_IRQn = 81,
+ SPI4_IRQn = 84
+ );
+
+ TADC_Registers = record
+ SR : longword;
+ CR1 : longword;
+ CR2 : longword;
+ SMPR1 : longword;
+ SMPR2 : longword;
+ JOFR1 : longword;
+ JOFR2 : longword;
+ JOFR3 : longword;
+ JOFR4 : longword;
+ HTR : longword;
+ LTR : longword;
+ SQR1 : longword;
+ SQR2 : longword;
+ SQR3 : longword;
+ JSQR : longword;
+ JDR1 : longword;
+ JDR2 : longword;
+ JDR3 : longword;
+ JDR4 : longword;
+ DR : longword;
+ end;
+
+ TADC_Common_Registers = record
+ CSR : longword;
+ CCR : longword;
+ CDR : longword;
+ end;
+
+ TCRC_Registers = record
+ DR : longword;
+ IDR : byte;
+ RESERVED0 : byte;
+ RESERVED1 : word;
+ CR : longword;
+ end;
+
+ TDBGMCU_Registers = record
+ IDCODE : longword;
+ CR : longword;
+ APB1FZ : longword;
+ APB2FZ : longword;
+ end;
+
+ TDMA_Stream_Registers = record
+ CR : longword;
+ NDTR : longword;
+ PAR : longword;
+ M0AR : longword;
+ M1AR : longword;
+ FCR : longword;
+ end;
+
+ TDMA_Registers = record
+ LISR : longword;
+ HISR : longword;
+ LIFCR : longword;
+ HIFCR : longword;
+ end;
+
+ TEXTI_Registers = record
+ IMR : longword;
+ EMR : longword;
+ RTSR : longword;
+ FTSR : longword;
+ SWIER : longword;
+ PR : longword;
+ end;
+
+ TFLASH_Registers = record
+ ACR : longword;
+ KEYR : longword;
+ OPTKEYR : longword;
+ SR : longword;
+ CR : longword;
+ OPTCR : longword;
+ OPTCR1 : longword;
+ end;
+
+ TGPIO_Registers = record
+ MODER : longword;
+ OTYPER : longword;
+ OSPEEDR : longword;
+ PUPDR : longword;
+ IDR : longword;
+ ODR : longword;
+ BSRR : longword;
+ LCKR : longword;
+ AFR : array[0..1] of longword;
+ end;
+
+ TSYSCFG_Registers = record
+ MEMRMP : longword;
+ PMC : longword;
+ EXTICR : array[0..3] of longword;
+ RESERVED : array[0..1] of longword;
+ CMPCR : longword;
+ end;
+
+ TI2C_Registers = record
+ CR1 : longword;
+ CR2 : longword;
+ OAR1 : longword;
+ OAR2 : longword;
+ DR : longword;
+ SR1 : longword;
+ SR2 : longword;
+ CCR : longword;
+ TRISE : longword;
+ FLTR : longword;
+ end;
+
+ TIWDG_Registers = record
+ KR : longword;
+ PR : longword;
+ RLR : longword;
+ SR : longword;
+ end;
+
+ TPWR_Registers = record
+ CR : longword;
+ CSR : longword;
+ end;
+
+ TRCC_Registers = record
+ CR : longword;
+ PLLCFGR : longword;
+ CFGR : longword;
+ CIR : longword;
+ AHB1RSTR : longword;
+ AHB2RSTR : longword;
+ AHB3RSTR : longword;
+ RESERVED0 : longword;
+ APB1RSTR : longword;
+ APB2RSTR : longword;
+ RESERVED1 : array[0..1] of longword;
+ AHB1ENR : longword;
+ AHB2ENR : longword;
+ AHB3ENR : longword;
+ RESERVED2 : longword;
+ APB1ENR : longword;
+ APB2ENR : longword;
+ RESERVED3 : array[0..1] of longword;
+ AHB1LPENR : longword;
+ AHB2LPENR : longword;
+ AHB3LPENR : longword;
+ RESERVED4 : longword;
+ APB1LPENR : longword;
+ APB2LPENR : longword;
+ RESERVED5 : array[0..1] of longword;
+ BDCR : longword;
+ CSR : longword;
+ RESERVED6 : array[0..1] of longword;
+ SSCGR : longword;
+ PLLI2SCFGR : longword;
+ RESERVED7 : longword;
+ DCKCFGR : longword;
+ end;
+
+ TRTC_Registers = record
+ TR : longword;
+ DR : longword;
+ CR : longword;
+ ISR : longword;
+ PRER : longword;
+ WUTR : longword;
+ CALIBR : longword;
+ ALRMAR : longword;
+ ALRMBR : longword;
+ WPR : longword;
+ SSR : longword;
+ SHIFTR : longword;
+ TSTR : longword;
+ TSDR : longword;
+ TSSSR : longword;
+ CALR : longword;
+ TAFCR : longword;
+ ALRMASSR : longword;
+ ALRMBSSR : longword;
+ RESERVED7 : longword;
+ BKP0R : longword;
+ BKP1R : longword;
+ BKP2R : longword;
+ BKP3R : longword;
+ BKP4R : longword;
+ BKP5R : longword;
+ BKP6R : longword;
+ BKP7R : longword;
+ BKP8R : longword;
+ BKP9R : longword;
+ BKP10R : longword;
+ BKP11R : longword;
+ BKP12R : longword;
+ BKP13R : longword;
+ BKP14R : longword;
+ BKP15R : longword;
+ BKP16R : longword;
+ BKP17R : longword;
+ BKP18R : longword;
+ BKP19R : longword;
+ end;
+
+ TSDIO_Registers = record
+ POWER : longword;
+ CLKCR : longword;
+ ARG : longword;
+ CMD : longword;
+ RESPCMD : longword;
+ RESP1 : longword;
+ RESP2 : longword;
+ RESP3 : longword;
+ RESP4 : longword;
+ DTIMER : longword;
+ DLEN : longword;
+ DCTRL : longword;
+ DCOUNT : longword;
+ STA : longword;
+ ICR : longword;
+ MASK : longword;
+ RESERVED0 : array[0..1] of longword;
+ FIFOCNT : longword;
+ RESERVED1 : array[0..12] of longword;
+ FIFO : longword;
+ end;
+
+ TSPI_Registers = record
+ CR1 : longword;
+ CR2 : longword;
+ SR : longword;
+ DR : longword;
+ CRCPR : longword;
+ RXCRCR : longword;
+ TXCRCR : longword;
+ I2SCFGR : longword;
+ I2SPR : longword;
+ end;
+
+ TTIM_Registers = record
+ CR1 : longword;
+ CR2 : longword;
+ SMCR : longword;
+ DIER : longword;
+ SR : longword;
+ EGR : longword;
+ CCMR1 : longword;
+ CCMR2 : longword;
+ CCER : longword;
+ CNT : longword;
+ PSC : longword;
+ ARR : longword;
+ RCR : longword;
+ CCR1 : longword;
+ CCR2 : longword;
+ CCR3 : longword;
+ CCR4 : longword;
+ BDTR : longword;
+ DCR : longword;
+ DMAR : longword;
+ &OR : longword;
+ end;
+
+ TUSART_Registers = record
+ SR : longword;
+ DR : longword;
+ BRR : longword;
+ CR1 : longword;
+ CR2 : longword;
+ CR3 : longword;
+ GTPR : longword;
+ end;
+
+ TWWDG_Registers = record
+ CR : longword;
+ CFR : longword;
+ SR : longword;
+ end;
+
+ TUSB_OTG_Global_Registers = record
+ GOTGCTL : longword;
+ GOTGINT : longword;
+ GAHBCFG : longword;
+ GUSBCFG : longword;
+ GRSTCTL : longword;
+ GINTSTS : longword;
+ GINTMSK : longword;
+ GRXSTSR : longword;
+ GRXSTSP : longword;
+ GRXFSIZ : longword;
+ DIEPTXF0_HNPTXFSIZ : longword;
+ HNPTXSTS : longword;
+ Reserved30 : array[0..1] of longword;
+ GCCFG : longword;
+ CID : longword;
+ Reserved40 : array[0..47] of longword;
+ HPTXFSIZ : longword;
+ DIEPTXF : array[0..14] of longword;
+ end;
+
+ TUSB_OTG_Device_Registers = record
+ DCFG : longword;
+ DCTL : longword;
+ DSTS : longword;
+ Reserved0C : longword;
+ DIEPMSK : longword;
+ DOEPMSK : longword;
+ DAINT : longword;
+ DAINTMSK : longword;
+ Reserved20 : longword;
+ Reserved9 : longword;
+ DVBUSDIS : longword;
+ DVBUSPULSE : longword;
+ DTHRCTL : longword;
+ DIEPEMPMSK : longword;
+ DEACHINT : longword;
+ DEACHMSK : longword;
+ Reserved40 : longword;
+ DINEP1MSK : longword;
+ Reserved44 : array[0..14] of longword;
+ DOUTEP1MSK : longword;
+ end;
+
+ TUSB_OTG_INEndpoint_Registers = record
+ DIEPCTL : longword;
+ Reserved04 : longword;
+ DIEPINT : longword;
+ Reserved0C : longword;
+ DIEPTSIZ : longword;
+ DIEPDMA : longword;
+ DTXFSTS : longword;
+ Reserved18 : longword;
+ end;
+
+ TUSB_OTG_OUTEndpoint_Registers = record
+ DOEPCTL : longword;
+ Reserved04 : longword;
+ DOEPINT : longword;
+ Reserved0C : longword;
+ DOEPTSIZ : longword;
+ DOEPDMA : longword;
+ Reserved18 : array[0..1] of longword;
+ end;
+
+ TUSB_OTG_Host_Registers = record
+ HCFG : longword;
+ HFIR : longword;
+ HFNUM : longword;
+ Reserved40C : longword;
+ HPTXSTS : longword;
+ HAINT : longword;
+ HAINTMSK : longword;
+ end;
+
+ TUSB_OTG_HostChannel_Registers = record
+ HCCHAR : longword;
+ HCSPLT : longword;
+ HCINT : longword;
+ HCINTMSK : longword;
+ HCTSIZ : longword;
+ HCDMA : longword;
+ Reserved : array[0..1] of longword;
+ end;
+
+const
+ FLASH_BASE = $08000000;
+ SRAM1_BASE = $20000000;
+ PERIPH_BASE = $40000000;
+ SRAM1_BB_BASE = $22000000;
+ PERIPH_BB_BASE= $42000000;
+ BKPSRAM_BB_BASE= $42480000;
+ FLASH_OTP_BASE= $1FFF7800;
+ SRAM_BASE = SRAM1_BASE;
+ SRAM_BB_BASE = SRAM1_BB_BASE;
+ APB1PERIPH_BASE= PERIPH_BASE;
+ APB2PERIPH_BASE= PERIPH_BASE + $00010000;
+ AHB1PERIPH_BASE= PERIPH_BASE + $00020000;
+ AHB2PERIPH_BASE= PERIPH_BASE + $10000000;
+ TIM2_BASE = APB1PERIPH_BASE + $0000;
+ TIM3_BASE = APB1PERIPH_BASE + $0400;
+ TIM4_BASE = APB1PERIPH_BASE + $0800;
+ TIM5_BASE = APB1PERIPH_BASE + $0C00;
+ RTC_BASE = APB1PERIPH_BASE + $2800;
+ WWDG_BASE = APB1PERIPH_BASE + $2C00;
+ IWDG_BASE = APB1PERIPH_BASE + $3000;
+ I2S2ext_BASE = APB1PERIPH_BASE + $3400;
+ SPI2_BASE = APB1PERIPH_BASE + $3800;
+ SPI3_BASE = APB1PERIPH_BASE + $3C00;
+ I2S3ext_BASE = APB1PERIPH_BASE + $4000;
+ USART2_BASE = APB1PERIPH_BASE + $4400;
+ I2C1_BASE = APB1PERIPH_BASE + $5400;
+ I2C2_BASE = APB1PERIPH_BASE + $5800;
+ I2C3_BASE = APB1PERIPH_BASE + $5C00;
+ PWR_BASE = APB1PERIPH_BASE + $7000;
+ TIM1_BASE = APB2PERIPH_BASE + $0000;
+ USART1_BASE = APB2PERIPH_BASE + $1000;
+ USART6_BASE = APB2PERIPH_BASE + $1400;
+ ADC1_BASE = APB2PERIPH_BASE + $2000;
+ ADC1_COMMON_BASE= APB2PERIPH_BASE + $2300;
+ ADC_BASE = ADC1_COMMON_BASE;
+ SDIO_BASE = APB2PERIPH_BASE + $2C00;
+ SPI1_BASE = APB2PERIPH_BASE + $3000;
+ SPI4_BASE = APB2PERIPH_BASE + $3400;
+ SYSCFG_BASE = APB2PERIPH_BASE + $3800;
+ EXTI_BASE = APB2PERIPH_BASE + $3C00;
+ TIM9_BASE = APB2PERIPH_BASE + $4000;
+ TIM10_BASE = APB2PERIPH_BASE + $4400;
+ TIM11_BASE = APB2PERIPH_BASE + $4800;
+ GPIOA_BASE = AHB1PERIPH_BASE + $0000;
+ GPIOB_BASE = AHB1PERIPH_BASE + $0400;
+ GPIOC_BASE = AHB1PERIPH_BASE + $0800;
+ GPIOD_BASE = AHB1PERIPH_BASE + $0C00;
+ GPIOE_BASE = AHB1PERIPH_BASE + $1000;
+ GPIOH_BASE = AHB1PERIPH_BASE + $1C00;
+ CRC_BASE = AHB1PERIPH_BASE + $3000;
+ RCC_BASE = AHB1PERIPH_BASE + $3800;
+ FLASH_R_BASE = AHB1PERIPH_BASE + $3C00;
+ DMA1_BASE = AHB1PERIPH_BASE + $6000;
+ DMA1_Stream0_BASE= DMA1_BASE + $010;
+ DMA1_Stream1_BASE= DMA1_BASE + $028;
+ DMA1_Stream2_BASE= DMA1_BASE + $040;
+ DMA1_Stream3_BASE= DMA1_BASE + $058;
+ DMA1_Stream4_BASE= DMA1_BASE + $070;
+ DMA1_Stream5_BASE= DMA1_BASE + $088;
+ DMA1_Stream6_BASE= DMA1_BASE + $0A0;
+ DMA1_Stream7_BASE= DMA1_BASE + $0B8;
+ DMA2_BASE = AHB1PERIPH_BASE + $6400;
+ DMA2_Stream0_BASE= DMA2_BASE + $010;
+ DMA2_Stream1_BASE= DMA2_BASE + $028;
+ DMA2_Stream2_BASE= DMA2_BASE + $040;
+ DMA2_Stream3_BASE= DMA2_BASE + $058;
+ DMA2_Stream4_BASE= DMA2_BASE + $070;
+ DMA2_Stream5_BASE= DMA2_BASE + $088;
+ DMA2_Stream6_BASE= DMA2_BASE + $0A0;
+ DMA2_Stream7_BASE= DMA2_BASE + $0B8;
+ DBGMCU_BASE = $E0042000;
+ USB_OTG_FS_PERIPH_BASE= $50000000;
+ USB_OTG_GLOBAL_BASE= $000;
+ USB_OTG_DEVICE_BASE= $800;
+ USB_OTG_IN_ENDPOINT_BASE= $900;
+ USB_OTG_OUT_ENDPOINT_BASE= $B00;
+ USB_OTG_HOST_BASE= $400;
+ USB_OTG_HOST_PORT_BASE= $440;
+ USB_OTG_HOST_CHANNEL_BASE= $500;
+ USB_OTG_PCGCCTL_BASE= $E00;
+ USB_OTG_FIFO_BASE= $1000;
+ UID_BASE = $1FFF7A10;
+ FLASHSIZE_BASE= $1FFF7A22;
+ PACKAGE_BASE = $1FFF7BF0;
+
+var
+ TIM2 : TTIM_Registers absolute TIM2_BASE;
+ TIM3 : TTIM_Registers absolute TIM3_BASE;
+ TIM4 : TTIM_Registers absolute TIM4_BASE;
+ TIM5 : TTIM_Registers absolute TIM5_BASE;
+ RTC : TRTC_Registers absolute RTC_BASE;
+ WWDG : TWWDG_Registers absolute WWDG_BASE;
+ IWDG : TIWDG_Registers absolute IWDG_BASE;
+ I2S2ext : TSPI_Registers absolute I2S2ext_BASE;
+ SPI2 : TSPI_Registers absolute SPI2_BASE;
+ SPI3 : TSPI_Registers absolute SPI3_BASE;
+ I2S3ext : TSPI_Registers absolute I2S3ext_BASE;
+ USART2 : TUSART_Registers absolute USART2_BASE;
+ I2C1 : TI2C_Registers absolute I2C1_BASE;
+ I2C2 : TI2C_Registers absolute I2C2_BASE;
+ I2C3 : TI2C_Registers absolute I2C3_BASE;
+ PWR : TPWR_Registers absolute PWR_BASE;
+ TIM1 : TTIM_Registers absolute TIM1_BASE;
+ USART1 : TUSART_Registers absolute USART1_BASE;
+ USART6 : TUSART_Registers absolute USART6_BASE;
+ ADC1 : TADC_Registers absolute ADC1_BASE;
+ ADC1_COMMON : TADC_Common_Registers absolute ADC1_COMMON_BASE;
+ SDIO : TSDIO_Registers absolute SDIO_BASE;
+ SPI1 : TSPI_Registers absolute SPI1_BASE;
+ SPI4 : TSPI_Registers absolute SPI4_BASE;
+ SYSCFG : TSYSCFG_Registers absolute SYSCFG_BASE;
+ EXTI : TEXTI_Registers absolute EXTI_BASE;
+ TIM9 : TTIM_Registers absolute TIM9_BASE;
+ TIM10 : TTIM_Registers absolute TIM10_BASE;
+ TIM11 : TTIM_Registers absolute TIM11_BASE;
+ GPIOA : TGPIO_Registers absolute GPIOA_BASE;
+ GPIOB : TGPIO_Registers absolute GPIOB_BASE;
+ GPIOC : TGPIO_Registers absolute GPIOC_BASE;
+ GPIOD : TGPIO_Registers absolute GPIOD_BASE;
+ GPIOE : TGPIO_Registers absolute GPIOE_BASE;
+ GPIOH : TGPIO_Registers absolute GPIOH_BASE;
+ CRC : TCRC_Registers absolute CRC_BASE;
+ RCC : TRCC_Registers absolute RCC_BASE;
+ FLASH : TFLASH_Registers absolute FLASH_R_BASE;
+ DMA1 : TDMA_Registers absolute DMA1_BASE;
+ DMA1_Stream0 : TDMA_Stream_Registers absolute DMA1_Stream0_BASE;
+ DMA1_Stream1 : TDMA_Stream_Registers absolute DMA1_Stream1_BASE;
+ DMA1_Stream2 : TDMA_Stream_Registers absolute DMA1_Stream2_BASE;
+ DMA1_Stream3 : TDMA_Stream_Registers absolute DMA1_Stream3_BASE;
+ DMA1_Stream4 : TDMA_Stream_Registers absolute DMA1_Stream4_BASE;
+ DMA1_Stream5 : TDMA_Stream_Registers absolute DMA1_Stream5_BASE;
+ DMA1_Stream6 : TDMA_Stream_Registers absolute DMA1_Stream6_BASE;
+ DMA1_Stream7 : TDMA_Stream_Registers absolute DMA1_Stream7_BASE;
+ DMA2 : TDMA_Registers absolute DMA2_BASE;
+ DMA2_Stream0 : TDMA_Stream_Registers absolute DMA2_Stream0_BASE;
+ DMA2_Stream1 : TDMA_Stream_Registers absolute DMA2_Stream1_BASE;
+ DMA2_Stream2 : TDMA_Stream_Registers absolute DMA2_Stream2_BASE;
+ DMA2_Stream3 : TDMA_Stream_Registers absolute DMA2_Stream3_BASE;
+ DMA2_Stream4 : TDMA_Stream_Registers absolute DMA2_Stream4_BASE;
+ DMA2_Stream5 : TDMA_Stream_Registers absolute DMA2_Stream5_BASE;
+ DMA2_Stream6 : TDMA_Stream_Registers absolute DMA2_Stream6_BASE;
+ DMA2_Stream7 : TDMA_Stream_Registers absolute DMA2_Stream7_BASE;
+ DBGMCU : TDBGMCU_Registers absolute DBGMCU_BASE;
+
+implementation
+
+procedure NonMaskableInt_interrupt; external name 'NonMaskableInt_interrupt';
+procedure MemoryManagement_interrupt; external name 'MemoryManagement_interrupt';
+procedure BusFault_interrupt; external name 'BusFault_interrupt';
+procedure UsageFault_interrupt; external name 'UsageFault_interrupt';
+procedure SVCall_interrupt; external name 'SVCall_interrupt';
+procedure DebugMonitor_interrupt; external name 'DebugMonitor_interrupt';
+procedure PendSV_interrupt; external name 'PendSV_interrupt';
+procedure SysTick_interrupt; external name 'SysTick_interrupt';
+procedure WWDG_interrupt; external name 'WWDG_interrupt';
+procedure PVD_interrupt; external name 'PVD_interrupt';
+procedure TAMP_STAMP_interrupt; external name 'TAMP_STAMP_interrupt';
+procedure RTC_WKUP_interrupt; external name 'RTC_WKUP_interrupt';
+procedure FLASH_interrupt; external name 'FLASH_interrupt';
+procedure RCC_interrupt; external name 'RCC_interrupt';
+procedure EXTI0_interrupt; external name 'EXTI0_interrupt';
+procedure EXTI1_interrupt; external name 'EXTI1_interrupt';
+procedure EXTI2_interrupt; external name 'EXTI2_interrupt';
+procedure EXTI3_interrupt; external name 'EXTI3_interrupt';
+procedure EXTI4_interrupt; external name 'EXTI4_interrupt';
+procedure DMA1_Stream0_interrupt; external name 'DMA1_Stream0_interrupt';
+procedure DMA1_Stream1_interrupt; external name 'DMA1_Stream1_interrupt';
+procedure DMA1_Stream2_interrupt; external name 'DMA1_Stream2_interrupt';
+procedure DMA1_Stream3_interrupt; external name 'DMA1_Stream3_interrupt';
+procedure DMA1_Stream4_interrupt; external name 'DMA1_Stream4_interrupt';
+procedure DMA1_Stream5_interrupt; external name 'DMA1_Stream5_interrupt';
+procedure DMA1_Stream6_interrupt; external name 'DMA1_Stream6_interrupt';
+procedure ADC_interrupt; external name 'ADC_interrupt';
+procedure EXTI9_5_interrupt; external name 'EXTI9_5_interrupt';
+procedure TIM1_BRK_TIM9_interrupt; external name 'TIM1_BRK_TIM9_interrupt';
+procedure TIM1_UP_TIM10_interrupt; external name 'TIM1_UP_TIM10_interrupt';
+procedure TIM1_TRG_COM_TIM11_interrupt; external name 'TIM1_TRG_COM_TIM11_interrupt';
+procedure TIM1_CC_interrupt; external name 'TIM1_CC_interrupt';
+procedure TIM2_interrupt; external name 'TIM2_interrupt';
+procedure TIM3_interrupt; external name 'TIM3_interrupt';
+procedure TIM4_interrupt; external name 'TIM4_interrupt';
+procedure I2C1_EV_interrupt; external name 'I2C1_EV_interrupt';
+procedure I2C1_ER_interrupt; external name 'I2C1_ER_interrupt';
+procedure I2C2_EV_interrupt; external name 'I2C2_EV_interrupt';
+procedure I2C2_ER_interrupt; external name 'I2C2_ER_interrupt';
+procedure SPI1_interrupt; external name 'SPI1_interrupt';
+procedure SPI2_interrupt; external name 'SPI2_interrupt';
+procedure USART1_interrupt; external name 'USART1_interrupt';
+procedure USART2_interrupt; external name 'USART2_interrupt';
+procedure EXTI15_10_interrupt; external name 'EXTI15_10_interrupt';
+procedure RTC_Alarm_interrupt; external name 'RTC_Alarm_interrupt';
+procedure OTG_FS_WKUP_interrupt; external name 'OTG_FS_WKUP_interrupt';
+procedure DMA1_Stream7_interrupt; external name 'DMA1_Stream7_interrupt';
+procedure SDIO_interrupt; external name 'SDIO_interrupt';
+procedure TIM5_interrupt; external name 'TIM5_interrupt';
+procedure SPI3_interrupt; external name 'SPI3_interrupt';
+procedure DMA2_Stream0_interrupt; external name 'DMA2_Stream0_interrupt';
+procedure DMA2_Stream1_interrupt; external name 'DMA2_Stream1_interrupt';
+procedure DMA2_Stream2_interrupt; external name 'DMA2_Stream2_interrupt';
+procedure DMA2_Stream3_interrupt; external name 'DMA2_Stream3_interrupt';
+procedure DMA2_Stream4_interrupt; external name 'DMA2_Stream4_interrupt';
+procedure OTG_FS_interrupt; external name 'OTG_FS_interrupt';
+procedure DMA2_Stream5_interrupt; external name 'DMA2_Stream5_interrupt';
+procedure DMA2_Stream6_interrupt; external name 'DMA2_Stream6_interrupt';
+procedure DMA2_Stream7_interrupt; external name 'DMA2_Stream7_interrupt';
+procedure USART6_interrupt; external name 'USART6_interrupt';
+procedure I2C3_EV_interrupt; external name 'I2C3_EV_interrupt';
+procedure I2C3_ER_interrupt; external name 'I2C3_ER_interrupt';
+procedure FPU_interrupt; external name 'FPU_interrupt';
+procedure SPI4_interrupt; external name 'SPI4_interrupt';
+
+
+{$i cortexm4f_start.inc}
+
+procedure Vectors; assembler; nostackframe;
+label interrupt_vectors;
+asm
+ .section ".init.interrupt_vectors"
+ interrupt_vectors:
+ .long _stack_top
+ .long Startup
+ .long NonMaskableInt_interrupt
+ .long 0
+ .long MemoryManagement_interrupt
+ .long BusFault_interrupt
+ .long UsageFault_interrupt
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long SVCall_interrupt
+ .long DebugMonitor_interrupt
+ .long 0
+ .long PendSV_interrupt
+ .long SysTick_interrupt
+ .long WWDG_interrupt
+ .long PVD_interrupt
+ .long TAMP_STAMP_interrupt
+ .long RTC_WKUP_interrupt
+ .long FLASH_interrupt
+ .long RCC_interrupt
+ .long EXTI0_interrupt
+ .long EXTI1_interrupt
+ .long EXTI2_interrupt
+ .long EXTI3_interrupt
+ .long EXTI4_interrupt
+ .long DMA1_Stream0_interrupt
+ .long DMA1_Stream1_interrupt
+ .long DMA1_Stream2_interrupt
+ .long DMA1_Stream3_interrupt
+ .long DMA1_Stream4_interrupt
+ .long DMA1_Stream5_interrupt
+ .long DMA1_Stream6_interrupt
+ .long ADC_interrupt
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long EXTI9_5_interrupt
+ .long TIM1_BRK_TIM9_interrupt
+ .long TIM1_UP_TIM10_interrupt
+ .long TIM1_TRG_COM_TIM11_interrupt
+ .long TIM1_CC_interrupt
+ .long TIM2_interrupt
+ .long TIM3_interrupt
+ .long TIM4_interrupt
+ .long I2C1_EV_interrupt
+ .long I2C1_ER_interrupt
+ .long I2C2_EV_interrupt
+ .long I2C2_ER_interrupt
+ .long SPI1_interrupt
+ .long SPI2_interrupt
+ .long USART1_interrupt
+ .long USART2_interrupt
+ .long 0
+ .long EXTI15_10_interrupt
+ .long RTC_Alarm_interrupt
+ .long OTG_FS_WKUP_interrupt
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long DMA1_Stream7_interrupt
+ .long 0
+ .long SDIO_interrupt
+ .long TIM5_interrupt
+ .long SPI3_interrupt
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long DMA2_Stream0_interrupt
+ .long DMA2_Stream1_interrupt
+ .long DMA2_Stream2_interrupt
+ .long DMA2_Stream3_interrupt
+ .long DMA2_Stream4_interrupt
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long OTG_FS_interrupt
+ .long DMA2_Stream5_interrupt
+ .long DMA2_Stream6_interrupt
+ .long DMA2_Stream7_interrupt
+ .long USART6_interrupt
+ .long I2C3_EV_interrupt
+ .long I2C3_ER_interrupt
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long FPU_interrupt
+ .long 0
+ .long 0
+ .long SPI4_interrupt
+
+ .weak NonMaskableInt_interrupt
+ .weak MemoryManagement_interrupt
+ .weak BusFault_interrupt
+ .weak UsageFault_interrupt
+ .weak SVCall_interrupt
+ .weak DebugMonitor_interrupt
+ .weak PendSV_interrupt
+ .weak SysTick_interrupt
+ .weak WWDG_interrupt
+ .weak PVD_interrupt
+ .weak TAMP_STAMP_interrupt
+ .weak RTC_WKUP_interrupt
+ .weak FLASH_interrupt
+ .weak RCC_interrupt
+ .weak EXTI0_interrupt
+ .weak EXTI1_interrupt
+ .weak EXTI2_interrupt
+ .weak EXTI3_interrupt
+ .weak EXTI4_interrupt
+ .weak DMA1_Stream0_interrupt
+ .weak DMA1_Stream1_interrupt
+ .weak DMA1_Stream2_interrupt
+ .weak DMA1_Stream3_interrupt
+ .weak DMA1_Stream4_interrupt
+ .weak DMA1_Stream5_interrupt
+ .weak DMA1_Stream6_interrupt
+ .weak ADC_interrupt
+ .weak EXTI9_5_interrupt
+ .weak TIM1_BRK_TIM9_interrupt
+ .weak TIM1_UP_TIM10_interrupt
+ .weak TIM1_TRG_COM_TIM11_interrupt
+ .weak TIM1_CC_interrupt
+ .weak TIM2_interrupt
+ .weak TIM3_interrupt
+ .weak TIM4_interrupt
+ .weak I2C1_EV_interrupt
+ .weak I2C1_ER_interrupt
+ .weak I2C2_EV_interrupt
+ .weak I2C2_ER_interrupt
+ .weak SPI1_interrupt
+ .weak SPI2_interrupt
+ .weak USART1_interrupt
+ .weak USART2_interrupt
+ .weak EXTI15_10_interrupt
+ .weak RTC_Alarm_interrupt
+ .weak OTG_FS_WKUP_interrupt
+ .weak DMA1_Stream7_interrupt
+ .weak SDIO_interrupt
+ .weak TIM5_interrupt
+ .weak SPI3_interrupt
+ .weak DMA2_Stream0_interrupt
+ .weak DMA2_Stream1_interrupt
+ .weak DMA2_Stream2_interrupt
+ .weak DMA2_Stream3_interrupt
+ .weak DMA2_Stream4_interrupt
+ .weak OTG_FS_interrupt
+ .weak DMA2_Stream5_interrupt
+ .weak DMA2_Stream6_interrupt
+ .weak DMA2_Stream7_interrupt
+ .weak USART6_interrupt
+ .weak I2C3_EV_interrupt
+ .weak I2C3_ER_interrupt
+ .weak FPU_interrupt
+ .weak SPI4_interrupt
+
+ .set NonMaskableInt_interrupt, Haltproc
+ .set MemoryManagement_interrupt, Haltproc
+ .set BusFault_interrupt, Haltproc
+ .set UsageFault_interrupt, Haltproc
+ .set SVCall_interrupt, Haltproc
+ .set DebugMonitor_interrupt, Haltproc
+ .set PendSV_interrupt, Haltproc
+ .set SysTick_interrupt, Haltproc
+ .set WWDG_interrupt, Haltproc
+ .set PVD_interrupt, Haltproc
+ .set TAMP_STAMP_interrupt, Haltproc
+ .set RTC_WKUP_interrupt, Haltproc
+ .set FLASH_interrupt, Haltproc
+ .set RCC_interrupt, Haltproc
+ .set EXTI0_interrupt, Haltproc
+ .set EXTI1_interrupt, Haltproc
+ .set EXTI2_interrupt, Haltproc
+ .set EXTI3_interrupt, Haltproc
+ .set EXTI4_interrupt, Haltproc
+ .set DMA1_Stream0_interrupt, Haltproc
+ .set DMA1_Stream1_interrupt, Haltproc
+ .set DMA1_Stream2_interrupt, Haltproc
+ .set DMA1_Stream3_interrupt, Haltproc
+ .set DMA1_Stream4_interrupt, Haltproc
+ .set DMA1_Stream5_interrupt, Haltproc
+ .set DMA1_Stream6_interrupt, Haltproc
+ .set ADC_interrupt, Haltproc
+ .set EXTI9_5_interrupt, Haltproc
+ .set TIM1_BRK_TIM9_interrupt, Haltproc
+ .set TIM1_UP_TIM10_interrupt, Haltproc
+ .set TIM1_TRG_COM_TIM11_interrupt, Haltproc
+ .set TIM1_CC_interrupt, Haltproc
+ .set TIM2_interrupt, Haltproc
+ .set TIM3_interrupt, Haltproc
+ .set TIM4_interrupt, Haltproc
+ .set I2C1_EV_interrupt, Haltproc
+ .set I2C1_ER_interrupt, Haltproc
+ .set I2C2_EV_interrupt, Haltproc
+ .set I2C2_ER_interrupt, Haltproc
+ .set SPI1_interrupt, Haltproc
+ .set SPI2_interrupt, Haltproc
+ .set USART1_interrupt, Haltproc
+ .set USART2_interrupt, Haltproc
+ .set EXTI15_10_interrupt, Haltproc
+ .set RTC_Alarm_interrupt, Haltproc
+ .set OTG_FS_WKUP_interrupt, Haltproc
+ .set DMA1_Stream7_interrupt, Haltproc
+ .set SDIO_interrupt, Haltproc
+ .set TIM5_interrupt, Haltproc
+ .set SPI3_interrupt, Haltproc
+ .set DMA2_Stream0_interrupt, Haltproc
+ .set DMA2_Stream1_interrupt, Haltproc
+ .set DMA2_Stream2_interrupt, Haltproc
+ .set DMA2_Stream3_interrupt, Haltproc
+ .set DMA2_Stream4_interrupt, Haltproc
+ .set OTG_FS_interrupt, Haltproc
+ .set DMA2_Stream5_interrupt, Haltproc
+ .set DMA2_Stream6_interrupt, Haltproc
+ .set DMA2_Stream7_interrupt, Haltproc
+ .set USART6_interrupt, Haltproc
+ .set I2C3_EV_interrupt, Haltproc
+ .set I2C3_ER_interrupt, Haltproc
+ .set FPU_interrupt, Haltproc
+ .set SPI4_interrupt, Haltproc
+
+ .text
+ end;
+end.
diff --git a/rtl/freertos/arm/stm32g071xx.pp b/rtl/freertos/arm/stm32g071xx.pp
new file mode 100644
index 0000000000..68d3839b92
--- /dev/null
+++ b/rtl/freertos/arm/stm32g071xx.pp
@@ -0,0 +1,760 @@
+unit stm32g071xx;
+interface
+{$PACKRECORDS C}
+{$GOTO ON}
+{$SCOPEDENUMS ON}
+
+type
+ TIRQn_Enum = (
+ NonMaskableInt_IRQn = -14,
+ HardFault_IRQn = -13,
+ SVC_IRQn = -5,
+ PendSV_IRQn = -2,
+ SysTick_IRQn = -1,
+ WWDG_IRQn = 0,
+ PVD_IRQn = 1,
+ RTC_TAMP_IRQn = 2,
+ FLASH_IRQn = 3,
+ RCC_IRQn = 4,
+ EXTI0_1_IRQn = 5,
+ EXTI2_3_IRQn = 6,
+ EXTI4_15_IRQn = 7,
+ UCPD1_2_IRQn = 8,
+ DMA1_Channel1_IRQn = 9,
+ DMA1_Channel2_3_IRQn = 10,
+ DMA1_Ch4_7_DMAMUX1_OVR_IRQn = 11,
+ ADC1_COMP_IRQn = 12,
+ TIM1_BRK_UP_TRG_COM_IRQn = 13,
+ TIM1_CC_IRQn = 14,
+ TIM2_IRQn = 15,
+ TIM3_IRQn = 16,
+ TIM6_DAC_LPTIM1_IRQn = 17,
+ TIM7_LPTIM2_IRQn = 18,
+ TIM14_IRQn = 19,
+ TIM15_IRQn = 20,
+ TIM16_IRQn = 21,
+ TIM17_IRQn = 22,
+ I2C1_IRQn = 23,
+ I2C2_IRQn = 24,
+ SPI1_IRQn = 25,
+ SPI2_IRQn = 26,
+ USART1_IRQn = 27,
+ USART2_IRQn = 28,
+ USART3_4_LPUART1_IRQn = 29,
+ CEC_IRQn = 30
+ );
+
+ TADC_Registers = record
+ ISR : longword;
+ IER : longword;
+ CR : longword;
+ CFGR1 : longword;
+ CFGR2 : longword;
+ SMPR : longword;
+ RESERVED1 : longword;
+ RESERVED2 : longword;
+ TR1 : longword;
+ TR2 : longword;
+ CHSELR : longword;
+ TR3 : longword;
+ RESERVED3 : array[0..3] of longword;
+ DR : longword;
+ RESERVED4 : array[0..22] of longword;
+ AWD2CR : longword;
+ AWD3CR : longword;
+ RESERVED5 : array[0..2] of longword;
+ CALFACT : longword;
+ end;
+
+ TADC_Common_Registers = record
+ CCR : longword;
+ end;
+
+ TCEC_Registers = record
+ CR : longword;
+ CFGR : longword;
+ TXDR : longword;
+ RXDR : longword;
+ ISR : longword;
+ IER : longword;
+ end;
+
+ TCOMP_Registers = record
+ CSR : longword;
+ end;
+
+ TCOMP_Common_Registers = record
+ CSR_ODD : longword;
+ CSR_EVEN : longword;
+ end;
+
+ TCRC_Registers = record
+ DR : longword;
+ IDR : longword;
+ CR : longword;
+ RESERVED1 : longword;
+ INIT : longword;
+ POL : longword;
+ end;
+
+ TDAC_Registers = record
+ CR : longword;
+ SWTRIGR : longword;
+ DHR12R1 : longword;
+ DHR12L1 : longword;
+ DHR8R1 : longword;
+ DHR12R2 : longword;
+ DHR12L2 : longword;
+ DHR8R2 : longword;
+ DHR12RD : longword;
+ DHR12LD : longword;
+ DHR8RD : longword;
+ DOR1 : longword;
+ DOR2 : longword;
+ SR : longword;
+ CCR : longword;
+ MCR : longword;
+ SHSR1 : longword;
+ SHSR2 : longword;
+ SHHR : longword;
+ SHRR : longword;
+ end;
+
+ TDBG_Registers = record
+ IDCODE : longword;
+ CR : longword;
+ APBFZ1 : longword;
+ APBFZ2 : longword;
+ end;
+
+ TDMA_Channel_Registers = record
+ CCR : longword;
+ CNDTR : longword;
+ CPAR : longword;
+ CMAR : longword;
+ end;
+
+ TDMA_Registers = record
+ ISR : longword;
+ IFCR : longword;
+ end;
+
+ TDMAMUX_Channel_Registers = record
+ CCR : longword;
+ end;
+
+ TDMAMUX_ChannelStatus_Registers = record
+ CSR : longword;
+ CFR : longword;
+ end;
+
+ TDMAMUX_RequestGen_Registers = record
+ RGCR : longword;
+ end;
+
+ TDMAMUX_RequestGenStatus_Registers = record
+ RGSR : longword;
+ RGCFR : longword;
+ end;
+
+ TEXTI_Registers = record
+ RTSR1 : longword;
+ FTSR1 : longword;
+ SWIER1 : longword;
+ RPR1 : longword;
+ FPR1 : longword;
+ RESERVED1 : array[0..2] of longword;
+ RESERVED2 : array[0..4] of longword;
+ RESERVED3 : array[0..10] of longword;
+ EXTICR : array[0..3] of longword;
+ RESERVED4 : array[0..3] of longword;
+ IMR1 : longword;
+ EMR1 : longword;
+ RESERVED5 : array[0..1] of longword;
+ IMR2 : longword;
+ EMR2 : longword;
+ end;
+
+ TFLASH_Registers = record
+ ACR : longword;
+ RESERVED1 : longword;
+ KEYR : longword;
+ OPTKEYR : longword;
+ SR : longword;
+ CR : longword;
+ ECCR : longword;
+ RESERVED2 : longword;
+ OPTR : longword;
+ PCROP1ASR : longword;
+ PCROP1AER : longword;
+ WRP1AR : longword;
+ WRP1BR : longword;
+ PCROP1BSR : longword;
+ PCROP1BER : longword;
+ RESERVED3 : array[0..16] of longword;
+ SECR : longword;
+ end;
+
+ TGPIO_Registers = record
+ MODER : longword;
+ OTYPER : longword;
+ OSPEEDR : longword;
+ PUPDR : longword;
+ IDR : longword;
+ ODR : longword;
+ BSRR : longword;
+ LCKR : longword;
+ AFR : array[0..1] of longword;
+ BRR : longword;
+ end;
+
+ TI2C_Registers = record
+ CR1 : longword;
+ CR2 : longword;
+ OAR1 : longword;
+ OAR2 : longword;
+ TIMINGR : longword;
+ TIMEOUTR : longword;
+ ISR : longword;
+ ICR : longword;
+ PECR : longword;
+ RXDR : longword;
+ TXDR : longword;
+ end;
+
+ TIWDG_Registers = record
+ KR : longword;
+ PR : longword;
+ RLR : longword;
+ SR : longword;
+ WINR : longword;
+ end;
+
+ TLPTIM_Registers = record
+ ISR : longword;
+ ICR : longword;
+ IER : longword;
+ CFGR : longword;
+ CR : longword;
+ CMP : longword;
+ ARR : longword;
+ CNT : longword;
+ RESERVED1 : longword;
+ CFGR2 : longword;
+ end;
+
+ TPWR_Registers = record
+ CR1 : longword;
+ CR2 : longword;
+ CR3 : longword;
+ CR4 : longword;
+ SR1 : longword;
+ SR2 : longword;
+ SCR : longword;
+ RESERVED1 : longword;
+ PUCRA : longword;
+ PDCRA : longword;
+ PUCRB : longword;
+ PDCRB : longword;
+ PUCRC : longword;
+ PDCRC : longword;
+ PUCRD : longword;
+ PDCRD : longword;
+ RESERVED2 : longword;
+ RESERVED3 : longword;
+ PUCRF : longword;
+ PDCRF : longword;
+ end;
+
+ TRCC_Registers = record
+ CR : longword;
+ ICSCR : longword;
+ CFGR : longword;
+ PLLCFGR : longword;
+ RESERVED0 : longword;
+ RESERVED1 : longword;
+ CIER : longword;
+ CIFR : longword;
+ CICR : longword;
+ IOPRSTR : longword;
+ AHBRSTR : longword;
+ APBRSTR1 : longword;
+ APBRSTR2 : longword;
+ IOPENR : longword;
+ AHBENR : longword;
+ APBENR1 : longword;
+ APBENR2 : longword;
+ IOPSMENR : longword;
+ AHBSMENR : longword;
+ APBSMENR1 : longword;
+ APBSMENR2 : longword;
+ CCIPR : longword;
+ RESERVED2 : longword;
+ BDCR : longword;
+ CSR : longword;
+ end;
+
+ TRTC_Registers = record
+ TR : longword;
+ DR : longword;
+ SSR : longword;
+ ICSR : longword;
+ PRER : longword;
+ WUTR : longword;
+ CR : longword;
+ RESERVED0 : longword;
+ RESERVED1 : longword;
+ WPR : longword;
+ CALR : longword;
+ SHIFTR : longword;
+ TSTR : longword;
+ TSDR : longword;
+ TSSSR : longword;
+ RESERVED2 : longword;
+ ALRMAR : longword;
+ ALRMASSR : longword;
+ ALRMBR : longword;
+ ALRMBSSR : longword;
+ SR : longword;
+ MISR : longword;
+ RESERVED3 : longword;
+ SCR : longword;
+ &OR : longword;
+ end;
+
+ TTAMP_Registers = record
+ CR1 : longword;
+ CR2 : longword;
+ RESERVED0 : longword;
+ FLTCR : longword;
+ RESERVED1 : array[0..6] of longword;
+ IER : longword;
+ SR : longword;
+ MISR : longword;
+ RESERVED2 : longword;
+ SCR : longword;
+ RESERVED3 : array[0..47] of longword;
+ BKP0R : longword;
+ BKP1R : longword;
+ BKP2R : longword;
+ BKP3R : longword;
+ BKP4R : longword;
+ end;
+
+ TSPI_Registers = record
+ CR1 : longword;
+ CR2 : longword;
+ SR : longword;
+ DR : longword;
+ CRCPR : longword;
+ RXCRCR : longword;
+ TXCRCR : longword;
+ I2SCFGR : longword;
+ I2SPR : longword;
+ end;
+
+ TSYSCFG_Registers = record
+ CFGR1 : longword;
+ RESERVED0 : array[0..4] of longword;
+ CFGR2 : longword;
+ RESERVED1 : array[0..24] of longword;
+ IT_LINE_SR : array[0..31] of longword;
+ end;
+
+ TTIM_Registers = record
+ CR1 : longword;
+ CR2 : longword;
+ SMCR : longword;
+ DIER : longword;
+ SR : longword;
+ EGR : longword;
+ CCMR1 : longword;
+ CCMR2 : longword;
+ CCER : longword;
+ CNT : longword;
+ PSC : longword;
+ ARR : longword;
+ RCR : longword;
+ CCR1 : longword;
+ CCR2 : longword;
+ CCR3 : longword;
+ CCR4 : longword;
+ BDTR : longword;
+ DCR : longword;
+ DMAR : longword;
+ OR1 : longword;
+ CCMR3 : longword;
+ CCR5 : longword;
+ CCR6 : longword;
+ AF1 : longword;
+ AF2 : longword;
+ TISEL : longword;
+ end;
+
+ TUSART_Registers = record
+ CR1 : longword;
+ CR2 : longword;
+ CR3 : longword;
+ BRR : longword;
+ GTPR : longword;
+ RTOR : longword;
+ RQR : longword;
+ ISR : longword;
+ ICR : longword;
+ RDR : longword;
+ TDR : longword;
+ PRESC : longword;
+ end;
+
+ TVREFBUF_Registers = record
+ CSR : longword;
+ CCR : longword;
+ end;
+
+ TWWDG_Registers = record
+ CR : longword;
+ CFR : longword;
+ SR : longword;
+ end;
+
+ TUCPD_Registers = record
+ CFG1 : longword;
+ CFG2 : longword;
+ RESERVED0 : longword;
+ CR : longword;
+ IMR : longword;
+ SR : longword;
+ ICR : longword;
+ TX_ORDSET : longword;
+ TX_PAYSZ : longword;
+ TXDR : longword;
+ RX_ORDSET : longword;
+ RX_PAYSZ : longword;
+ RXDR : longword;
+ RX_ORDEXT1 : longword;
+ RX_ORDEXT2 : longword;
+ end;
+
+const
+ FLASH_BASE = $08000000;
+ SRAM_BASE = $20000000;
+ PERIPH_BASE = $40000000;
+ IOPORT_BASE = $50000000;
+ APBPERIPH_BASE= PERIPH_BASE;
+ AHBPERIPH_BASE= PERIPH_BASE + $00020000;
+ TIM2_BASE = APBPERIPH_BASE + 0;
+ TIM3_BASE = APBPERIPH_BASE + $00000400;
+ TIM6_BASE = APBPERIPH_BASE + $00001000;
+ TIM7_BASE = APBPERIPH_BASE + $00001400;
+ TIM14_BASE = APBPERIPH_BASE + $00002000;
+ RTC_BASE = APBPERIPH_BASE + $00002800;
+ WWDG_BASE = APBPERIPH_BASE + $00002C00;
+ IWDG_BASE = APBPERIPH_BASE + $00003000;
+ SPI2_BASE = APBPERIPH_BASE + $00003800;
+ USART2_BASE = APBPERIPH_BASE + $00004400;
+ USART3_BASE = APBPERIPH_BASE + $00004800;
+ USART4_BASE = APBPERIPH_BASE + $00004C00;
+ I2C1_BASE = APBPERIPH_BASE + $00005400;
+ I2C2_BASE = APBPERIPH_BASE + $00005800;
+ PWR_BASE = APBPERIPH_BASE + $00007000;
+ DAC1_BASE = APBPERIPH_BASE + $00007400;
+ DAC_BASE = APBPERIPH_BASE + $00007400;
+ CEC_BASE = APBPERIPH_BASE + $00007800;
+ LPTIM1_BASE = APBPERIPH_BASE + $00007C00;
+ LPUART1_BASE = APBPERIPH_BASE + $00008000;
+ LPTIM2_BASE = APBPERIPH_BASE + $00009400;
+ UCPD1_BASE = APBPERIPH_BASE + $0000A000;
+ UCPD2_BASE = APBPERIPH_BASE + $0000A400;
+ TAMP_BASE = APBPERIPH_BASE + $0000B000;
+ SYSCFG_BASE = APBPERIPH_BASE + $00010000;
+ VREFBUF_BASE = APBPERIPH_BASE + $00010030;
+ COMP1_BASE = SYSCFG_BASE + $0200;
+ COMP2_BASE = SYSCFG_BASE + $0204;
+ ADC1_BASE = APBPERIPH_BASE + $00012400;
+ ADC1_COMMON_BASE= APBPERIPH_BASE + $00012708;
+ ADC_BASE = ADC1_COMMON_BASE;
+ TIM1_BASE = APBPERIPH_BASE + $00012C00;
+ SPI1_BASE = APBPERIPH_BASE + $00013000;
+ USART1_BASE = APBPERIPH_BASE + $00013800;
+ TIM15_BASE = APBPERIPH_BASE + $00014000;
+ TIM16_BASE = APBPERIPH_BASE + $00014400;
+ TIM17_BASE = APBPERIPH_BASE + $00014800;
+ DBG_BASE = APBPERIPH_BASE + $00015800;
+ DMA1_BASE = AHBPERIPH_BASE;
+ DMAMUX1_BASE = AHBPERIPH_BASE + $00000800;
+ RCC_BASE = AHBPERIPH_BASE + $00001000;
+ EXTI_BASE = AHBPERIPH_BASE + $00001800;
+ FLASH_R_BASE = AHBPERIPH_BASE + $00002000;
+ CRC_BASE = AHBPERIPH_BASE + $00003000;
+ DMA1_Channel1_BASE= DMA1_BASE + $00000008;
+ DMA1_Channel2_BASE= DMA1_BASE + $0000001C;
+ DMA1_Channel3_BASE= DMA1_BASE + $00000030;
+ DMA1_Channel4_BASE= DMA1_BASE + $00000044;
+ DMA1_Channel5_BASE= DMA1_BASE + $00000058;
+ DMA1_Channel6_BASE= DMA1_BASE + $0000006C;
+ DMA1_Channel7_BASE= DMA1_BASE + $00000080;
+ DMAMUX1_Channel0_BASE= DMAMUX1_BASE;
+ DMAMUX1_Channel1_BASE= DMAMUX1_BASE + $00000004;
+ DMAMUX1_Channel2_BASE= DMAMUX1_BASE + $00000008;
+ DMAMUX1_Channel3_BASE= DMAMUX1_BASE + $0000000C;
+ DMAMUX1_Channel4_BASE= DMAMUX1_BASE + $00000010;
+ DMAMUX1_Channel5_BASE= DMAMUX1_BASE + $00000014;
+ DMAMUX1_Channel6_BASE= DMAMUX1_BASE + $00000018;
+ DMAMUX1_RequestGenerator0_BASE= DMAMUX1_BASE + $00000100;
+ DMAMUX1_RequestGenerator1_BASE= DMAMUX1_BASE + $00000104;
+ DMAMUX1_RequestGenerator2_BASE= DMAMUX1_BASE + $00000108;
+ DMAMUX1_RequestGenerator3_BASE= DMAMUX1_BASE + $0000010C;
+ DMAMUX1_ChannelStatus_BASE= DMAMUX1_BASE + $00000080;
+ DMAMUX1_RequestGenStatus_BASE= DMAMUX1_BASE + $00000140;
+ GPIOA_BASE = IOPORT_BASE + $00000000;
+ GPIOB_BASE = IOPORT_BASE + $00000400;
+ GPIOC_BASE = IOPORT_BASE + $00000800;
+ GPIOD_BASE = IOPORT_BASE + $00000C00;
+ GPIOF_BASE = IOPORT_BASE + $00001400;
+ PACKAGE_BASE = $1FFF7500;
+ UID_BASE = $1FFF7590;
+ FLASHSIZE_BASE= $1FFF75E0;
+
+var
+ TIM2 : TTIM_Registers absolute TIM2_BASE;
+ TIM3 : TTIM_Registers absolute TIM3_BASE;
+ TIM6 : TTIM_Registers absolute TIM6_BASE;
+ TIM7 : TTIM_Registers absolute TIM7_BASE;
+ TIM14 : TTIM_Registers absolute TIM14_BASE;
+ RTC : TRTC_Registers absolute RTC_BASE;
+ TAMP : TTAMP_Registers absolute TAMP_BASE;
+ WWDG : TWWDG_Registers absolute WWDG_BASE;
+ IWDG : TIWDG_Registers absolute IWDG_BASE;
+ SPI2 : TSPI_Registers absolute SPI2_BASE;
+ USART2 : TUSART_Registers absolute USART2_BASE;
+ USART3 : TUSART_Registers absolute USART3_BASE;
+ USART4 : TUSART_Registers absolute USART4_BASE;
+ I2C1 : TI2C_Registers absolute I2C1_BASE;
+ I2C2 : TI2C_Registers absolute I2C2_BASE;
+ LPTIM1 : TLPTIM_Registers absolute LPTIM1_BASE;
+ PWR : TPWR_Registers absolute PWR_BASE;
+ RCC : TRCC_Registers absolute RCC_BASE;
+ EXTI : TEXTI_Registers absolute EXTI_BASE;
+ DAC1 : TDAC_Registers absolute DAC1_BASE;
+ DAC : TDAC_Registers absolute DAC_BASE;
+ LPUART1 : TUSART_Registers absolute LPUART1_BASE;
+ LPTIM2 : TLPTIM_Registers absolute LPTIM2_BASE;
+ CEC : TCEC_Registers absolute CEC_BASE;
+ SYSCFG : TSYSCFG_Registers absolute SYSCFG_BASE;
+ VREFBUF : TVREFBUF_Registers absolute VREFBUF_BASE;
+ COMP1 : TCOMP_Registers absolute COMP1_BASE;
+ COMP2 : TCOMP_Registers absolute COMP2_BASE;
+ COMP12_COMMON : TCOMP_Common_Registers absolute COMP1_BASE;
+ TIM1 : TTIM_Registers absolute TIM1_BASE;
+ SPI1 : TSPI_Registers absolute SPI1_BASE;
+ USART1 : TUSART_Registers absolute USART1_BASE;
+ TIM15 : TTIM_Registers absolute TIM15_BASE;
+ TIM16 : TTIM_Registers absolute TIM16_BASE;
+ TIM17 : TTIM_Registers absolute TIM17_BASE;
+ DMA1 : TDMA_Registers absolute DMA1_BASE;
+ FLASH : TFLASH_Registers absolute FLASH_R_BASE;
+ CRC : TCRC_Registers absolute CRC_BASE;
+ GPIOA : TGPIO_Registers absolute GPIOA_BASE;
+ GPIOB : TGPIO_Registers absolute GPIOB_BASE;
+ GPIOC : TGPIO_Registers absolute GPIOC_BASE;
+ GPIOD : TGPIO_Registers absolute GPIOD_BASE;
+ GPIOF : TGPIO_Registers absolute GPIOF_BASE;
+ ADC1 : TADC_Registers absolute ADC1_BASE;
+ ADC1_COMMON : TADC_Common_Registers absolute ADC1_COMMON_BASE;
+ UCPD1 : TUCPD_Registers absolute UCPD1_BASE;
+ UCPD2 : TUCPD_Registers absolute UCPD2_BASE;
+ DMA1_Channel1 : TDMA_Channel_Registers absolute DMA1_Channel1_BASE;
+ DMA1_Channel2 : TDMA_Channel_Registers absolute DMA1_Channel2_BASE;
+ DMA1_Channel3 : TDMA_Channel_Registers absolute DMA1_Channel3_BASE;
+ DMA1_Channel4 : TDMA_Channel_Registers absolute DMA1_Channel4_BASE;
+ DMA1_Channel5 : TDMA_Channel_Registers absolute DMA1_Channel5_BASE;
+ DMA1_Channel6 : TDMA_Channel_Registers absolute DMA1_Channel6_BASE;
+ DMA1_Channel7 : TDMA_Channel_Registers absolute DMA1_Channel7_BASE;
+ DMAMUX1 : TDMAMUX_Channel_Registers absolute DMAMUX1_BASE;
+ DMAMUX1_Channel0: TDMAMUX_Channel_Registers absolute DMAMUX1_Channel0_BASE;
+ DMAMUX1_Channel1: TDMAMUX_Channel_Registers absolute DMAMUX1_Channel1_BASE;
+ DMAMUX1_Channel2: TDMAMUX_Channel_Registers absolute DMAMUX1_Channel2_BASE;
+ DMAMUX1_Channel3: TDMAMUX_Channel_Registers absolute DMAMUX1_Channel3_BASE;
+ DMAMUX1_Channel4: TDMAMUX_Channel_Registers absolute DMAMUX1_Channel4_BASE;
+ DMAMUX1_Channel5: TDMAMUX_Channel_Registers absolute DMAMUX1_Channel5_BASE;
+ DMAMUX1_Channel6: TDMAMUX_Channel_Registers absolute DMAMUX1_Channel6_BASE;
+ DMAMUX1_RequestGenerator0: TDMAMUX_RequestGen_Registers absolute DMAMUX1_RequestGenerator0_BASE;
+ DMAMUX1_RequestGenerator1: TDMAMUX_RequestGen_Registers absolute DMAMUX1_RequestGenerator1_BASE;
+ DMAMUX1_RequestGenerator2: TDMAMUX_RequestGen_Registers absolute DMAMUX1_RequestGenerator2_BASE;
+ DMAMUX1_RequestGenerator3: TDMAMUX_RequestGen_Registers absolute DMAMUX1_RequestGenerator3_BASE;
+ DMAMUX1_ChannelStatus: TDMAMUX_ChannelStatus_Registers absolute DMAMUX1_ChannelStatus_BASE;
+ DMAMUX1_RequestGenStatus: TDMAMUX_RequestGenStatus_Registers absolute DMAMUX1_RequestGenStatus_BASE;
+ DBG : TDBG_Registers absolute DBG_BASE;
+
+implementation
+
+procedure NonMaskableInt_interrupt; external name 'NonMaskableInt_interrupt';
+procedure HardFault_interrupt; external name 'HardFault_interrupt';
+procedure SVC_interrupt; external name 'SVC_interrupt';
+procedure PendSV_interrupt; external name 'PendSV_interrupt';
+procedure SysTick_interrupt; external name 'SysTick_interrupt';
+procedure WWDG_interrupt; external name 'WWDG_interrupt';
+procedure PVD_interrupt; external name 'PVD_interrupt';
+procedure RTC_TAMP_interrupt; external name 'RTC_TAMP_interrupt';
+procedure FLASH_interrupt; external name 'FLASH_interrupt';
+procedure RCC_interrupt; external name 'RCC_interrupt';
+procedure EXTI0_1_interrupt; external name 'EXTI0_1_interrupt';
+procedure EXTI2_3_interrupt; external name 'EXTI2_3_interrupt';
+procedure EXTI4_15_interrupt; external name 'EXTI4_15_interrupt';
+procedure UCPD1_2_interrupt; external name 'UCPD1_2_interrupt';
+procedure DMA1_Channel1_interrupt; external name 'DMA1_Channel1_interrupt';
+procedure DMA1_Channel2_3_interrupt; external name 'DMA1_Channel2_3_interrupt';
+procedure DMA1_Ch4_7_DMAMUX1_OVR_interrupt; external name 'DMA1_Ch4_7_DMAMUX1_OVR_interrupt';
+procedure ADC1_COMP_interrupt; external name 'ADC1_COMP_interrupt';
+procedure TIM1_BRK_UP_TRG_COM_interrupt; external name 'TIM1_BRK_UP_TRG_COM_interrupt';
+procedure TIM1_CC_interrupt; external name 'TIM1_CC_interrupt';
+procedure TIM2_interrupt; external name 'TIM2_interrupt';
+procedure TIM3_interrupt; external name 'TIM3_interrupt';
+procedure TIM6_DAC_LPTIM1_interrupt; external name 'TIM6_DAC_LPTIM1_interrupt';
+procedure TIM7_LPTIM2_interrupt; external name 'TIM7_LPTIM2_interrupt';
+procedure TIM14_interrupt; external name 'TIM14_interrupt';
+procedure TIM15_interrupt; external name 'TIM15_interrupt';
+procedure TIM16_interrupt; external name 'TIM16_interrupt';
+procedure TIM17_interrupt; external name 'TIM17_interrupt';
+procedure I2C1_interrupt; external name 'I2C1_interrupt';
+procedure I2C2_interrupt; external name 'I2C2_interrupt';
+procedure SPI1_interrupt; external name 'SPI1_interrupt';
+procedure SPI2_interrupt; external name 'SPI2_interrupt';
+procedure USART1_interrupt; external name 'USART1_interrupt';
+procedure USART2_interrupt; external name 'USART2_interrupt';
+procedure USART3_4_LPUART1_interrupt; external name 'USART3_4_LPUART1_interrupt';
+procedure CEC_interrupt; external name 'CEC_interrupt';
+
+
+{$i cortexm0_start.inc}
+
+procedure Vectors; assembler; nostackframe;
+label interrupt_vectors;
+asm
+ .section ".init.interrupt_vectors"
+ interrupt_vectors:
+ .long _stack_top
+ .long Startup
+ .long NonMaskableInt_interrupt
+ .long HardFault_interrupt
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long 0
+ .long SVC_interrupt
+ .long 0
+ .long 0
+ .long PendSV_interrupt
+ .long SysTick_interrupt
+ .long WWDG_interrupt
+ .long PVD_interrupt
+ .long RTC_TAMP_interrupt
+ .long FLASH_interrupt
+ .long RCC_interrupt
+ .long EXTI0_1_interrupt
+ .long EXTI2_3_interrupt
+ .long EXTI4_15_interrupt
+ .long UCPD1_2_interrupt
+ .long DMA1_Channel1_interrupt
+ .long DMA1_Channel2_3_interrupt
+ .long DMA1_Ch4_7_DMAMUX1_OVR_interrupt
+ .long ADC1_COMP_interrupt
+ .long TIM1_BRK_UP_TRG_COM_interrupt
+ .long TIM1_CC_interrupt
+ .long TIM2_interrupt
+ .long TIM3_interrupt
+ .long TIM6_DAC_LPTIM1_interrupt
+ .long TIM7_LPTIM2_interrupt
+ .long TIM14_interrupt
+ .long TIM15_interrupt
+ .long TIM16_interrupt
+ .long TIM17_interrupt
+ .long I2C1_interrupt
+ .long I2C2_interrupt
+ .long SPI1_interrupt
+ .long SPI2_interrupt
+ .long USART1_interrupt
+ .long USART2_interrupt
+ .long USART3_4_LPUART1_interrupt
+ .long CEC_interrupt
+
+ .weak NonMaskableInt_interrupt
+ .weak HardFault_interrupt
+ .weak SVC_interrupt
+ .weak PendSV_interrupt
+ .weak SysTick_interrupt
+ .weak WWDG_interrupt
+ .weak PVD_interrupt
+ .weak RTC_TAMP_interrupt
+ .weak FLASH_interrupt
+ .weak RCC_interrupt
+ .weak EXTI0_1_interrupt
+ .weak EXTI2_3_interrupt
+ .weak EXTI4_15_interrupt
+ .weak UCPD1_2_interrupt
+ .weak DMA1_Channel1_interrupt
+ .weak DMA1_Channel2_3_interrupt
+ .weak DMA1_Ch4_7_DMAMUX1_OVR_interrupt
+ .weak ADC1_COMP_interrupt
+ .weak TIM1_BRK_UP_TRG_COM_interrupt
+ .weak TIM1_CC_interrupt
+ .weak TIM2_interrupt
+ .weak TIM3_interrupt
+ .weak TIM6_DAC_LPTIM1_interrupt
+ .weak TIM7_LPTIM2_interrupt
+ .weak TIM14_interrupt
+ .weak TIM15_interrupt
+ .weak TIM16_interrupt
+ .weak TIM17_interrupt
+ .weak I2C1_interrupt
+ .weak I2C2_interrupt
+ .weak SPI1_interrupt
+ .weak SPI2_interrupt
+ .weak USART1_interrupt
+ .weak USART2_interrupt
+ .weak USART3_4_LPUART1_interrupt
+ .weak CEC_interrupt
+
+ .set NonMaskableInt_interrupt, Haltproc
+ .set HardFault_interrupt, Haltproc
+ .set SVC_interrupt, Haltproc
+ .set PendSV_interrupt, Haltproc
+ .set SysTick_interrupt, Haltproc
+ .set WWDG_interrupt, Haltproc
+ .set PVD_interrupt, Haltproc
+ .set RTC_TAMP_interrupt, Haltproc
+ .set FLASH_interrupt, Haltproc
+ .set RCC_interrupt, Haltproc
+ .set EXTI0_1_interrupt, Haltproc
+ .set EXTI2_3_interrupt, Haltproc
+ .set EXTI4_15_interrupt, Haltproc
+ .set UCPD1_2_interrupt, Haltproc
+ .set DMA1_Channel1_interrupt, Haltproc
+ .set DMA1_Channel2_3_interrupt, Haltproc
+ .set DMA1_Ch4_7_DMAMUX1_OVR_interrupt, Haltproc
+ .set ADC1_COMP_interrupt, Haltproc
+ .set TIM1_BRK_UP_TRG_COM_interrupt, Haltproc
+ .set TIM1_CC_interrupt, Haltproc
+ .set TIM2_interrupt, Haltproc
+ .set TIM3_interrupt, Haltproc
+ .set TIM6_DAC_LPTIM1_interrupt, Haltproc
+ .set TIM7_LPTIM2_interrupt, Haltproc
+ .set TIM14_interrupt, Haltproc
+ .set TIM15_interrupt, Haltproc
+ .set TIM16_interrupt, Haltproc
+ .set TIM17_interrupt, Haltproc
+ .set I2C1_interrupt, Haltproc
+ .set I2C2_interrupt, Haltproc
+ .set SPI1_interrupt, Haltproc
+ .set SPI2_interrupt, Haltproc
+ .set USART1_interrupt, Haltproc
+ .set USART2_interrupt, Haltproc
+ .set USART3_4_LPUART1_interrupt, Haltproc
+ .set CEC_interrupt, Haltproc
+
+ .text
+ end;
+end.
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