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authorjonas <jonas@3ad0048d-3df7-0310-abae-a5850022a9f2>2021-04-14 20:56:32 +0000
committerjonas <jonas@3ad0048d-3df7-0310-abae-a5850022a9f2>2021-04-14 20:56:32 +0000
commit8f5cd94a705eca555335027e3044d730b5e6baea (patch)
treeb177bda3c94ba6117160a54ee47a5dc2b03066f7 /compiler
parent688826f09a096666e27928f0ac5791cfdd0f8f8e (diff)
downloadfpc-8f5cd94a705eca555335027e3044d730b5e6baea.tar.gz
* AArch64: fix spilling integer registers to stack offsets that cannot be
encoded directly into the spilling instructions (second part of mantis #38053) git-svn-id: https://svn.freepascal.org/svn/fpc/trunk@49207 3ad0048d-3df7-0310-abae-a5850022a9f2
Diffstat (limited to 'compiler')
-rw-r--r--compiler/aarch64/rgcpu.pas8
1 files changed, 5 insertions, 3 deletions
diff --git a/compiler/aarch64/rgcpu.pas b/compiler/aarch64/rgcpu.pas
index 268c0913fa..875cc04ee9 100644
--- a/compiler/aarch64/rgcpu.pas
+++ b/compiler/aarch64/rgcpu.pas
@@ -1,7 +1,7 @@
{
Copyright (c) 1998-2002 by Florian Klaempfl
- This unit implements the SPARC specific class for the register
+ This unit implements the AArch64 specific class for the register
allocator
This program is free software; you can redistribute it and/or modify
@@ -87,8 +87,8 @@ implementation
begin
helplist:=TAsmList.create;
- if getregtype(tempreg)=R_INTREGISTER then
- hreg:=tempreg
+ if (getregtype(tempreg)=R_INTREGISTER) then
+ hreg:=getregisterinline(helplist,[R_SUBWHOLE])
else
hreg:=cg.getaddressregister(helplist);
@@ -100,6 +100,8 @@ implementation
else
helpins:=spilling_create_store(tempreg,tmpref);
helplist.concat(helpins);
+ if (getregtype(tempreg)=R_INTREGISTER) then
+ ungetregisterinline(helplist,hreg);
add_cpu_interferences(helpins);
list.insertlistafter(pos,helplist);
helplist.free;