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U    rtl/aarch64/mathu.inc
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A    tests/webtbs/tw33607.pp
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U    compiler/aarch64/aasmcpu.pas
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G    compiler/aarch64/aasmcpu.pas
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U    compiler/aarch64/racpugas.pas
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U    compiler/aarch64/racpu.pas
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G    compiler/aarch64/racpugas.pas
U    compiler/rautils.pas
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U    compiler/aarch64/rgcpu.pas
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G    compiler/aarch64/aasmcpu.pas
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git-svn-id: https://svn.freepascal.org/svn/fpc/branches/fixes_3_2@47756 3ad0048d-3df7-0310-abae-a5850022a9f2

1 files changed, 12 insertions, 14 deletions

diff --git a/rtl/aarch64/mathu.inc b/rtl/aarch64/mathu.inc
index 7481703372..469bb49eca 100644
--- a/rtl/aarch64/mathu.inc
+++ b/rtl/aarch64/mathu.inc
@@ -103,21 +103,23 @@ function GetExceptionMask: TFPUExceptionMask;
     if ((fpcr and fpu_ide)=0) then
       result := result+[exDenormalized];
     }
+    { as the fpcr flags might be RAZ, the softfloat exception mask
+      is considered as the authoritative mask }
     result:=softfloat_exception_mask;
   end;
 
 
 function SetExceptionMask(const Mask: TFPUExceptionMask): TFPUExceptionMask;
-  {
   var
     newfpcr: dword;
-  }
   begin
-    { as I am not aware of any hardware exception supporting AArch64 implementation,
-      and else the trapping enable flags are RAZ, work solely with softfloat_exception_mask (FK)
-    }
+    { clear "exception happened" flags }
+    ClearExceptions(false);
     softfloat_exception_mask:=mask;
-    {
+
+    { at least the ThunderX AArch64 support apperently hardware exceptions,
+      so set fpcr correctly, thought it might be WI on most implementations it does not hurt
+    }
     newfpcr:=fpu_exception_mask;
     if exInvalidOp in Mask then
       newfpcr:=newfpcr and not(fpu_ioe);
@@ -131,14 +133,10 @@ function SetExceptionMask(const Mask: TFPUExceptionMask): TFPUExceptionMask;
       newfpcr:=newfpcr and not(fpu_ixe);
     if exDenormalized in Mask then
       newfpcr:=newfpcr and not(fpu_ide);
-    }
-    { clear "exception happened" flags }
-    ClearExceptions(false);
-    { set new exception mask }
-//    setfpcr((getfpcr and not(fpu_exception_mask)) or newfpcr);
-    { unsupported mask bits will remain 0 -> read exception mask again }
-//    result:=GetExceptionMask;
-//    softfloat_exception_mask:=result;
+    setfpcr((getfpcr and not(fpu_exception_mask)) or newfpcr);
+
+    { as the fpcr flags might be RAZ, the softfloat exception mask
+      is considered as the authoritative mask }
     result:=softfloat_exception_mask;
   end;