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* Fix RV32 RTL.laksen2016-10-246-10/+295
* Fixed up RiscV 32bit code generation.laksen2016-10-2424-655/+683
* Add some simple peephole optimizations.laksen2016-10-233-13/+154
* Fix stack alignment for RV64, and fixed size calculation for float parameters.laksen2016-10-2211-117/+280
* Update to use AUIPC+JALR instead of JAL to jump and link.laksen2016-09-037-62/+75
* Make sure to include software mul for rv64i configurationslaksen2016-07-101-1/+2
* Rebuilt makefiles.laksen2016-07-0944-88/+1435
* Update RiscV64 support to 2.1 and privileged standard 1.9.laksen2016-07-0914-17/+184
* Rebuilt makefiles.laksen2016-06-1247-96/+1561
* Add RiscV support in RTL and needed packages.laksen2016-06-1211-52/+389
* Fix problem with set "*" operations getting treated like integer multiplicati...laksen2016-06-122-0/+14
* Merged from trunk.laksen2016-06-1226-636/+743
* Adds some Risc-V support. For now concentrating on Risc-V64 which is the most...laksen2016-06-12135-60/+15359
* Creating branch for RISC-V supportlaksen2016-06-1216357-0/+7265395
* Add pseudo instructions for jump and call instructions to allow jump optimiza...laksen2016-05-287-20/+167
* Enabled do_spill_replace.laksen2016-05-283-8/+80
* Implement some missing things in the SPC32 backend.laksen2016-05-155-6/+124
* Merged with trunk, and fixed some errors introduced.laksen2016-05-154376-268500/+1077083
* Added more checks to allow compiler to build from scratch.laksen2015-11-213-9/+14
* Make r12 one of the first registers to be allocated since it's volatile.laksen2015-10-263-6/+65
* Add some support for shifterop parameters in intrinsics.laksen2015-10-266-31/+47
* Add missing ARM instructions to simple peephole optimizations and spilling_ge...laksen2015-07-072-2/+11
* + add header to automatically created files which informs that the file is cr...florian2015-06-217-2/+44
* + rule to create arm intrinsic filesflorian2015-06-212-1/+18
* Add support for SSE and related MMX intrinsics. Still needs a lot of polishin...laksen2015-06-2129-28/+1952
* Add initial support for table generated ARM intrinsics functionslaksen2015-06-2016-8/+2302
* Initial branch for target specific intrinsic functionslaksen2015-06-2015792-0/+6989625
* Merged from trunk.laksen2015-03-1333-265/+498
* Disable internal assemblerlaksen2015-03-132-5/+5
* Make MRS and MSR use the right encoding on Thumb architectures.laksen2015-03-084-7/+7
* Fix off by 1 error in assembler reader which prevented B instructions from be...laksen2015-03-081-1/+1
* Merged from trunklaksen2015-03-081432-9957/+54571
* Rebase to trunk revisionlaksen2015-02-151231-27808/+230906
* Disable internal linker in arm-linux for now.laksen2015-02-151-1/+1
* Use proper syntax when emitting UAL VFP instructions for all postfix types.laksen2015-02-012-4/+11
* Add missing size postfix to VNEG VFP instruction.laksen2015-01-111-2/+9
* Use proper relocation type for Thumb-2 BLX.laksen2015-01-112-2/+8
* Add MSR/MRS for ARMv6M/7M.laksen2015-01-024-3/+89
* Merged from recent trunk.laksen2015-01-01119-3109/+8239
* Add CPSxx instructions, and some missing FPA instructions.laksen2015-01-014-1/+201
* Add FPA support.laksen2015-01-018-24/+705
* Fix SWI as a pseudo instruction.laksen2014-12-294-33/+326
* Fix an issue with local BLX branches not being turned into BL branches.laksen2014-12-281-0/+5
* Refactor and secure some immediate operand encodings.laksen2014-12-285-54/+109
* Fix some encoding bugs in ARM modes. Mostly shifts and signindex errors.laksen2014-12-281-7/+27
* Fix encoding of shifterops for ARM dataprocessing instructions.laksen2014-12-281-1/+1
* Fix some warnings about unitialized variables.laksen2014-12-271-2/+5
* Add Neg as a pseudo instruction, and fix RRX pseudo code expansion.laksen2014-12-276-75/+224
* Add support for TBB/TBH instructions.laksen2014-12-275-15/+386
* Add missing NOP, and B instruction forms.laksen2014-12-279-30/+107
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