| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | * patch Christo Crause: Use LDS for 8 bit references, resolves #38173 | florian | 2020-12-06 | 1 | -3/+12 |
| * | * do not reuse a loaded reference for avrtiny in a_op_const*, resolves #38142 | florian | 2020-11-27 | 1 | -3/+10 |
| * | * patch by Marģers to unify internal error numbers, resolves #37888 | florian | 2020-10-13 | 1 | -10/+10 |
| * | + introduce tcgobj.a_loadfpu_reg_intreg | florian | 2020-09-12 | 1 | -1/+19 |
| * | Disable limitation of handling of negative shift values, can be enalbed agai... | pierre | 2020-08-04 | 1 | -1/+1 |
| * | * tcg.a_load_cgparaloc_ref: Always enable SHR instruction for mips/mipsel CPUs | pierre | 2020-07-14 | 1 | -1/+4 |
| * | * rename the ARM/AArch64-Darwin targets to ARM/AArch64-iOS | jonas | 2020-07-10 | 1 | -1/+1 |
| * | * handle LOC_(C)SUBSETREG/REF in second_NegNot_assign | nickysn | 2020-05-07 | 1 | -11/+95 |
| * | * don't convert the fpu parameters size from tcgsize -> int -> float_tcgsize | jonas | 2020-05-02 | 1 | -132/+149 |
| * | * support floating point parameters split over multiple locations, including | jonas | 2020-05-01 | 1 | -43/+50 |
| * | * do not use an extra register in tcginlinenode.second_IncDec if not needed | florian | 2020-04-29 | 1 | -0/+1 |
| * | * fix warnings in cgobj for 8-bit alu cpus | nickysn | 2020-04-19 | 1 | -0/+4 |
| * | * treat all Z80 registers as 8-bit | nickysn | 2020-04-03 | 1 | -2/+0 |
| * | * changed the ifndef avr to ifdef avr in GetNextReg | nickysn | 2020-04-02 | 1 | -5/+5 |
| * | * moved the AVR-specific comment next to the AVR specific code | nickysn | 2020-04-02 | 1 | -1/+1 |
| * | - disable the check for R_SUBWHOLE in GetNextReg for Z80 | nickysn | 2020-04-02 | 1 | -0/+2 |
| * | Fix handling of parameters with size below the size of a full register | pierre | 2020-03-28 | 1 | -2/+6 |
| * | * cleaning up tcgsize: it makes no sense to declare every combination and type | florian | 2020-01-04 | 1 | -6/+3 |
| * | * symbols called by g_call might need to be imported from dynamic packages as... | svenbarth | 2019-11-21 | 1 | -2/+4 |
| * | * removed accidently committed debug statement | florian | 2019-11-07 | 1 | -2/+1 |
| * | * do not allocate an extra register for some integer operations if not needed | florian | 2019-11-07 | 1 | -1/+2 |
| * | + software handling of exceptions on arm | florian | 2019-07-28 | 1 | -2/+9 |
| * | * fix case completeness and unreachable code warnings in compiler that would | jonas | 2019-05-12 | 1 | -0/+12 |
| * | * let the ARM code generator use the generic tcg.a_load_ref_cgpara() instead | jonas | 2019-02-16 | 1 | -10/+22 |
| * | + initial work for tls-based threadvar support on arm-linux | florian | 2018-11-07 | 1 | -0/+8 |
| * | * Optimized generic implementations of tcg.a_op_const_ref() and tcg.a_op_reg_... | yury | 2018-10-27 | 1 | -4/+22 |
| * | Merged riscv_new branch | florian | 2018-09-26 | 1 | -0/+10 |
| * | * removed temppos field again from parameter locations: they're not allocated | jonas | 2018-04-27 | 1 | -10/+10 |
| * | * keep track of the temp position separately from the offset in references, | jonas | 2018-04-22 | 1 | -10/+10 |
| * | * replaced the saved_XXX_registers arrays with virtual methods inside | nickysn | 2018-04-19 | 1 | -28/+40 |
| * | * moved execution weight calculation into a separate pass, so the info is ava... | florian | 2018-04-08 | 1 | -1/+1 |
| * | + tcg.a_op_loc_reg | florian | 2018-03-11 | 1 | -0/+17 |
| * | Fix msdos failure due to copy/paste error in previous commit | pierre | 2017-11-20 | 1 | -2/+2 |
| * | + shift by 8 and 16 on 8 and 16 bit cpus by simple register moves | florian | 2017-11-19 | 1 | -0/+52 |
| * | + let a_load_loc_reg handle also LOC_*MMREGISTER as we have loadmm_*intreg* | florian | 2017-10-01 | 1 | -0/+2 |
| * | * fix avr for new GetNextReg behaviour | florian | 2017-09-24 | 1 | -2/+8 |
| * | + added check in GetNextReg(), so it halts with an internal error, if called on | nickysn | 2017-09-11 | 1 | -0/+16 |
| * | * also integrated the getnextreg() implementation for 8-bit and 16-bit alus from | nickysn | 2017-09-11 | 1 | -1/+15 |
| * | * integrated the getintregister() implementation for 8-bit and 16-bit alus from | nickysn | 2017-09-11 | 1 | -0/+61 |
| * | * GetNextReg(), used by 16-bit and 8-bit code generators (i8086 and avr) moved | nickysn | 2017-09-11 | 1 | -0/+11 |
| * | * do not call a_load_reg_reg with tosize=OS_NO | florian | 2017-08-24 | 1 | -0/+2 |
| * | * fix tcg.a_load_cgparaloc_ref for ref. sizes of 7 on little endian systems | florian | 2017-08-21 | 1 | -1/+1 |
| * | + implement tcg.a_load_cgparaloc_ref for un-even sizes and little endian syst... | florian | 2017-08-20 | 1 | -8/+33 |
| * | * tcg.a_load_cgparaloc_ref checks the size of the ref exactly to avoid overwr... | florian | 2017-08-20 | 1 | -51/+123 |
| * | + tcg.a_loadfpu_intreg_reg, make use of it in tcg.a_load_cgparaloc_anyreg | florian | 2017-07-09 | 1 | -0/+19 |
| * | * removed unused units | florian | 2017-05-09 | 1 | -1/+1 |
| * | + mask only the low bits that matter for the const of OP_ROL and OP_ROR in | nickysn | 2017-05-01 | 1 | -3/+18 |
| * | + optimize OP_XOR by 0 to OP_NONE in optimize_op_const | nickysn | 2017-04-24 | 1 | -0/+6 |
| * | * fixed tnegnotassign1.pp on powerpc and other RISC cpus | nickysn | 2017-04-09 | 1 | -1/+8 |
| * | + added volatility information to all memory references | jonas | 2016-11-27 | 1 | -11/+11 |
