From 39dd6a5f576a883d73e9fa81f7f033736b10a432 Mon Sep 17 00:00:00 2001 From: laksen Date: Tue, 17 Mar 2015 21:24:07 +0000 Subject: Add workaround for ARM thumb when using GAS. git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@30254 3ad0048d-3df7-0310-abae-a5850022a9f2 --- compiler/arm/aasmcpu.pas | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) (limited to 'compiler/arm') diff --git a/compiler/arm/aasmcpu.pas b/compiler/arm/aasmcpu.pas index 68a86be81a..b3be8a91bb 100644 --- a/compiler/arm/aasmcpu.pas +++ b/compiler/arm/aasmcpu.pas @@ -216,6 +216,7 @@ uses constructor op_reg_reg_reg(op : tasmop;_op1,_op2,_op3 : tregister); constructor op_reg_reg_const(op : tasmop;_op1,_op2 : tregister; _op3: aint); constructor op_reg_const_const(op : tasmop;_op1 : tregister; _op2,_op3: aint); + constructor op_reg_reg_const_const(op : tasmop;_op1,_op2 : tregister; _op3,_op4: aint); constructor op_reg_reg_sym_ofs(op : tasmop;_op1,_op2 : tregister; _op3: tasmsymbol;_op3ofs: longint); constructor op_reg_reg_ref(op : tasmop;_op1,_op2 : tregister; const _op3: treference); constructor op_reg_reg_shifterop(op : tasmop;_op1,_op2 : tregister;_op3 : tshifterop); @@ -309,7 +310,8 @@ uses implementation uses - itcpugas,aoptcpu; + itcpugas,aoptcpu, + systems; procedure taicpu.loadshifterop(opidx:longint;const so:tshifterop); @@ -522,6 +524,17 @@ implementation end; + constructor taicpu.op_reg_reg_const_const(op: tasmop; _op1, _op2: tregister; _op3, _op4: aint); + begin + inherited create(op); + ops:=4; + loadreg(0,_op1); + loadreg(1,_op2); + loadconst(2,aint(_op3)); + loadconst(3,aint(_op4)); + end; + + constructor taicpu.op_reg_const_ref(op : tasmop;_op1 : tregister;_op2 : aint;_op3 : treference); begin inherited create(op); @@ -765,7 +778,8 @@ implementation { check for pre/post indexed } result := operand_read; //Thumb2 - A_LSL, A_LSR, A_ROR, A_ASR, A_SDIV, A_UDIV, A_MOVW, A_MOVT, A_MLS, A_BFI: + A_LSL, A_LSR, A_ROR, A_ASR, A_SDIV, A_UDIV, A_MOVW, A_MOVT, A_MLS, A_BFI, + A_SMMLA,A_SMMLS: if opnr in [0] then result:=operand_write else @@ -1572,6 +1586,7 @@ implementation A_NEG: begin taicpu(curtai).opcode:=A_RSB; + taicpu(curtai).oppostfix:=PF_S; // NEG should always set flags (according to documentation NEG = RSBS) if taicpu(curtai).ops=2 then begin @@ -1599,7 +1614,9 @@ implementation procedure finalizearmcode(list, listtoinsert: TAsmList); begin - expand_instructions(list); + { Don't expand pseudo instructions when using GAS, it breaks on some thumb instructions } + if target_asm.id<>as_gas then + expand_instructions(list); { Do Thumb-2 16bit -> 32bit transformations } if GenerateThumb2Code then -- cgit v1.2.1 From 1e9b6b7cfebd8f9f87c4a69721c4283b8dc484b8 Mon Sep 17 00:00:00 2001 From: laksen Date: Sat, 21 Mar 2015 12:46:45 +0000 Subject: Fix issue in is_thumb32_imm. imm<11:10> have to be non-zero meaning the rotate only works from 8 to 31. Caused 0x8000001F to be mistaken for a valid immediate. git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@30266 3ad0048d-3df7-0310-abae-a5850022a9f2 --- compiler/arm/cpubase.pas | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'compiler/arm') diff --git a/compiler/arm/cpubase.pas b/compiler/arm/cpubase.pas index 66fd7f1a09..101401384a 100644 --- a/compiler/arm/cpubase.pas +++ b/compiler/arm/cpubase.pas @@ -608,7 +608,7 @@ unit cpubase; else begin result:=false; - for i:=1 to 31 do + for i:=8 to 31 do begin t:=RolDWord(d,i); if ((t and $FF)=t) and -- cgit v1.2.1 From 3cd90d9a4c5b58af52d7bba9a4dfc5cef7dd1a9d Mon Sep 17 00:00:00 2001 From: laksen Date: Sun, 22 Mar 2015 14:39:43 +0000 Subject: ARMv7M supports UMULL. Fix missing conflicts for multiplication instructions for >=ARMv6. git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@30276 3ad0048d-3df7-0310-abae-a5850022a9f2 --- compiler/arm/cpuinfo.pas | 4 ++-- compiler/arm/rgcpu.pas | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'compiler/arm') diff --git a/compiler/arm/cpuinfo.pas b/compiler/arm/cpuinfo.pas index a3dd2f6c21..86428c0a56 100644 --- a/compiler/arm/cpuinfo.pas +++ b/compiler/arm/cpuinfo.pas @@ -767,8 +767,8 @@ Const { cpu_armv7 } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_RBIT,CPUARM_HAS_LDREX,CPUARM_HAS_DMB,CPUARM_HAS_THUMB2,CPUARM_HAS_UMULL], { cpu_armv7a } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_RBIT,CPUARM_HAS_LDREX,CPUARM_HAS_DMB,CPUARM_HAS_THUMB2,CPUARM_HAS_UMULL], { cpu_armv7r } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_RBIT,CPUARM_HAS_LDREX,CPUARM_HAS_THUMB_IDIV,CPUARM_HAS_DMB,CPUARM_HAS_THUMB2,CPUARM_HAS_UMULL], - { cpu_armv7m } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_RBIT,CPUARM_HAS_LDREX,CPUARM_HAS_THUMB_IDIV,CPUARM_HAS_DMB,CPUARM_HAS_THUMB2], - { cpu_armv7em } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_RBIT,CPUARM_HAS_LDREX,CPUARM_HAS_THUMB_IDIV,CPUARM_HAS_DMB,CPUARM_HAS_THUMB2] + { cpu_armv7m } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_RBIT,CPUARM_HAS_LDREX,CPUARM_HAS_THUMB_IDIV,CPUARM_HAS_DMB,CPUARM_HAS_THUMB2,CPUARM_HAS_UMULL], + { cpu_armv7em } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_RBIT,CPUARM_HAS_LDREX,CPUARM_HAS_THUMB_IDIV,CPUARM_HAS_DMB,CPUARM_HAS_THUMB2,CPUARM_HAS_UMULL] ); { contains all CPU supporting any kind of thumb instruction set } diff --git a/compiler/arm/rgcpu.pas b/compiler/arm/rgcpu.pas index ca55f59f2c..be21c685f7 100644 --- a/compiler/arm/rgcpu.pas +++ b/compiler/arm/rgcpu.pas @@ -579,9 +579,9 @@ unit rgcpu; A_SMULL, A_SMLAL: begin + add_edge(getsupreg(taicpu(p).oper[0]^.reg),getsupreg(taicpu(p).oper[1]^.reg)); if current_settings.cputype