1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
|
{
Copyright (c) 2000-2002 by Florian Klaempfl
Code generation for add nodes on the SPARC
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
****************************************************************************
}
unit ncpuadd;
{$i fpcdefs.inc}
interface
uses
node,ncgadd,cpubase;
type
tsparcaddnode = class(tcgaddnode)
private
function GetResFlags(unsigned:Boolean):TResFlags;
function GetFPUResFlags:TResFlags;
protected
procedure second_addfloat;override;
procedure second_cmpfloat;override;
procedure second_cmpboolean;override;
procedure second_cmpsmallset;override;
procedure second_cmp64bit;override;
procedure second_cmpordinal;override;
procedure second_addordinal;override;
public
function pass_1: tnode; override;
function use_generic_mul32to64: boolean; override;
end;
implementation
uses
systems,
cutils,verbose,
paramgr,procinfo,
aasmtai,aasmdata,aasmcpu,defutil,
cgbase,cgcpu,cgutils,
cpupara,
ncon,nset,nadd,
hlcgobj, ncgutil,cgobj;
{*****************************************************************************
TSparcAddNode
*****************************************************************************}
function TSparcAddNode.GetResFlags(unsigned:Boolean):TResFlags;
begin
case NodeType of
equaln:
GetResFlags:=F_E;
unequaln:
GetResFlags:=F_NE;
else
if not(unsigned) then
begin
if nf_swapped in flags then
case NodeType of
ltn:
GetResFlags:=F_G;
lten:
GetResFlags:=F_GE;
gtn:
GetResFlags:=F_L;
gten:
GetResFlags:=F_LE;
else
internalerror(2014082010);
end
else
case NodeType of
ltn:
GetResFlags:=F_L;
lten:
GetResFlags:=F_LE;
gtn:
GetResFlags:=F_G;
gten:
GetResFlags:=F_GE;
else
internalerror(2014082011);
end;
end
else
begin
if nf_swapped in Flags then
case NodeType of
ltn:
GetResFlags:=F_A;
lten:
GetResFlags:=F_AE;
gtn:
GetResFlags:=F_B;
gten:
GetResFlags:=F_BE;
else
internalerror(2014082012);
end
else
case NodeType of
ltn:
GetResFlags:=F_B;
lten:
GetResFlags:=F_BE;
gtn:
GetResFlags:=F_A;
gten:
GetResFlags:=F_AE;
else
internalerror(2014082013);
end;
end;
end;
end;
function TSparcAddNode.GetFPUResFlags:TResFlags;
begin
case NodeType of
equaln:
result:=F_FE;
unequaln:
result:=F_FNE;
else
begin
if nf_swapped in Flags then
case NodeType of
ltn:
result:=F_FG;
lten:
result:=F_FGE;
gtn:
result:=F_FL;
gten:
result:=F_FLE;
else
internalerror(2014082014);
end
else
case NodeType of
ltn:
result:=F_FL;
lten:
result:=F_FLE;
gtn:
result:=F_FG;
gten:
result:=F_FGE;
else
internalerror(2014082015);
end;
end;
end;
end;
procedure tsparcaddnode.second_addfloat;
var
op : TAsmOp;
begin
pass_left_right;
if (nf_swapped in flags) then
swapleftright;
{ force fpureg as location, left right doesn't matter
as both will be in a fpureg }
hlcg.location_force_fpureg(current_asmdata.CurrAsmList,left.location,left.resultdef,true);
hlcg.location_force_fpureg(current_asmdata.CurrAsmList,right.location,right.resultdef,(left.location.loc<>LOC_CFPUREGISTER));
location_reset(location,LOC_FPUREGISTER,def_cgsize(resultdef));
if left.location.loc<>LOC_CFPUREGISTER then
location.register:=left.location.register
else
location.register:=right.location.register;
case nodetype of
addn :
begin
if location.size=OS_F64 then
op:=A_FADDd
else
op:=A_FADDs;
end;
muln :
begin
if location.size=OS_F64 then
op:=A_FMULd
else
op:=A_FMULs;
end;
subn :
begin
if location.size=OS_F64 then
op:=A_FSUBd
else
op:=A_FSUBs;
end;
slashn :
begin
if location.size=OS_F64 then
op:=A_FDIVd
else
op:=A_FDIVs;
end;
else
internalerror(200306014);
end;
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(op,
left.location.register,right.location.register,location.register));
end;
procedure tsparcaddnode.second_cmpfloat;
var
op : tasmop;
begin
pass_left_right;
if (nf_swapped in flags) then
swapleftright;
{ force fpureg as location, left right doesn't matter
as both will be in a fpureg }
hlcg.location_force_fpureg(current_asmdata.CurrAsmList,left.location,left.resultdef,true);
hlcg.location_force_fpureg(current_asmdata.CurrAsmList,right.location,right.resultdef,true);
location_reset(location,LOC_FLAGS,OS_NO);
location.resflags:=getfpuresflags;
if left.location.size=OS_F64 then
op:=A_FCMPd
else
op:=A_FCMPs;
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(op,
left.location.register,right.location.register));
{ Delay slot (can only contain integer operation) }
current_asmdata.CurrAsmList.concat(taicpu.op_none(A_NOP));
end;
procedure tsparcaddnode.second_cmpboolean;
begin
pass_left_right;
force_reg_left_right(true,true);
if right.location.loc = LOC_CONSTANT then
tcgsparc(cg).handle_reg_const_reg(current_asmdata.CurrAsmList,A_SUBcc,left.location.register,right.location.value,NR_G0)
else
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_SUBcc,left.location.register,right.location.register,NR_G0));
location_reset(location,LOC_FLAGS,OS_NO);
location.resflags:=getresflags(true);
end;
procedure tsparcaddnode.second_cmpsmallset;
var
tmpreg : tregister;
begin
pass_left_right;
location_reset(location,LOC_FLAGS,OS_NO);
force_reg_left_right(false,false);
case nodetype of
equaln,
unequaln:
begin
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_SUBcc,left.location.register,right.location.register,NR_G0));
location.resflags:=getresflags(true);
end;
lten,
gten:
begin
if (not(nf_swapped in flags) and
(nodetype = lten)) or
((nf_swapped in flags) and
(nodetype = gten)) then
swapleftright;
tmpreg:=cg.getintregister(current_asmdata.CurrAsmList,left.location.size);
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_AND,left.location.register,right.location.register,tmpreg));
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_SUBcc,tmpreg,right.location.register,NR_G0));
location.resflags:=F_E;
end;
else
internalerror(2012042701);
end;
end;
procedure tsparcaddnode.second_cmp64bit;
var
unsigned : boolean;
hreg1,hreg2: tregister;
procedure emit_compare(list:tasmlist; ls,rs:tnode);
var
lreg: tregister64;
begin
if (ls.location.loc=LOC_CONSTANT) then
begin
lreg.reghi:=NR_G0;
lreg.reglo:=NR_G0;
if lo(ls.location.value64)<>0 then
begin
lreg.reglo:=cg.GetIntRegister(list,OS_INT);
cg.a_load_const_reg(list,OS_INT,lo(ls.location.value64),lreg.reglo);
end;
if hi(ls.location.value64)<>0 then
begin
lreg.reghi:=cg.GetIntRegister(list,OS_INT);
cg.a_load_const_reg(list,OS_INT,hi(ls.location.value64),lreg.reghi);
end;
end
else
lreg:=ls.location.register64;
if (rs.location.loc=LOC_CONSTANT) then
begin
tcgsparc(cg).handle_reg_const_reg(list,A_SUBcc,lreg.reglo,lo(rs.location.value64),NR_G0);
tcgsparc(cg).handle_reg_const_reg(list,A_SUBXcc,lreg.reghi,hi(rs.location.value64),NR_G0);
end
else
begin
list.concat(taicpu.op_reg_reg_reg(A_SUBcc,lreg.reglo,rs.location.register64.reglo,NR_G0));
list.concat(taicpu.op_reg_reg_reg(A_SUBXcc,lreg.reghi,rs.location.register64.reghi,NR_G0));
end;
end;
begin
pass_left_right;
force_reg_left_right(true,true);
unsigned:=not(is_signed(left.resultdef)) or
not(is_signed(right.resultdef));
location_reset(location,LOC_FLAGS,OS_NO);
if (nodetype in [equaln,unequaln]) then
begin
location.resflags:=getresflags(unsigned);
if (right.location.loc=LOC_CONSTANT) then
begin
if hi(right.location.value64)<>0 then
begin
hreg1:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
tcgsparc(cg).handle_reg_const_reg(current_asmdata.CurrAsmList,A_XOR,left.location.register64.reghi,hi(right.location.value64),hreg1);
end
else
hreg1:=left.location.register64.reghi;
if lo(right.location.value64)<>0 then
begin
hreg2:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
tcgsparc(cg).handle_reg_const_reg(current_asmdata.CurrAsmList,A_XOR,left.location.register64.reglo,lo(right.location.value64),hreg2);
end
else
hreg2:=left.location.register64.reglo;
end
else
begin
hreg1:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
hreg2:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_XOR,left.location.register64.reghi,right.location.register64.reghi,hreg1));
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_XOR,left.location.register64.reglo,right.location.register64.reglo,hreg2));
end;
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_ORcc,hreg1,hreg2,NR_G0));
end
else
begin
{ undo possible swapped state }
if (nf_swapped in flags) then
swapleftright;
{ Subtracting sides sets N,V and C flags correctly, but not Z flag
(which ends up depending only on upper dword). So don't use conditions
that test Z flag:
unsigned signed
a < b => F_B F_L
a >= b => F_AE F_GE
a <= b => swap, F_AE F_GE
a > b => swap, F_B F_L }
if (nodetype in [ltn,gten]) then
begin
emit_compare(current_asmdata.CurrAsmList,left,right);
location.resflags:=getresflags(unsigned);
end
else if (nodetype in [lten,gtn]) then
begin
emit_compare(current_asmdata.CurrAsmList,right,left);
toggleflag(nf_swapped);
location.resflags:=getresflags(unsigned);
toggleflag(nf_swapped);
end
else
InternalError(2014011001);
end;
end;
procedure tsparcaddnode.second_cmpordinal;
var
unsigned : boolean;
begin
pass_left_right;
force_reg_left_right(true,true);
unsigned:=not(is_signed(left.resultdef)) or
not(is_signed(right.resultdef));
if right.location.loc = LOC_CONSTANT then
tcgsparc(cg).handle_reg_const_reg(current_asmdata.CurrAsmList,A_SUBcc,left.location.register,right.location.value,NR_G0)
else
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_SUBcc,left.location.register,right.location.register,NR_G0));
location_reset(location,LOC_FLAGS,OS_NO);
location.resflags:=getresflags(unsigned);
end;
const
multops: array[boolean] of TAsmOp = (A_SMUL, A_UMUL);
procedure tsparcaddnode.second_addordinal;
var
unsigned: boolean;
begin
unsigned:=not(is_signed(left.resultdef)) or
not(is_signed(right.resultdef));
if (nodetype=muln) and is_64bit(resultdef) then
begin
pass_left_right;
force_reg_left_right(true,false);
location_reset(location,LOC_REGISTER,def_cgsize(resultdef));
location.register64.reglo:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
location.register64.reghi:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_reg(multops[unsigned],left.location.register,right.location.register,location.register64.reglo));
current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg(A_MOV,NR_Y,location.register64.reghi));
end
else
inherited second_addordinal;
end;
function tsparcaddnode.use_generic_mul32to64: boolean;
begin
result:=false;
end;
function tsparcaddnode.pass_1: tnode;
begin
result:=inherited pass_1;
if not assigned(result) then
begin
if is_64bitint(left.resultdef) and
(nodetype in [equaln,unequaln,ltn,gtn,lten,gten]) then
expectloc:=LOC_FLAGS;
end;
end;
begin
caddnode:=tsparcaddnode;
end.
|
