1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
|
{
Copyright (c) 1998-2002 by Florian Klaempfl
Generate generic mathematical nodes
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
****************************************************************************
}
unit ncgmat;
{$i fpcdefs.inc}
interface
uses
node,nmat,cpubase,cgbase;
type
tcgunaryminusnode = class(tunaryminusnode)
protected
{ This routine is called to change the sign of the
floating point value in the floating point
register r.
This routine should be overriden, since
the generic version is not optimal at all. The
generic version assumes that floating
point values are stored in the register
in IEEE-754 format.
}
procedure emit_float_sign_change(r: tregister; _size : tcgsize);virtual;
{$ifdef SUPPORT_MMX}
procedure second_mmx;virtual;abstract;
{$endif SUPPORT_MMX}
{$ifndef cpu64bit}
procedure second_64bit;virtual;
{$endif cpu64bit}
procedure second_integer;virtual;
procedure second_float;virtual;
public
procedure pass_2;override;
end;
tcgmoddivnode = class(tmoddivnode)
procedure pass_2;override;
protected
{ This routine must do an actual 32-bit division, be it
signed or unsigned. The result must set into the the
@var(num) register.
@param(signed Indicates if the division must be signed)
@param(denum Register containing the denominator
@param(num Register containing the numerator, will also receive result)
The actual optimizations regarding shifts have already
been done and emitted, so this should really a do a divide.
}
procedure emit_div_reg_reg(signed: boolean;denum,num : tregister);virtual;abstract;
{ This routine must do an actual 32-bit modulo, be it
signed or unsigned. The result must set into the the
@var(num) register.
@param(signed Indicates if the modulo must be signed)
@param(denum Register containing the denominator
@param(num Register containing the numerator, will also receive result)
The actual optimizations regarding shifts have already
been done and emitted, so this should really a do a modulo.
}
procedure emit_mod_reg_reg(signed: boolean;denum,num : tregister);virtual;abstract;
{$ifndef cpu64bit}
{ This routine must do an actual 64-bit division, be it
signed or unsigned. The result must set into the the
@var(num) register.
@param(signed Indicates if the division must be signed)
@param(denum Register containing the denominator
@param(num Register containing the numerator, will also receive result)
The actual optimizations regarding shifts have already
been done and emitted, so this should really a do a divide.
Currently, this routine should only be implemented on
64-bit systems, otherwise a helper is called in 1st pass.
}
procedure emit64_div_reg_reg(signed: boolean;denum,num : tregister64);virtual;
{$endif cpu64bit}
end;
tcgshlshrnode = class(tshlshrnode)
{$ifndef cpu64bit}
procedure second_64bit;virtual;
{$endif cpu64bit}
procedure second_integer;virtual;
procedure pass_2;override;
end;
tcgnotnode = class(tnotnode)
protected
procedure second_boolean;virtual;abstract;
{$ifdef SUPPORT_MMX}
procedure second_mmx;virtual;abstract;
{$endif SUPPORT_MMX}
{$ifndef cpu64bit}
procedure second_64bit;virtual;
{$endif cpu64bit}
procedure second_integer;virtual;
public
procedure pass_2;override;
end;
implementation
uses
globtype,systems,
cutils,verbose,globals,
symconst,aasmbase,aasmtai,aasmcpu,defutil,
parabase,
pass_2,
ncon,
tgobj,ncgutil,cgobj,cgutils,paramgr
{$ifndef cpu64bit}
,cg64f32
{$endif cpu64bit}
;
{*****************************************************************************
TCGUNARYMINUSNODE
*****************************************************************************}
procedure tcgunaryminusnode.emit_float_sign_change(r: tregister; _size : tcgsize);
var
href,
href2 : treference;
begin
{ get a temporary memory reference to store the floating
point value
}
tg.gettemp(exprasmlist,tcgsize2size[_size],tt_normal,href);
{ store the floating point value in the temporary memory area }
cg.a_loadfpu_reg_ref(exprasmlist,_size,r,href);
{ only single and double ieee are supported, for little endian
the signed bit is in the second dword }
href2:=href;
case _size of
OS_F64 :
if target_info.endian = endian_little then
inc(href2.offset,4);
OS_F32 :
;
else
internalerror(200406021);
end;
{ flip sign-bit (bit 31/63) of single/double }
cg.a_op_const_ref(exprasmlist,OP_XOR,OS_32,aint($80000000),href2);
cg.a_loadfpu_ref_reg(exprasmlist,_size,href,r);
tg.ungetiftemp(exprasmlist,href);
end;
{$ifndef cpu64bit}
procedure tcgunaryminusnode.second_64bit;
begin
secondpass(left);
{ load left operator in a register }
location_copy(location,left.location);
location_force_reg(exprasmlist,location,OS_64,false);
cg64.a_op64_loc_reg(exprasmlist,OP_NEG,OS_64,
location,joinreg64(location.register64.reglo,location.register64.reghi));
end;
{$endif cpu64bit}
procedure tcgunaryminusnode.second_float;
begin
secondpass(left);
location_reset(location,LOC_FPUREGISTER,def_cgsize(resulttype.def));
case left.location.loc of
LOC_REFERENCE,
LOC_CREFERENCE :
begin
location.register:=cg.getfpuregister(exprasmlist,location.size);
cg.a_loadfpu_ref_reg(exprasmlist,
def_cgsize(left.resulttype.def),
left.location.reference,location.register);
emit_float_sign_change(location.register,def_cgsize(left.resulttype.def));
end;
LOC_FPUREGISTER:
begin
location.register:=left.location.register;
emit_float_sign_change(location.register,def_cgsize(left.resulttype.def));
end;
LOC_CFPUREGISTER:
begin
location.register:=cg.getfpuregister(exprasmlist,location.size);
cg.a_loadfpu_reg_reg(exprasmlist,left.location.size,left.location.register,location.register);
emit_float_sign_change(location.register,def_cgsize(left.resulttype.def));
end;
else
internalerror(200306021);
end;
end;
procedure tcgunaryminusnode.second_integer;
begin
secondpass(left);
{ load left operator in a register }
location_copy(location,left.location);
location_force_reg(exprasmlist,location,OS_INT,false);
cg.a_op_reg_reg(exprasmlist,OP_NEG,OS_INT,location.register,location.register);
end;
procedure tcgunaryminusnode.pass_2;
begin
{$ifndef cpu64bit}
if is_64bit(left.resulttype.def) then
second_64bit
else
{$endif cpu64bit}
{$ifdef SUPPORT_MMX}
if (cs_mmx in aktlocalswitches) and is_mmx_able_array(left.resulttype.def) then
second_mmx
else
{$endif SUPPORT_MMX}
if (left.resulttype.def.deftype=floatdef) then
second_float
else
second_integer;
end;
{*****************************************************************************
TCGMODDIVNODE
*****************************************************************************}
{$ifndef cpu64bit}
procedure tcgmoddivnode.emit64_div_reg_reg(signed: boolean; denum,num:tregister64);
begin
{ handled in pass_1 already, unless pass_1 is
overriden
}
{ should be handled in pass_1 (JM) }
internalerror(200109052);
end;
{$endif cpu64bit}
procedure tcgmoddivnode.pass_2;
var
hreg1 : tregister;
hdenom : tregister;
power : longint;
hl : tasmlabel;
paraloc1 : tcgpara;
begin
secondpass(left);
if codegenerror then
exit;
secondpass(right);
if codegenerror then
exit;
location_copy(location,left.location);
{$ifndef cpu64bit}
if is_64bit(resulttype.def) then
begin
{ this code valid for 64-bit cpu's only ,
otherwise helpers are called in pass_1
}
location_force_reg(exprasmlist,location,OS_64,false);
location_copy(location,left.location);
location_force_reg(exprasmlist,right.location,OS_64,false);
emit64_div_reg_reg(is_signed(left.resulttype.def),
joinreg64(right.location.register64.reglo,right.location.register64.reghi),
joinreg64(location.register64.reglo,location.register64.reghi));
end
else
{$endif cpu64bit}
begin
{ put numerator in register }
location_force_reg(exprasmlist,left.location,OS_INT,false);
hreg1:=left.location.register;
if (nodetype=divn) and
(right.nodetype=ordconstn) and
ispowerof2(tordconstnode(right).value,power) then
Begin
{ for signed numbers, the numerator must be adjusted before the
shift instruction, but not wih unsigned numbers! Otherwise,
"Cardinal($ffffffff) div 16" overflows! (JM) }
If is_signed(left.resulttype.def) Then
Begin
objectlibrary.getlabel(hl);
cg.a_cmp_const_reg_label(exprasmlist,OS_INT,OC_GT,0,hreg1,hl);
if power=1 then
cg.a_op_const_reg(exprasmlist,OP_ADD,OS_INT,1,hreg1)
else
cg.a_op_const_reg(exprasmlist,OP_ADD,OS_INT,tordconstnode(right).value-1,hreg1);
cg.a_label(exprasmlist,hl);
cg.a_op_const_reg(exprasmlist,OP_SAR,OS_INT,power,hreg1);
End
Else { not signed }
cg.a_op_const_reg(exprasmlist,OP_SHR,OS_INT,power,hreg1);
End
else
begin
{ bring denominator to hdenom }
{ hdenom is always free, it's }
{ only used for temporary }
{ purposes }
hdenom := cg.getintregister(exprasmlist,OS_INT);
cg.a_load_loc_reg(exprasmlist,right.location.size,right.location,hdenom);
{ verify if the divisor is zero, if so return an error
immediately
}
objectlibrary.getlabel(hl);
cg.a_cmp_const_reg_label(exprasmlist,OS_INT,OC_NE,0,hdenom,hl);
paraloc1.init;
paramanager.getintparaloc(pocall_default,1,paraloc1);
paramanager.allocparaloc(exprasmlist,paraloc1);
cg.a_param_const(exprasmlist,OS_S32,200,paraloc1);
paramanager.freeparaloc(exprasmlist,paraloc1);
cg.a_call_name(exprasmlist,'FPC_HANDLERROR');
paraloc1.done;
cg.a_label(exprasmlist,hl);
if nodetype = modn then
emit_mod_reg_reg(is_signed(left.resulttype.def),hdenom,hreg1)
else
emit_div_reg_reg(is_signed(left.resulttype.def),hdenom,hreg1);
end;
location_reset(location,LOC_REGISTER,OS_INT);
location.register:=hreg1;
end;
cg.g_overflowcheck(exprasmlist,location,resulttype.def);
end;
{*****************************************************************************
TCGSHLRSHRNODE
*****************************************************************************}
{$ifndef cpu64bit}
procedure tcgshlshrnode.second_64bit;
begin
{ already hanled in 1st pass }
internalerror(2002081501);
end;
{$endif cpu64bit}
procedure tcgshlshrnode.second_integer;
var
op : topcg;
hcountreg : tregister;
begin
{ determine operator }
case nodetype of
shln: op:=OP_SHL;
shrn: op:=OP_SHR;
end;
{ load left operators in a register }
location_copy(location,left.location);
location_force_reg(exprasmlist,location,OS_INT,false);
{ shifting by a constant directly coded: }
if (right.nodetype=ordconstn) then
begin
{ l shl 32 should 0 imho, but neither TP nor Delphi do it in this way (FK)
if right.value<=31 then
}
cg.a_op_const_reg(exprasmlist,op,location.size,
tordconstnode(right).value and 31,location.register);
{
else
emit_reg_reg(A_XOR,S_L,hregister1,
hregister1);
}
end
else
begin
{ load right operators in a register - this
is done since most target cpu which will use this
node do not support a shift count in a mem. location (cec)
}
if right.location.loc<>LOC_REGISTER then
begin
hcountreg:=cg.getintregister(exprasmlist,OS_INT);
cg.a_load_loc_reg(exprasmlist,right.location.size,right.location,hcountreg);
end
else
hcountreg:=right.location.register;
cg.a_op_reg_reg(exprasmlist,op,OS_INT,hcountreg,location.register);
end;
end;
procedure tcgshlshrnode.pass_2;
begin
secondpass(left);
secondpass(right);
{$ifndef cpu64bit}
if is_64bit(left.resulttype.def) then
second_64bit
else
{$endif cpu64bit}
second_integer;
end;
{*****************************************************************************
TCGNOTNODE
*****************************************************************************}
{$ifndef cpu64bit}
procedure tcgnotnode.second_64bit;
begin
secondpass(left);
location_force_reg(exprasmlist,left.location,def_cgsize(left.resulttype.def),false);
location_copy(location,left.location);
{ perform the NOT operation }
cg64.a_op64_reg_reg(exprasmlist,OP_NOT,location.size,left.location.register64,location.register64);
end;
{$endif cpu64bit}
procedure tcgnotnode.second_integer;
begin
secondpass(left);
location_force_reg(exprasmlist,left.location,def_cgsize(left.resulttype.def),false);
location_copy(location,left.location);
{ perform the NOT operation }
cg.a_op_reg_reg(exprasmlist,OP_NOT,location.size,location.register,location.register);
end;
procedure tcgnotnode.pass_2;
begin
if is_boolean(resulttype.def) then
second_boolean
{$ifdef SUPPORT_MMX}
else if (cs_mmx in aktlocalswitches) and is_mmx_able_array(left.resulttype.def) then
second_mmx
{$endif SUPPORT_MMX}
{$ifndef cpu64bit}
else if is_64bit(left.resulttype.def) then
second_64bit
{$endif cpu64bit}
else
second_integer;
end;
begin
cmoddivnode:=tcgmoddivnode;
cunaryminusnode:=tcgunaryminusnode;
cshlshrnode:=tcgshlshrnode;
cnotnode:=tcgnotnode;
end.
|