1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
|
{
Copyright (c) 1998-2002 by Florian Klaempfl
Generate PowerPC assembler for math nodes
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
****************************************************************************
}
unit nppcmat;
{$i fpcdefs.inc}
interface
uses
node,nmat;
type
tppcmoddivnode = class(tmoddivnode)
function pass_1: tnode;override;
procedure pass_2;override;
end;
tppcshlshrnode = class(tshlshrnode)
procedure pass_2;override;
{ everything will be handled in pass_2 }
function first_shlshr64bitint: tnode; override;
end;
tppcunaryminusnode = class(tunaryminusnode)
procedure pass_2;override;
end;
tppcnotnode = class(tnotnode)
procedure pass_2;override;
end;
implementation
uses
globtype,systems,
cutils,verbose,globals,
symconst,symdef,
aasmbase,aasmcpu,aasmtai,
defutil,
cgbase,cgutils,cgobj,pass_1,pass_2,
ncon,procinfo,
cpubase,cpuinfo,
ncgutil,cgcpu,cg64f32,rgobj;
{*****************************************************************************
TPPCMODDIVNODE
*****************************************************************************}
function tppcmoddivnode.pass_1: tnode;
begin
result := inherited pass_1;
if not assigned(result) then
include(current_procinfo.flags,pi_do_call);
end;
procedure tppcmoddivnode.pass_2;
const
{ signed overflow }
divops: array[boolean, boolean] of tasmop =
((A_DIVWU,A_DIVWUO_),(A_DIVW,A_DIVWO_));
zerocond: tasmcond = (dirhint: DH_Plus; simple: true; cond:C_NE; cr: RS_CR1);
var
power : longint;
op : tasmop;
numerator,
divider,
resultreg : tregister;
size : Tcgsize;
hl : tasmlabel;
begin
secondpass(left);
secondpass(right);
location_copy(location,left.location);
{ put numerator in register }
size:=def_cgsize(left.resulttype.def);
location_force_reg(exprasmlist,left.location,
size,true);
location_copy(location,left.location);
numerator := location.register;
resultreg := location.register;
if (location.loc = LOC_CREGISTER) then
begin
location.loc := LOC_REGISTER;
location.register := cg.getintregister(exprasmlist,size);
resultreg := location.register;
end;
if (nodetype = modn) then
begin
resultreg := cg.getintregister(exprasmlist,size);
end;
if (nodetype = divn) and
(right.nodetype = ordconstn) and
ispowerof2(tordconstnode(right).value,power) then
begin
{ From "The PowerPC Compiler Writer's Guide": }
{ This code uses the fact that, in the PowerPC architecture, }
{ the shift right algebraic instructions set the Carry bit if }
{ the source register contains a negative number and one or }
{ more 1-bits are shifted out. Otherwise, the carry bit is }
{ cleared. The addze instruction corrects the quotient, if }
{ necessary, when the dividend is negative. For example, if }
{ n = -13, (0xFFFF_FFF3), and k = 2, after executing the srawi }
{ instruction, q = -4 (0xFFFF_FFFC) and CA = 1. After executing }
{ the addze instruction, q = -3, the correct quotient. }
cg.a_op_const_reg_reg(exprasmlist,OP_SAR,OS_32,power,
numerator,resultreg);
exprasmlist.concat(taicpu.op_reg_reg(A_ADDZE,resultreg,resultreg));
end
else
begin
{ load divider in a register if necessary }
location_force_reg(exprasmlist,right.location,
def_cgsize(right.resulttype.def),true);
if (right.nodetype <> ordconstn) then
exprasmlist.concat(taicpu.op_reg_reg_const(A_CMPWI,NR_CR1,
right.location.register,0));
divider := right.location.register;
{ needs overflow checking, (-maxlongint-1) div (-1) overflows! }
{ And on PPC, the only way to catch a div-by-0 is by checking }
{ the overflow flag (JM) }
op := divops[is_signed(right.resulttype.def),
cs_check_overflow in aktlocalswitches];
exprasmlist.concat(taicpu.op_reg_reg_reg(op,resultreg,numerator,
divider));
if (nodetype = modn) then
begin
exprasmlist.concat(taicpu.op_reg_reg_reg(A_MULLW,resultreg,
divider,resultreg));
exprasmlist.concat(taicpu.op_reg_reg_reg(A_SUB,location.register,
numerator,resultreg));
resultreg := location.register;
end;
end;
{ set result location }
location.loc:=LOC_REGISTER;
location.register:=resultreg;
if right.nodetype <> ordconstn then
begin
objectlibrary.getlabel(hl);
exprasmlist.concat(taicpu.op_cond_sym(A_BC,zerocond,hl));
cg.a_call_name(exprasmlist,'FPC_DIVBYZERO');
cg.a_label(exprasmlist,hl);
end;
cg.g_overflowcheck(exprasmlist,location,resulttype.def);
end;
{*****************************************************************************
TPPCSHLRSHRNODE
*****************************************************************************}
function tppcshlshrnode.first_shlshr64bitint: tnode;
begin
result := nil;
end;
procedure tppcshlshrnode.pass_2;
var
resultreg, hregister1,hregister2,
hreg64hi,hreg64lo : tregister;
op : topcg;
asmop1, asmop2: tasmop;
shiftval: aint;
begin
secondpass(left);
secondpass(right);
if is_64bitint(left.resulttype.def) then
begin
location_force_reg(exprasmlist,left.location,
def_cgsize(left.resulttype.def),true);
location_copy(location,left.location);
hreg64hi := location.register64.reghi;
hreg64lo := location.register64.reglo;
if (location.loc = LOC_CREGISTER) then
begin
location.loc := LOC_REGISTER;
location.register64.reghi := cg.getintregister(exprasmlist,OS_32);
location.register64.reglo := cg.getintregister(exprasmlist,OS_32);
end;
if (right.nodetype = ordconstn) then
begin
shiftval := tordconstnode(right).value;
shiftval := shiftval and 63;
{
I think the statements below is much more correct instead of the hack above,
but then we fail tshlshr.pp :/
if shiftval > 63 then
begin
cg.a_load_const_reg(exprasmlist,OS_32,0,location.register64.reglo);
cg.a_load_const_reg(exprasmlist,OS_32,0,location.register64.reglo);
end
else } if shiftval > 31 then
begin
if nodetype = shln then
begin
cg.a_op_const_reg_reg(exprasmlist,OP_SHL,OS_32,
shiftval and 31,hreg64lo,location.register64.reghi);
cg.a_load_const_reg(exprasmlist,OS_32,0,location.register64.reglo);
end
else
begin
cg.a_op_const_reg_reg(exprasmlist,OP_SHR,OS_32,
shiftval and 31,hreg64hi,location.register64.reglo);
cg.a_load_const_reg(exprasmlist,OS_32,0,location.register64.reghi);
end;
end
else
begin
if nodetype = shln then
begin
exprasmlist.concat(taicpu.op_reg_reg_const_const_const(
A_RLWINM,location.register64.reghi,hreg64hi,shiftval,
0,31-shiftval));
exprasmlist.concat(taicpu.op_reg_reg_const_const_const(
A_RLWIMI,location.register64.reghi,hreg64lo,shiftval,
32-shiftval,31));
exprasmlist.concat(taicpu.op_reg_reg_const_const_const(
A_RLWINM,location.register64.reglo,hreg64lo,shiftval,
0,31-shiftval));
end
else
begin
exprasmlist.concat(taicpu.op_reg_reg_const_const_const(
A_RLWINM,location.register64.reglo,hreg64lo,32-shiftval,
shiftval,31));
exprasmlist.concat(taicpu.op_reg_reg_const_const_const(
A_RLWIMI,location.register64.reglo,hreg64hi,32-shiftval,
0,shiftval-1));
exprasmlist.concat(taicpu.op_reg_reg_const_const_const(
A_RLWINM,location.register64.reghi,hreg64hi,32-shiftval,
shiftval,31));
end;
end;
end
else
{ no constant shiftcount }
begin
location_force_reg(exprasmlist,right.location,OS_S32,true);
hregister1 := right.location.register;
if nodetype = shln then
begin
asmop1 := A_SLW;
asmop2 := A_SRW;
end
else
begin
asmop1 := A_SRW;
asmop2 := A_SLW;
resultreg := hreg64hi;
hreg64hi := hreg64lo;
hreg64lo := resultreg;
resultreg := location.register64.reghi;
location.register64.reghi := location.register64.reglo;
location.register64.reglo := resultreg;
end;
cg.getcpuregister(exprasmlist,NR_R0);
exprasmlist.concat(taicpu.op_reg_reg_const(A_SUBFIC,
NR_R0,hregister1,32));
exprasmlist.concat(taicpu.op_reg_reg_reg(asmop1,
location.register64.reghi,hreg64hi,hregister1));
exprasmlist.concat(taicpu.op_reg_reg_reg(asmop2,
NR_R0,hreg64lo,NR_R0));
exprasmlist.concat(taicpu.op_reg_reg_reg(A_OR,
location.register64.reghi,location.register64.reghi,NR_R0));
exprasmlist.concat(taicpu.op_reg_reg_const(A_SUBI,
NR_R0,hregister1,32));
exprasmlist.concat(taicpu.op_reg_reg_reg(asmop1,
NR_R0,hreg64lo,NR_R0));
exprasmlist.concat(taicpu.op_reg_reg_reg(A_OR,
location.register64.reghi,location.register64.reghi,NR_R0));
exprasmlist.concat(taicpu.op_reg_reg_reg(asmop1,
location.register64.reglo,hreg64lo,hregister1));
cg.ungetcpuregister(exprasmlist,NR_R0);
if nodetype = shrn then
begin
resultreg := location.register64.reghi;
location.register64.reghi := location.register64.reglo;
location.register64.reglo := resultreg;
end;
end
end
else
begin
{ load left operators in a register }
location_force_reg(exprasmlist,left.location,def_cgsize(left.resulttype.def),true);
location_copy(location,left.location);
resultreg := location.register;
hregister1 := location.register;
if (location.loc = LOC_CREGISTER) then
begin
location.loc := LOC_REGISTER;
resultreg := cg.getintregister(exprasmlist,OS_32);
location.register := resultreg;
end;
{ determine operator }
if nodetype=shln then
op:=OP_SHL
else
op:=OP_SHR;
{ shifting by a constant directly coded: }
if (right.nodetype=ordconstn) then
cg.a_op_const_reg_reg(exprasmlist,op,OS_32,
tordconstnode(right).value and 31,hregister1,resultreg)
else
begin
{ load shift count in a register if necessary }
location_force_reg(exprasmlist,right.location,def_cgsize(right.resulttype.def),true);
hregister2 := right.location.register;
cg.a_op_reg_reg_reg(exprasmlist,op,OS_32,hregister2,
hregister1,resultreg);
end;
end;
end;
{*****************************************************************************
TPPCUNARYMINUSNODE
*****************************************************************************}
procedure tppcunaryminusnode.pass_2;
var
src1: tregister;
op: tasmop;
begin
secondpass(left);
if is_64bitint(left.resulttype.def) then
begin
location_force_reg(exprasmlist,left.location,def_cgsize(left.resulttype.def),true);
location_copy(location,left.location);
if (location.loc = LOC_CREGISTER) then
begin
location.register64.reglo := cg.getintregister(exprasmlist,OS_INT);
location.register64.reghi := cg.getintregister(exprasmlist,OS_INT);
location.loc := LOC_REGISTER;
end;
exprasmlist.concat(taicpu.op_reg_reg_const(A_SUBFIC,
location.register64.reglo,left.location.register64.reglo,0));
if not(cs_check_overflow in aktlocalswitches) then
exprasmlist.concat(taicpu.op_reg_reg(A_SUBFZE,
location.register64.reghi,left.location.register64.reghi))
else
exprasmlist.concat(taicpu.op_reg_reg(A_SUBFZEO_,
location.register64.reghi,left.location.register64.reghi));
end
else
begin
location_copy(location,left.location);
location.loc:=LOC_REGISTER;
case left.location.loc of
LOC_FPUREGISTER, LOC_REGISTER:
begin
src1 := left.location.register;
location.register := src1;
end;
LOC_CFPUREGISTER, LOC_CREGISTER:
begin
src1 := left.location.register;
if left.location.loc = LOC_CREGISTER then
location.register := cg.getintregister(exprasmlist,OS_INT)
else
location.register := cg.getfpuregister(exprasmlist,location.size);
end;
LOC_REFERENCE,LOC_CREFERENCE:
begin
if (left.resulttype.def.deftype=floatdef) then
begin
src1 := cg.getfpuregister(exprasmlist,def_cgsize(left.resulttype.def));
location.register := src1;
cg.a_loadfpu_ref_reg(exprasmlist,
def_cgsize(left.resulttype.def),
left.location.reference,src1);
end
else
begin
src1 := cg.getintregister(exprasmlist,OS_32);
location.register:= src1;
cg.a_load_ref_reg(exprasmlist,OS_32,OS_32,
left.location.reference,src1);
end;
end;
end;
{ choose appropriate operand }
if left.resulttype.def.deftype <> floatdef then
begin
if not(cs_check_overflow in aktlocalswitches) then
op := A_NEG
else
op := A_NEGO_;
location.loc := LOC_REGISTER;
end
else
begin
op := A_FNEG;
location.loc := LOC_FPUREGISTER;
end;
{ emit operation }
exprasmlist.concat(taicpu.op_reg_reg(op,location.register,src1));
end;
{ Here was a problem... }
{ Operand to be negated always }
{ seems to be converted to signed }
{ 32-bit before doing neg!! }
{ So this is useless... }
{ that's not true: -2^31 gives an overflow error if it is negated (FK) }
cg.g_overflowcheck(exprasmlist,location,resulttype.def);
end;
{*****************************************************************************
TPPCNOTNODE
*****************************************************************************}
procedure tppcnotnode.pass_2;
var
hl : tasmlabel;
begin
if is_boolean(resulttype.def) then
begin
{ if the location is LOC_JUMP, we do the secondpass after the
labels are allocated
}
if left.expectloc=LOC_JUMP then
begin
hl:=truelabel;
truelabel:=falselabel;
falselabel:=hl;
secondpass(left);
maketojumpbool(exprasmlist,left,lr_load_regvars);
hl:=truelabel;
truelabel:=falselabel;
falselabel:=hl;
location.loc:=LOC_JUMP;
end
else
begin
secondpass(left);
case left.location.loc of
LOC_FLAGS :
begin
location_copy(location,left.location);
inverse_flags(location.resflags);
end;
LOC_REGISTER, LOC_CREGISTER, LOC_REFERENCE, LOC_CREFERENCE :
begin
location_force_reg(exprasmlist,left.location,def_cgsize(left.resulttype.def),true);
exprasmlist.concat(taicpu.op_reg_const(A_CMPWI,left.location.register,0));
location_reset(location,LOC_FLAGS,OS_NO);
location.resflags.cr:=RS_CR0;
location.resflags.flag:=F_EQ;
end;
else
internalerror(2003042401);
end;
end;
end
else if is_64bitint(left.resulttype.def) then
begin
secondpass(left);
location_force_reg(exprasmlist,left.location,def_cgsize(left.resulttype.def),false);
location_copy(location,left.location);
{ perform the NOT operation }
exprasmlist.concat(taicpu.op_reg_reg(A_NOT,location.register64.reghi,
location.register64.reghi));
exprasmlist.concat(taicpu.op_reg_reg(A_NOT,location.register64.reglo,
location.register64.reglo));
end
else
begin
secondpass(left);
location_force_reg(exprasmlist,left.location,def_cgsize(left.resulttype.def),true);
location_copy(location,left.location);
location.loc := LOC_REGISTER;
location.register := cg.getintregister(exprasmlist,OS_INT);
{ perform the NOT operation }
cg.a_op_reg_reg(exprasmlist,OP_NOT,def_cgsize(resulttype.def),left.location.register,
location.register);
end;
end;
begin
cmoddivnode:=tppcmoddivnode;
cshlshrnode:=tppcshlshrnode;
cunaryminusnode:=tppcunaryminusnode;
cnotnode:=tppcnotnode;
end.
|