diff options
Diffstat (limited to 'FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_common.h')
| -rw-r--r-- | FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_common.h | 504 |
1 files changed, 74 insertions, 430 deletions
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_common.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_common.h index b7be9c3f1..09a668e05 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_common.h +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_common.h @@ -1,6 +1,6 @@ /*
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2019 NXP
+ * Copyright 2016-2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -15,19 +15,10 @@ #include <string.h>
#include <stdlib.h>
-#if defined(__ICCARM__)
+#if defined(__ICCARM__) || (defined(__CC_ARM) || defined(__ARMCC_VERSION)) || defined(__GNUC__)
#include <stddef.h>
#endif
-/*
- * For CMSIS pack RTE.
- * CMSIS pack RTE generates "RTC_Components.h" which contains the statements
- * of the related <RTE_Components_h> element for all selected software components.
- */
-#ifdef _RTE_
-#include "RTE_Components.h"
-#endif
-
#include "fsl_device_registers.h"
/*!
@@ -36,6 +27,15 @@ */
/*******************************************************************************
+ * Configurations
+ ******************************************************************************/
+
+/*! @brief Macro to use the default weak IRQ handler in drivers. */
+#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
+#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1
+#endif
+
+/*******************************************************************************
* Definitions
******************************************************************************/
@@ -47,8 +47,8 @@ /*! @name Driver version */
/*@{*/
-/*! @brief common driver version 2.2.2. */
-#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 2, 2))
+/*! @brief common driver version. */
+#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 3, 0))
/*@}*/
/* Debug console type definition. */
@@ -62,6 +62,7 @@ #define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */
#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_QSCI 10U /*!< Debug console based on QSCI. */
/*! @brief Status group numbers. */
enum _status_groups
@@ -139,6 +140,10 @@ enum _status_groups kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */
kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */
kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */
+ kStatusGroup_SFA = 103, /*!< Group number for SFA status codes*/
+ kStatusGroup_SPC = 104, /*!< Group number for SPC status codes. */
+ kStatusGroup_PUF = 105, /*!< Group number for PUF status codes. */
+ kStatusGroup_TOUCH_PANEL = 106, /*!< Group number for touch panel status codes */
kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */
kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */
@@ -162,34 +167,39 @@ enum _status_groups kStatusGroup_SDK_OCOTP = 146, /*!< Group number for OCOTP status codes. */
kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/
kStatusGroup_CODEC = 148, /*!< Group number for codec status codes. */
- kStatusGroup_ASRC = 149, /*!< Group number for codec status ASRC. */
+ kStatusGroup_ASRC = 149, /*!< Group number for codec status ASRC. */
kStatusGroup_OTFAD = 150, /*!< Group number for codec status codes. */
+ kStatusGroup_SDIOSLV = 151, /*!< Group number for SDIOSLV status codes. */
+ kStatusGroup_MECC = 152, /*!< Group number for MECC status codes. */
+ kStatusGroup_ENET_QOS = 153, /*!< Group number for ENET_QOS status codes. */
+ kStatusGroup_LOG = 154, /*!< Group number for LOG status codes. */
+ kStatusGroup_I3CBUS = 155, /*!< Group number for I3CBUS status codes. */
+ kStatusGroup_QSCI = 156, /*!< Group number for QSCI status codes. */
+ kStatusGroup_SNT = 157, /*!< Group number for SNT status codes. */
};
-/*! @brief Generic status return codes. */
+/*! \public
+ * @brief Generic status return codes.
+ */
enum
{
- kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0),
- kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1),
- kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2),
- kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3),
- kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4),
- kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5),
- kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6),
+ kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< Generic status for Success. */
+ kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< Generic status for Fail. */
+ kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< Generic status for read only failure. */
+ kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< Generic status for out of range access. */
+ kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< Generic status for invalid argument check. */
+ kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Generic status for timeout. */
+ kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Generic status for no transfer in progress. */
+ kStatus_Busy = MAKE_STATUS(kStatusGroup_Generic, 7), /*!< Generic status for module is busy. */
};
/*! @brief Type used for all status and error return values. */
typedef int32_t status_t;
-/*
- * Macro guard for whether to use default weak IRQ implementation in drivers
+/*!
+ * @name Min/max macros
+ * @{
*/
-#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
-#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1
-#endif
-
-/*! @name Min/max macros */
-/* @{ */
#if !defined(MIN)
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
#endif
@@ -215,192 +225,6 @@ typedef int32_t status_t; #endif
/* @} */
-/*! @name Timer utilities */
-/* @{ */
-/*! Macro to convert a microsecond period to raw count value */
-#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U)
-/*! Macro to convert a raw count value to microsecond */
-#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz)
-
-/*! Macro to convert a millisecond period to raw count value */
-#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U)
-/*! Macro to convert a raw count value to millisecond */
-#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)
-/* @} */
-
-/*! @name Alignment variable definition macros */
-/* @{ */
-#if (defined(__ICCARM__))
-/**
- * Workaround to disable MISRA C message suppress warnings for IAR compiler.
- * http:/ /supp.iar.com/Support/?note=24725
- */
-_Pragma("diag_suppress=Pm120")
-#define SDK_PRAGMA(x) _Pragma(#x)
- _Pragma("diag_error=Pm120")
-/*! Macro to define a variable with alignbytes alignment */
-#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
-/*! Macro to define a variable with L1 d-cache line size alignment */
-#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
-#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var
-#endif
-/*! Macro to define a variable with L2 cache line size alignment */
-#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
-#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
-#endif
-#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
-/*! Macro to define a variable with alignbytes alignment */
-#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
-/*! Macro to define a variable with L1 d-cache line size alignment */
-#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
-#define SDK_L1DCACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) var
-#endif
-/*! Macro to define a variable with L2 cache line size alignment */
-#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
-#define SDK_L2CACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) var
-#endif
-#elif defined(__GNUC__)
-/*! Macro to define a variable with alignbytes alignment */
-#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
-/*! Macro to define a variable with L1 d-cache line size alignment */
-#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
-#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)))
-#endif
-/*! Macro to define a variable with L2 cache line size alignment */
-#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
-#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)))
-#endif
-#else
-#error Toolchain not supported
-#define SDK_ALIGN(var, alignbytes) var
-#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
-#define SDK_L1DCACHE_ALIGN(var) var
-#endif
-#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
-#define SDK_L2CACHE_ALIGN(var) var
-#endif
-#endif
-
-/*! Macro to change a value to a given size aligned value */
-#define SDK_SIZEALIGN(var, alignbytes) \
- ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U)))
-/* @} */
-
-/*! @name Non-cacheable region definition macros */
-/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or
- * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables,
- * please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables
- * will be initialized to zero in system startup.
- */
-/* @{ */
-#if (defined(__ICCARM__))
-#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
-#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable"
-#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable"
-#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init"
-#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init"
-#else
-#define AT_NONCACHEABLE_SECTION(var) var
-#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
-#define AT_NONCACHEABLE_SECTION_INIT(var) var
-#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
-#endif
-#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
-#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
-#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
-#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
- __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var
-#if(defined(__CC_ARM))
-#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var
-#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
- __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var
-#else
-#define AT_NONCACHEABLE_SECTION(var) __attribute__((section(".bss.NonCacheable"))) var
-#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
- __attribute__((section(".bss.NonCacheable"))) __attribute__((aligned(alignbytes))) var
-#endif
-#else
-#define AT_NONCACHEABLE_SECTION(var) var
-#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
-#define AT_NONCACHEABLE_SECTION_INIT(var) var
-#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __attribute__((aligned(alignbytes))) var
-#endif
-#elif(defined(__XCC__))
-#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
-#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
- __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))
-#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"))) var
-#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
- __attribute__((section("NonCacheable"))) var __attribute__((aligned(alignbytes)))
-#elif(defined(__GNUC__))
-/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
- * in your projects to make sure the non-cacheable section variables will be initialized in system startup.
- */
-#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
-#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
-#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
- __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))
-#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var
-#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
- __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes)))
-#else
-#define AT_NONCACHEABLE_SECTION(var) var
-#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
-#define AT_NONCACHEABLE_SECTION_INIT(var) var
-#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var __attribute__((aligned(alignbytes)))
-#endif
-#else
-#error Toolchain not supported.
-#define AT_NONCACHEABLE_SECTION(var) var
-#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var
-#define AT_NONCACHEABLE_SECTION_INIT(var) var
-#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var
-#endif
-/* @} */
-
-/*! @name Time sensitive region */
-/* @{ */
-#if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE
-#if (defined(__ICCARM__))
-#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess"
-#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess"
-#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
-#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func
-#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
-#elif(defined(__GNUC__))
-#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func
-#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
-#else
-#error Toolchain not supported.
-#endif /* defined(__ICCARM__) */
-#else
-#if (defined(__ICCARM__))
-#define AT_QUICKACCESS_SECTION_CODE(func) func
-#define AT_QUICKACCESS_SECTION_DATA(func) func
-#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
-#define AT_QUICKACCESS_SECTION_CODE(func) func
-#define AT_QUICKACCESS_SECTION_DATA(func) func
-#elif(defined(__GNUC__))
-#define AT_QUICKACCESS_SECTION_CODE(func) func
-#define AT_QUICKACCESS_SECTION_DATA(func) func
-#else
-#error Toolchain not supported.
-#endif
-#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */
-/* @} */
-
-/*! @name Ram Function */
-#if (defined(__ICCARM__))
-#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction"
-#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
-#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
-#elif(defined(__GNUC__))
-#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
-#else
-#error Toolchain not supported.
-#endif /* defined(__ICCARM__) */
-/* @} */
-
/*! @name Suppress fallthrough warning macro */
/* For switch case code block, if case section ends without "break;" statement, there wil be
fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc.
@@ -415,229 +239,41 @@ _Pragma("diag_suppress=Pm120") #endif
/* @} */
-#if defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
-void DefaultISR(void);
-#endif
-/*
- * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
- * defined in previous of this file.
- */
-#include "fsl_clock.h"
-
-/*
- * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
- */
-#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
- (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
-#include "fsl_reset.h"
-#endif
-
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
- extern "C"
-{
-#endif
-
- /*!
- * @brief Enable specific interrupt.
- *
- * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt
- * levels. For example, there are NVIC and intmux. Here the interrupts connected
- * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
- * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
- * to NVIC first then routed to core.
- *
- * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts
- * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
- *
- * @param interrupt The IRQ number.
- * @retval kStatus_Success Interrupt enabled successfully
- * @retval kStatus_Fail Failed to enable the interrupt
- */
- static inline status_t EnableIRQ(IRQn_Type interrupt)
- {
- if (NotAvail_IRQn == interrupt)
- {
- return kStatus_Fail;
- }
-
-#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
- if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
- {
- return kStatus_Fail;
- }
-#endif
-
-#if defined(__GIC_PRIO_BITS)
- GIC_EnableIRQ(interrupt);
-#else
- NVIC_EnableIRQ(interrupt);
-#endif
- return kStatus_Success;
- }
-
- /*!
- * @brief Disable specific interrupt.
- *
- * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt
- * levels. For example, there are NVIC and intmux. Here the interrupts connected
- * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
- * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
- * to NVIC first then routed to core.
- *
- * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts
- * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
- *
- * @param interrupt The IRQ number.
- * @retval kStatus_Success Interrupt disabled successfully
- * @retval kStatus_Fail Failed to disable the interrupt
- */
- static inline status_t DisableIRQ(IRQn_Type interrupt)
- {
- if (NotAvail_IRQn == interrupt)
- {
- return kStatus_Fail;
- }
-
-#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
- if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
- {
- return kStatus_Fail;
- }
-#endif
-
-#if defined(__GIC_PRIO_BITS)
- GIC_DisableIRQ(interrupt);
-#else
- NVIC_DisableIRQ(interrupt);
-#endif
- return kStatus_Success;
- }
-
- /*!
- * @brief Disable the global IRQ
- *
- * Disable the global interrupt and return the current primask register. User is required to provided the primask
- * register for the EnableGlobalIRQ().
- *
- * @return Current primask value.
- */
- static inline uint32_t DisableGlobalIRQ(void)
- {
-#if defined (__XCC__)
- return 0;
-#else
-#if defined(CPSR_I_Msk)
- uint32_t cpsr = __get_CPSR() & CPSR_I_Msk;
-
- __disable_irq();
-
- return cpsr;
-#else
- uint32_t regPrimask = __get_PRIMASK();
-
- __disable_irq();
-
- return regPrimask;
-#endif
-#endif
- }
-
- /*!
- * @brief Enable the global IRQ
- *
- * Set the primask register with the provided primask value but not just enable the primask. The idea is for the
- * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
- * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
- *
- * @param primask value of primask register to be restored. The primask value is supposed to be provided by the
- * DisableGlobalIRQ().
- */
- static inline void EnableGlobalIRQ(uint32_t primask)
- {
-#if defined (__XCC__)
-#else
-#if defined(CPSR_I_Msk)
- __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);
-#else
- __set_PRIMASK(primask);
+extern "C" {
#endif
-#endif
- }
-
-#if defined(ENABLE_RAM_VECTOR_TABLE)
- /*!
- * @brief install IRQ handler
- *
- * @param irq IRQ number
- * @param irqHandler IRQ handler address
- * @return The old IRQ handler address
- */
- uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
-#endif /* ENABLE_RAM_VECTOR_TABLE. */
-
-#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
- /*!
- * @brief Enable specific interrupt for wake-up from deep-sleep mode.
- *
- * Enable the interrupt for wake-up from deep sleep mode.
- * Some interrupts are typically used in sleep mode only and will not occur during
- * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
- * those clocks (significantly increasing power consumption in the reduced power mode),
- * making these wake-ups possible.
- *
- * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly).
- *
- * @param interrupt The IRQ number.
- */
- void EnableDeepSleepIRQ(IRQn_Type interrupt);
-
- /*!
- * @brief Disable specific interrupt for wake-up from deep-sleep mode.
- *
- * Disable the interrupt for wake-up from deep sleep mode.
- * Some interrupts are typically used in sleep mode only and will not occur during
- * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
- * those clocks (significantly increasing power consumption in the reduced power mode),
- * making these wake-ups possible.
- *
- * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly).
- *
- * @param interrupt The IRQ number.
- */
- void DisableDeepSleepIRQ(IRQn_Type interrupt);
-#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
- /*!
- * @brief Allocate memory with given alignment and aligned size.
- *
- * This is provided to support the dynamically allocated memory
- * used in cache-able region.
- * @param size The length required to malloc.
- * @param alignbytes The alignment size.
- * @retval The allocated memory.
- */
- void *SDK_Malloc(size_t size, size_t alignbytes);
+/*!
+ * @brief Allocate memory with given alignment and aligned size.
+ *
+ * This is provided to support the dynamically allocated memory
+ * used in cache-able region.
+ * @param size The length required to malloc.
+ * @param alignbytes The alignment size.
+ * @retval The allocated memory.
+ */
+void *SDK_Malloc(size_t size, size_t alignbytes);
- /*!
- * @brief Free memory.
- *
- * @param ptr The memory to be release.
- */
- void SDK_Free(void *ptr);
+/*!
+ * @brief Free memory.
+ *
+ * @param ptr The memory to be release.
+ */
+void SDK_Free(void *ptr);
- /*!
- * @brief Delay at least for some time.
- * Please note that, this API uses while loop for delay, different run-time environments make the time not precise,
- * if precise delay count was needed, please implement a new delay function with hardware timer.
- *
- * @param delay_us Delay time in unit of microsecond.
- * @param coreClock_Hz Core clock frequency with Hz.
- */
- void SDK_DelayAtLeastUs(uint32_t delay_us, uint32_t coreClock_Hz);
+/*!
+* @brief Delay at least for some time.
+* Please note that, this API uses while loop for delay, different run-time environments make the time not precise,
+* if precise delay count was needed, please implement a new delay function with hardware timer.
+*
+* @param delayTime_us Delay time in unit of microsecond.
+* @param coreClock_Hz Core clock frequency with Hz.
+*/
+void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz);
#if defined(__cplusplus)
}
@@ -645,4 +281,12 @@ void DefaultISR(void); /*! @} */
+#if (defined(__DSC__) && defined(__CW__))
+#include "fsl_common_dsc.h"
+#elif defined(__XCC__)
+#include "fsl_common_dsp.h"
+#else
+#include "fsl_common_arm.h"
+#endif
+
#endif /* _FSL_COMMON_H_ */
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