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path: root/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_common_arm.c
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Diffstat (limited to 'FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_common_arm.c')
-rw-r--r--FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_common_arm.c32
1 files changed, 24 insertions, 8 deletions
diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_common_arm.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_common_arm.c
index e77a265ce..241005e92 100644
--- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_common_arm.c
+++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_common_arm.c
@@ -116,9 +116,9 @@ void DisableDeepSleepIRQ(IRQn_Type interrupt)
#endif /* FSL_FEATURE_POWERLIB_EXTEND */
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
-#if defined(SDK_DELAY_USE_DWT) && defined(DWT)
+#if defined(DWT)
/* Use WDT. */
-static void enableCpuCycleCounter(void)
+void MSDK_EnableCpuCycleCounter(void)
{
/* Make sure the DWT trace fucntion is enabled. */
if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR))
@@ -136,11 +136,13 @@ static void enableCpuCycleCounter(void)
}
}
-static uint32_t getCpuCycleCount(void)
+uint32_t MSDK_GetCpuCycleCount(void)
{
return DWT->CYCCNT;
}
-#else /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */
+#endif /* defined(DWT) */
+
+#if !(defined(SDK_DELAY_USE_DWT) && defined(DWT))
/* Use software loop. */
#if defined(__CC_ARM) /* This macro is arm v5 specific */
/* clang-format off */
@@ -152,6 +154,20 @@ loop
BNE loop
BX LR
}
+#elif defined(__ARM_ARCH_8A__) /* This macro is ARMv8-A specific */
+static void DelayLoop(uint32_t count)
+{
+ __ASM volatile(" MOV X0, %0" : : "r"(count));
+ __ASM volatile(
+ "loop: \n"
+ " SUB X0, X0, #1 \n"
+ " CMP X0, #0 \n"
+
+ " BNE loop \n"
+ :
+ :
+ : "r0");
+}
/* clang-format on */
#elif defined(__ARMCC_VERSION) || defined(__ICCARM__) || defined(__GNUC__)
/* Cortex-M0 has a smaller instruction set, SUBS isn't supported in thumb-16 mode reported from __GNUC__ compiler,
@@ -198,21 +214,21 @@ void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz)
#if defined(SDK_DELAY_USE_DWT) && defined(DWT) /* Use DWT for better accuracy */
- enableCpuCycleCounter();
+ MSDK_EnableCpuCycleCounter();
/* Calculate the count ticks. */
- count += getCpuCycleCount();
+ count += MSDK_GetCpuCycleCount();
if (count > UINT32_MAX)
{
count -= UINT32_MAX;
/* Wait for cyccnt overflow. */
- while (count < getCpuCycleCount())
+ while (count < MSDK_GetCpuCycleCount())
{
}
}
/* Wait for cyccnt reach count value. */
- while (count > getCpuCycleCount())
+ while (count > MSDK_GetCpuCycleCount())
{
}
#else