diff options
Diffstat (limited to 'FreeRTOS/Demo/RISC-V-spike-htif_GCC/spike-1.cfg')
| -rw-r--r-- | FreeRTOS/Demo/RISC-V-spike-htif_GCC/spike-1.cfg | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/FreeRTOS/Demo/RISC-V-spike-htif_GCC/spike-1.cfg b/FreeRTOS/Demo/RISC-V-spike-htif_GCC/spike-1.cfg new file mode 100644 index 000000000..572a94ea2 --- /dev/null +++ b/FreeRTOS/Demo/RISC-V-spike-htif_GCC/spike-1.cfg @@ -0,0 +1,33 @@ +adapter_khz 10000 + +interface remote_bitbang +remote_bitbang_host localhost +remote_bitbang_port 9824 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos auto +#target create $_TARGETNAME riscv -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 8096 -work-area-backup 1 + + +gdb_report_data_abort enable +gdb_report_register_access_error enable + +# Expose an unimplemented CSR so we can test non-existent register access +# behavior. +riscv expose_csrs 2288 +riscv expose_custom 1,12345-12348 + +init + +set challenge [riscv authdata_read] +riscv authdata_write [expr $challenge + 1] + +halt + +reg mstatus 0 + +arm semihosting enable |