diff options
Diffstat (limited to 'FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design/fpga_design_description/ICICLE_MSS_eMMC_cfg.xml')
| -rw-r--r-- | FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design/fpga_design_description/ICICLE_MSS_eMMC_cfg.xml | 4024 |
1 files changed, 4024 insertions, 0 deletions
diff --git a/FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design/fpga_design_description/ICICLE_MSS_eMMC_cfg.xml b/FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design/fpga_design_description/ICICLE_MSS_eMMC_cfg.xml new file mode 100644 index 000000000..310f29169 --- /dev/null +++ b/FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/boards/icicle-kit-es/fpga_design/fpga_design_description/ICICLE_MSS_eMMC_cfg.xml @@ -0,0 +1,4024 @@ + <mss xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="mpfs_hw_description.xsd"> + <design_information> + <libero_version>2021.1</libero_version> + <design_name>ICICLE_MSS</design_name> + <mpfs_part_no>MPFS250T_ES</mpfs_part_no> + <mpfs_package>FCVG484</mpfs_package> + <creation_date_time>04-11-2021_22:30:25</creation_date_time> + <xml_format_version>0.5.3</xml_format_version> + </design_information> + <mss_memory_map> + <map> + <mem_elements> + <mem description="Reset vector hart0" name="RESET_VECTOR_HART0" size="0x4">0x20220000</mem> + <mem description="Reset vector hart1" name="RESET_VECTOR_HART1" size="0x4">0x20220000</mem> + <mem description="Reset vector hart2" name="RESET_VECTOR_HART2" size="0x4">0x20220000</mem> + <mem description="Reset vector hart3" name="RESET_VECTOR_HART3" size="0x4">0x20220000</mem> + <mem description="Reset vector hart4" name="RESET_VECTOR_HART4" size="0x4">0x20220000</mem> + <mem description="example instance of memory" name="DDR_32_CACHE" size="0x100000">0x80000000</mem> + <mem description="example instance" name="DDR_32_NON_CACHE" size="0x100000">0xC0000000</mem> + <mem description="64 bit address " name="DDR_64_CACHE" size="0x100000">0x1000000000</mem> + <mem description="64 bit address " name="DDR_64_NON_CACHE" size="0x100000">0x1400000000</mem> + <mem description="example instance" name="DDR_32_WCB" size="0x100000">0xD0000000</mem> + <mem description="64 bit address " name="DDR_64_WCB" size="0x100000">0x1800000000</mem> + <mem description="Offset and size of reserved sNVM. (Not available to MSS)" name="RESERVED_SNVM" size="0x00000000">0x00000000</mem> + <mem description="Offset and size of reserved eNVM (Not available to MSS)" name="RESERVED_ENVM" size="0x00000000">0x00000000</mem> + </mem_elements> + </map> + <apb_split> + <registers> + <register address="0x00000000" description="This version incrments when change to format of this file" name="APB_SPLIT_VERSION"> + <field Type="RW" name="VERSION" offset="0" width="32">0x1</field> + </register> + <register address="0x00000004" description="Enabled in configurator when bit set to 1" name="MEM_CONFIGS_ENABLED"> + <field Type="RW" name="PMP" offset="0" width="0">0x0</field> + <field Type="RW" name="MPU" offset="1" width="0">0x0</field> + </register> + <register address="0x00000008" description="AMP Mode peripheral mapping register. When the register bit is '0' the peripheral is mapped into the 0x2000000 address range using AXI bus 5 from the Coreplex. When the register bit is '1' the peripheral is mapped into the 0x28000000 address range using AXI bus 6 from the Coreplex." name="APBBUS_CR"> + <field Type="RW" name="MMUART0" offset="0" width="1">0x0</field> + <field Type="RW" name="MMUART1" offset="1" width="1">0x0</field> + <field Type="RW" name="MMUART2" offset="2" width="1">0x0</field> + <field Type="RW" name="MMUART3" offset="3" width="1">0x0</field> + <field Type="RW" name="MMUART4" offset="4" width="1">0x0</field> + <field Type="RW" name="WDOG0" offset="5" width="1">0x0</field> + <field Type="RW" name="WDOG1" offset="6" width="1">0x0</field> + <field Type="RW" name="WDOG2" offset="7" width="1">0x0</field> + <field Type="RW" name="WDOG3" offset="8" width="1">0x0</field> + <field Type="RW" name="WDOG4" offset="9" width="1">0x0</field> + <field Type="RW" name="SPI0" offset="10" width="1">0x0</field> + <field Type="RW" name="SPI1" offset="11" width="1">0x0</field> + <field Type="RW" name="I2C0" offset="12" width="1">0x0</field> + <field Type="RW" name="I2C1" offset="13" width="1">0x0</field> + <field Type="RW" name="CAN0" offset="14" width="1">0x0</field> + <field Type="RW" name="CAN1" offset="15" width="1">0x0</field> + <field Type="RW" name="GEM0" offset="16" width="1">0x0</field> + <field Type="RW" name="GEM1" offset="17" width="1">0x0</field> + <field Type="RW" name="TIMER" offset="18" width="1">0x0</field> + <field Type="RW" name="GPIO0" offset="19" width="1">0x0</field> + <field Type="RW" name="GPIO1" offset="20" width="1">0x0</field> + <field Type="RW" name="GPIO2" offset="21" width="1">0x0</field> + <field Type="RW" name="RTC" offset="22" width="1">0x0</field> + <field Type="RW" name="H2FINT" offset="23" width="1">0x0</field> + </register> + <register address="0x00000012" description="AMP context A. When the register bit is '0' the peripheral is not allowed access from context A. " name="CONTEXT_A_EN"> + <field Type="RW" name="MMUART0" offset="0" width="1">0x0</field> + <field Type="RW" name="MMUART1" offset="1" width="1">0x0</field> + <field Type="RW" name="MMUART2" offset="2" width="1">0x0</field> + <field Type="RW" name="MMUART3" offset="3" width="1">0x0</field> + <field Type="RW" name="MMUART4" offset="4" width="1">0x0</field> + <field Type="RW" name="WDOG0" offset="5" width="1">0x0</field> + <field Type="RW" name="WDOG1" offset="6" width="1">0x0</field> + <field Type="RW" name="WDOG2" offset="7" width="1">0x0</field> + <field Type="RW" name="WDOG3" offset="8" width="1">0x0</field> + <field Type="RW" name="WDOG4" offset="9" width="1">0x0</field> + <field Type="RW" name="SPI0" offset="10" width="1">0x0</field> + <field Type="RW" name="SPI1" offset="11" width="1">0x0</field> + <field Type="RW" name="I2C0" offset="12" width="1">0x0</field> + <field Type="RW" name="I2C1" offset="13" width="1">0x0</field> + <field Type="RW" name="CAN0" offset="14" width="1">0x0</field> + <field Type="RW" name="CAN1" offset="15" width="1">0x0</field> + <field Type="RW" name="GEM0" offset="16" width="1">0x0</field> + <field Type="RW" name="GEM1" offset="17" width="1">0x0</field> + <field Type="RW" name="TIMER" offset="18" width="1">0x0</field> + <field Type="RW" name="GPIO0" offset="19" width="1">0x0</field> + <field Type="RW" name="GPIO1" offset="20" width="1">0x0</field> + <field Type="RW" name="GPIO2" offset="21" width="1">0x0</field> + <field Type="RW" name="RTC" offset="22" width="1">0x0</field> + <field Type="RW" name="H2FINT" offset="23" width="1">0x0</field> + <field Type="RW" name="CRYPTO" offset="24" width="1">0x0</field> + <field Type="RW" name="USB" offset="25" width="1">0x0</field> + <field Type="RW" name="QSPIXIP" offset="26" width="1">0x0</field> + <field Type="RW" name="ATHENA" offset="27" width="1">0x0</field> + <field Type="RW" name="TRACE" offset="28" width="1">0x0</field> + <field Type="RW" name="MAILBOX_SC" offset="29" width="1">0x0</field> + <field Type="RW" name="EMMC" offset="30" width="1">0x0</field> + </register> + <register address="0x00000016" description="AMP context B. When the register bit is '0' the peripheral is not allowed access from context B. " name="CONTEXT_B_EN"> + <field Type="RW" name="MMUART0" offset="0" width="1">0x0</field> + <field Type="RW" name="MMUART1" offset="1" width="1">0x0</field> + <field Type="RW" name="MMUART2" offset="2" width="1">0x0</field> + <field Type="RW" name="MMUART3" offset="3" width="1">0x0</field> + <field Type="RW" name="MMUART4" offset="4" width="1">0x0</field> + <field Type="RW" name="WDOG0" offset="5" width="1">0x0</field> + <field Type="RW" name="WDOG1" offset="6" width="1">0x0</field> + <field Type="RW" name="WDOG2" offset="7" width="1">0x0</field> + <field Type="RW" name="WDOG3" offset="8" width="1">0x0</field> + <field Type="RW" name="WDOG4" offset="9" width="1">0x0</field> + <field Type="RW" name="SPI0" offset="10" width="1">0x0</field> + <field Type="RW" name="SPI1" offset="11" width="1">0x0</field> + <field Type="RW" name="I2C0" offset="12" width="1">0x0</field> + <field Type="RW" name="I2C1" offset="13" width="1">0x0</field> + <field Type="RW" name="CAN0" offset="14" width="1">0x0</field> + <field Type="RW" name="CAN1" offset="15" width="1">0x0</field> + <field Type="RW" name="GEM0" offset="16" width="1">0x0</field> + <field Type="RW" name="GEM1" offset="17" width="1">0x0</field> + <field Type="RW" name="TIMER" offset="18" width="1">0x0</field> + <field Type="RW" name="GPIO0" offset="19" width="1">0x0</field> + <field Type="RW" name="GPIO1" offset="20" width="1">0x0</field> + <field Type="RW" name="GPIO2" offset="21" width="1">0x0</field> + <field Type="RW" name="RTC" offset="22" width="1">0x0</field> + <field Type="RW" name="H2FINT" offset="23" width="1">0x0</field> + <field Type="RW" name="CRYPTO" offset="24" width="1">0x0</field> + <field Type="RW" name="USB" offset="25" width="1">0x0</field> + <field Type="RW" name="QSPIXIP" offset="26" width="1">0x0</field> + <field Type="RW" name="ATHENA" offset="27" width="1">0x0</field> + <field Type="RW" name="TRACE" offset="28" width="1">0x0</field> + <field Type="RW" name="MAILBOX_SC" offset="29" width="1">0x0</field> + <field Type="RW" name="EMMC" offset="30" width="1">0x0</field> + </register> + <register address="0x00000020" description="When the register bit is '0' hart is not associated with context A." name="CONTEXT_A_HART_EN"> + <field Type="RW" name="HART0" offset="0" width="1">0x0</field> + <field Type="RW" name="HART1" offset="1" width="1">0x0</field> + <field Type="RW" name="HART2" offset="2" width="1">0x0</field> + <field Type="RW" name="HART3" offset="3" width="1">0x0</field> + <field Type="RW" name="HART4" offset="4" width="1">0x0</field> + </register> + <register address="0x00000024" description="When the register bit is '0' hart is not associated with context B." name="CONTEXT_B_HART_EN"> + <field Type="RW" name="HART0" offset="0" width="1">0x0</field> + <field Type="RW" name="HART1" offset="1" width="1">0x0</field> + <field Type="RW" name="HART2" offset="2" width="1">0x0</field> + <field Type="RW" name="HART3" offset="3" width="1">0x0</field> + <field Type="RW" name="HART4" offset="4" width="1">0x0</field> + </register> + </registers> + </apb_split> + <cache> + <registers> + <register address="0x00000008" description="Way indexes less than or equal to this register value may be used by the cache. E.g. set to 0x7, will allocate 8 cache ways, 0-7 to cache, and leave 8-15 as LIM. Note 1: Way 0 is always allocated as cache. Note 2: each way is 128KB." name="WAY_ENABLE"> + <field Type="RW" name="WAY_ENABLE" offset="0" width="8">0xB</field> + </register> + <register address="0x00000008" description="Way mask register master DMA. Set field to zero to disable way from this master. The available cache ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory, the ways you want reserved for scrathpad are not available for selection, you must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not evict the way. " name="WAY_MASK_DMA"> + <field Type="RW" name="WAY_MASK_0" offset="0" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_1" offset="1" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_2" offset="2" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_3" offset="3" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_4" offset="4" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_5" offset="5" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_6" offset="6" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_7" offset="7" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_8" offset="8" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_9" offset="9" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_10" offset="10" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_11" offset="11" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_12" offset="12" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_13" offset="13" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_14" offset="14" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_15" offset="15" width="1">0x1</field> + </register> + <register address="0x00000016" description="Way mask register master DMA. Set field to zero to disable way from this master. The available cache ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory, the ways you want reserved for scrathpad are not available for selection, you must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not evict the way. " name="WAY_MASK_AXI4_PORT_0"> + <field Type="RW" name="WAY_MASK_0" offset="0" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_1" offset="1" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_2" offset="2" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_3" offset="3" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_4" offset="4" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_5" offset="5" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_6" offset="6" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_7" offset="7" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_8" offset="8" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_9" offset="9" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_10" offset="10" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_11" offset="11" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_12" offset="12" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_13" offset="13" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_14" offset="14" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_15" offset="15" width="1">0x1</field> + </register> + <register address="0x00000024" description="Way mask register master DMA. Set field to zero to disable way from this master. The available cache ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory, the ways you want reserved for scrathpad are not available for selection, you must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not evict the way. " name="WAY_MASK_AXI4_PORT_1"> + <field Type="RW" name="WAY_MASK_0" offset="0" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_1" offset="1" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_2" offset="2" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_3" offset="3" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_4" offset="4" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_5" offset="5" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_6" offset="6" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_7" offset="7" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_8" offset="8" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_9" offset="9" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_10" offset="10" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_11" offset="11" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_12" offset="12" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_13" offset="13" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_14" offset="14" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_15" offset="15" width="1">0x1</field> + </register> + <register address="0x00000032" description="Way mask registerAXI slave port 2. Set field to zero to disable way from this master. The available cache ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory, the ways you want reserved for scrathpad are not available for selection, you must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not evict the way. " name="WAY_MASK_AXI4_PORT_2"> + <field Type="RW" name="WAY_MASK_0" offset="0" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_1" offset="1" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_2" offset="2" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_3" offset="3" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_4" offset="4" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_5" offset="5" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_6" offset="6" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_7" offset="7" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_8" offset="8" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_9" offset="9" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_10" offset="10" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_11" offset="11" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_12" offset="12" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_13" offset="13" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_14" offset="14" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_15" offset="15" width="1">0x1</field> + </register> + <register address="0x00000040" description="Way mask register AXI slave port 3. Set field to 1 to disable way from this master. Set field to zero to disable way from this master. The available cache ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory, the ways you want reserved for scrathpad are not available for selection, you must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not evict the way. " name="WAY_MASK_AXI4_PORT_3"> + <field Type="RW" name="WAY_MASK_0" offset="0" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_1" offset="1" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_2" offset="2" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_3" offset="3" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_4" offset="4" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_5" offset="5" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_6" offset="6" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_7" offset="7" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_8" offset="8" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_9" offset="9" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_10" offset="10" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_11" offset="11" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_12" offset="12" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_13" offset="13" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_14" offset="14" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_15" offset="15" width="1">0x1</field> + </register> + <register address="0x00000048" description="Way mask register E51 data cache (hart0). Set field to zero to disable way from this master. The available cache ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory, the ways you want reserved for scrathpad are not available for selection, you must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not evict the way. " name="WAY_MASK_E51_DCACHE"> + <field Type="RW" name="WAY_MASK_0" offset="0" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_1" offset="1" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_2" offset="2" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_3" offset="3" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_4" offset="4" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_5" offset="5" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_6" offset="6" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_7" offset="7" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_8" offset="8" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_9" offset="9" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_10" offset="10" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_11" offset="11" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_12" offset="12" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_13" offset="13" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_14" offset="14" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_15" offset="15" width="1">0x1</field> + </register> + <register address="0x00000056" description="Way mask registerE52 instruction cache (hart0). Set field to zero to disable way from this master. The available cache ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory, the ways you want reserved for scrathpad are not available for selection, you must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not evict the way. " name="WAY_MASK_E51_ICACHE"> + <field Type="RW" name="WAY_MASK_0" offset="0" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_1" offset="1" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_2" offset="2" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_3" offset="3" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_4" offset="4" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_5" offset="5" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_6" offset="6" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_7" offset="7" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_8" offset="8" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_9" offset="9" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_10" offset="10" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_11" offset="11" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_12" offset="12" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_13" offset="13" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_14" offset="14" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_15" offset="15" width="1">0x1</field> + </register> + <register address="0x00000064" description="Way mask register data cache (hart1). Set field to zero to disable way from this master. The available cache ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory, the ways you want reserved for scrathpad are not available for selection, you must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not evict the way. " name="WAY_MASK_U54_1_DCACHE"> + <field Type="RW" name="WAY_MASK_0" offset="0" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_1" offset="1" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_2" offset="2" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_3" offset="3" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_4" offset="4" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_5" offset="5" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_6" offset="6" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_7" offset="7" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_8" offset="8" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_9" offset="9" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_10" offset="10" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_11" offset="11" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_12" offset="12" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_13" offset="13" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_14" offset="14" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_15" offset="15" width="1">0x1</field> + </register> + <register address="0x00000072" description="Way mask register instruction cache (hart1). Set field to zero to disable way from this master. The available cache ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory, the ways you want reserved for scrathpad are not available for selection, you must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not evict the way. " name="WAY_MASK_U54_1_ICACHE"> + <field Type="RW" name="WAY_MASK_0" offset="0" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_1" offset="1" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_2" offset="2" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_3" offset="3" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_4" offset="4" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_5" offset="5" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_6" offset="6" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_7" offset="7" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_8" offset="8" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_9" offset="9" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_10" offset="10" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_11" offset="11" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_12" offset="12" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_13" offset="13" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_14" offset="14" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_15" offset="15" width="1">0x1</field> + </register> + <register address="0x00000080" description="Way mask register data cache (hart2). Set field to 1 to disable way from this master. Set field to zero to disable way from this master. The available cache ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory, the ways you want reserved for scrathpad are not available for selection, you must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not evict the way. " name="WAY_MASK_U54_2_DCACHE"> + <field Type="RW" name="WAY_MASK_0" offset="0" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_1" offset="1" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_2" offset="2" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_3" offset="3" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_4" offset="4" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_5" offset="5" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_6" offset="6" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_7" offset="7" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_8" offset="8" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_9" offset="9" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_10" offset="10" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_11" offset="11" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_12" offset="12" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_13" offset="13" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_14" offset="14" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_15" offset="15" width="1">0x1</field> + </register> + <register address="0x00000088" description="Way mask register instruction cache (hart2). Set field to zero to disable way from this master. The available cache ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory, the ways you want reserved for scrathpad are not available for selection, you must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not evict the way. " name="WAY_MASK_U54_2_ICACHE"> + <field Type="RW" name="WAY_MASK_0" offset="0" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_1" offset="1" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_2" offset="2" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_3" offset="3" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_4" offset="4" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_5" offset="5" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_6" offset="6" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_7" offset="7" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_8" offset="8" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_9" offset="9" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_10" offset="10" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_11" offset="11" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_12" offset="12" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_13" offset="13" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_14" offset="14" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_15" offset="15" width="1">0x1</field> + </register> + <register address="0x00000096" description="Way mask register data cache (hart3). Set field to 1 to disable way from this master.Set field to zero to disable way from this master. The available cache ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory, the ways you want reserved for scrathpad are not available for selection, you must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not evict the way. " name="WAY_MASK_U54_3_DCACHE"> + <field Type="RW" name="WAY_MASK_0" offset="0" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_1" offset="1" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_2" offset="2" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_3" offset="3" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_4" offset="4" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_5" offset="5" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_6" offset="6" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_7" offset="7" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_8" offset="8" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_9" offset="9" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_10" offset="10" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_11" offset="11" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_12" offset="12" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_13" offset="13" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_14" offset="14" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_15" offset="15" width="1">0x1</field> + </register> + <register address="0x00000104" description="Way mask register instruction cache(hart3). Set field to zero to disable way from this master. The available cache ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory, the ways you want reserved for scrathpad are not available for selection, you must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not evict the way. " name="WAY_MASK_U54_3_ICACHE"> + <field Type="RW" name="WAY_MASK_0" offset="0" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_1" offset="1" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_2" offset="2" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_3" offset="3" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_4" offset="4" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_5" offset="5" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_6" offset="6" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_7" offset="7" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_8" offset="8" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_9" offset="9" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_10" offset="10" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_11" offset="11" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_12" offset="12" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_13" offset="13" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_14" offset="14" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_15" offset="15" width="1">0x1</field> + </register> + <register address="0x00000112" description="Way mask register data cache (hart4). Set field to 1 to disable way from this master. Set field to zero to disable way from this master. The available cache ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory, the ways you want reserved for scrathpad are not available for selection, you must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not evict the way. " name="WAY_MASK_U54_4_DCACHE"> + <field Type="RW" name="WAY_MASK_0" offset="0" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_1" offset="1" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_2" offset="2" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_3" offset="3" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_4" offset="4" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_5" offset="5" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_6" offset="6" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_7" offset="7" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_8" offset="8" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_9" offset="9" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_10" offset="10" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_11" offset="11" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_12" offset="12" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_13" offset="13" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_14" offset="14" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_15" offset="15" width="1">0x1</field> + </register> + <register address="0x00000120" description="Way mask register instruction cache (hart4). Set field to zero to disable way from this master. The available cache ways are 0 to number set in WAY_ENABLE register. If using scratch pad memory, the ways you want reserved for scrathpad are not available for selection, you must set to 0. e.g. If three ways reserved for scratchpad, WAY_MASK_0, WAY_MASK_1 and WAY_MASK_2 will be set to zero for all masters, so they can not evict the way. " name="WAY_MASK_U54_4_ICACHE"> + <field Type="RW" name="WAY_MASK_0" offset="0" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_1" offset="1" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_2" offset="2" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_3" offset="3" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_4" offset="4" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_5" offset="5" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_6" offset="6" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_7" offset="7" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_8" offset="8" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_9" offset="9" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_10" offset="10" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_11" offset="11" width="1">0x0</field> + <field Type="RW" name="WAY_MASK_12" offset="12" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_13" offset="13" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_14" offset="14" width="1">0x1</field> + <field Type="RW" name="WAY_MASK_15" offset="15" width="1">0x1</field> + </register> + <register address="0x00000136" description="Number of ways reserved for scratchpad. Note 1: This is not a register Note 2: each way is 128KB. Note 3: Embedded software expects cache ways allocated for scratchpad start at way 0, and work up." name="NUM_SCRATCH_PAD_WAYS"> + <field Type="RW" name="NUM_OF_WAYS" offset="0" width="8">0x4</field> + </register> + </registers> + </cache> + <pmp_h0> + <registers> + <register address="0x000003A0" description="PMP configuration for 8 adress regions, bit 0 read, bit 1 write, bit 2 execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) " name="CSR_PMPCFG0"> + <field Type="RW" name="PMP0CFG" offset="0" width="8">0x00</field> + <field Type="RW" name="PMP1CFG" offset="8" width="8">0x0</field> + <field Type="RW" name="PMP2CFG" offset="16" width="8">0x00</field> + <field Type="RW" name="PMP3CFG" offset="24" width="8">0x00</field> + <field Type="RW" name="PMP4CFG" offset="32" width="8">0x00</field> + <field Type="RW" name="PMP5CFG" offset="40" width="8">0x00</field> + <field Type="RW" name="PMP6CFG" offset="48" width="8">0x00</field> + <field Type="RW" name="PMP7CFG" offset="56" width="8">0x00</field> + </register> + <register address="0x000003A2" description="PMP configuration for 8 address regions, bit 0 read, bit 1 write, bit 2 execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) " name="CSR_PMPCFG2"> + <field Type="RW" name="PMP8CFG" offset="0" width="8">0x00</field> + <field Type="RW" name="PMP9CFG" offset="8" width="8">0x00</field> + <field Type="RW" name="PMP10CFG" offset="16" width="8">0x00</field> + <field Type="RW" name="PMP11CFG" offset="24" width="8">0x00</field> + <field Type="RW" name="PMP12CFG" offset="32" width="8">0x00</field> + <field Type="RW" name="PMP13CFG" offset="40" width="8">0x00</field> + <field Type="RW" name="PMP14CFG" offset="48" width="8">0x00</field> + <field Type="RW" name="PMP15CFG" offset="56" width="8">0x00</field> + </register> + <register address="0x000003B0" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR0"> + <field Type="RW" name="CSR_PMPADDR0" offset="0" width="64">0x00</field> + </register> + <register address="0x000003B1" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR1"> + <field Type="RW" name="CSR_PMPADDR1" offset="0" width="64">0x00</field> + </register> + <register address="0x000003B2" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR2"> + <field Type="RW" name="CSR_PMPADDR2" offset="0" width="64">0x00</field> + </register> + <register address="0x000003B3" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR3"> + <field Type="RW" name="CSR_PMPADDR3" offset="0" width="64">0x00</field> + </register> + <register address="0x000003B4" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR4"> + <field Type="RW" name="CSR_PMPADDR4" offset="0" width="64">0x00</field> + </register> + <register address="0x000003B5" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR5"> + <field Type="RW" name="CSR_PMPADDR5" offset="0" width="64">0x00</field> + </register> + <register address="0x000003B6" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR6"> + <field Type="RW" name="CSR_PMPADDR6" offset="0" width="64">0x00</field> + </register> + <register address="0x000003B7" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR7"> + <field Type="RW" name="CSR_PMPADDR7" offset="0" width="64">0x00</field> + </register> + <register address="0x000003B8" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR8"> + <field Type="RW" name="CSR_PMPADDR8" offset="0" width="64">0x00</field> + </register> + <register address="0x000003B9" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR9"> + <field Type="RW" name="CSR_PMPADDR9" offset="0" width="64">0x00</field> + </register> + <register address="0x00003B10" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR10"> + <field Type="RW" name="CSR_PMPADDR10" offset="0" width="64">0x00</field> + </register> + <register address="0x00003B11" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR11"> + <field Type="RW" name="CSR_PMPADDR11" offset="0" width="64">0x00</field> + </register> + <register address="0x00003B12" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR12"> + <field Type="RW" name="CSR_PMPADDR12" offset="0" width="64">0x00</field> + </register> + <register address="0x00003B13" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR13"> + <field Type="RW" name="CSR_PMPADDR13" offset="0" width="64">0x00</field> + </register> + <register address="0x00003B14" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR14"> + <field Type="RW" name="CSR_PMPADDR14" offset="0" width="64">0x00</field> + </register> + <register address="0x00003B15" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR15"> + <field Type="RW" name="CSR_PMPADDR15" offset="0" width="64">0x00</field> + </register> + </registers> + </pmp_h0> + <pmp_h1> + <registers> + <register address="0x000003A0" description="PMP configuration for 8 adress regions, bit 0 read, bit 1 write, bit 2 execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) " name="CSR_PMPCFG0"> + <field Type="RW" name="PMP0CFG" offset="0" width="8">0x9F</field> + <field Type="RW" name="PMP1CFG" offset="8" width="8">0x0</field> + <field Type="RW" name="PMP2CFG" offset="16" width="8">0x0</field> + <field Type="RW" name="PMP3CFG" offset="24" width="8">0x0</field> + <field Type="RW" name="PMP4CFG" offset="32" width="8">0x0</field> + <field Type="RW" name="PMP5CFG" offset="40" width="8">0x0</field> + <field Type="RW" name="PMP6CFG" offset="48" width="8">0x0</field> + <field Type="RW" name="PMP7CFG" offset="56" width="8">0x0</field> + </register> + <register address="0x000003A2" description="PMP configuration for 8 address regions, bit 0 read, bit 1 write, bit 2 execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) " name="CSR_PMPCFG2"> + <field Type="RW" name="PMP8CFG" offset="0" width="8">0x0</field> + <field Type="RW" name="PMP9CFG" offset="8" width="8">0x0</field> + <field Type="RW" name="PMP10CFG" offset="16" width="8">0x0</field> + <field Type="RW" name="PMP11CFG" offset="24" width="8">0x0</field> + <field Type="RW" name="PMP12CFG" offset="32" width="8">0x0</field> + <field Type="RW" name="PMP13CFG" offset="40" width="8">0x0</field> + <field Type="RW" name="PMP14CFG" offset="48" width="8">0x0</field> + <field Type="RW" name="PMP15CFG" offset="56" width="8">0x0</field> + </register> + <register address="0x000003B0" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR0"> + <field Type="RW" name="CSR_PMPADDR0" offset="0" width="64">0xFFFFFFFFFFFFFFFF</field> + </register> + <register address="0x000003B1" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR1"> + <field Type="RW" name="CSR_PMPADDR1" offset="0" width="64">0x0</field> + </register> + <register address="0x000003B2" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR2"> + <field Type="RW" name="CSR_PMPADDR2" offset="0" width="64">0x0</field> + </register> + <register address="0x000003B3" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR3"> + <field Type="RW" name="CSR_PMPADDR3" offset="0" width="64">0x0</field> + </register> + <register address="0x000003B4" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR4"> + <field Type="RW" name="CSR_PMPADDR4" offset="0" width="64">0x0</field> + </register> + <register address="0x000003B5" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR5"> + <field Type="RW" name="CSR_PMPADDR5" offset="0" width="64">0x0</field> + </register> + <register address="0x000003B6" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR6"> + <field Type="RW" name="CSR_PMPADDR6" offset="0" width="64">0x0</field> + </register> + <register address="0x000003B7" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR7"> + <field Type="RW" name="CSR_PMPADDR7" offset="0" width="64">0x0</field> + </register> + <register address="0x000003B8" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR8"> + <field Type="RW" name="CSR_PMPADDR8" offset="0" width="64">0x0</field> + </register> + <register address="0x000003B9" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR9"> + <field Type="RW" name="CSR_PMPADDR9" offset="0" width="64">0x0</field> + </register> + <register address="0x00003B10" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR10"> + <field Type="RW" name="CSR_PMPADDR10" offset="0" width="64">0x0</field> + </register> + <register address="0x00003B11" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR11"> + <field Type="RW" name="CSR_PMPADDR11" offset="0" width="64">0x0</field> + </register> + <register address="0x00003B12" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR12"> + <field Type="RW" name="CSR_PMPADDR12" offset="0" width="64">0x0</field> + </register> + <register address="0x00003B13" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR13"> + <field Type="RW" name="CSR_PMPADDR13" offset="0" width="64">0x0</field> + </register> + <register address="0x00003B14" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR14"> + <field Type="RW" name="CSR_PMPADDR14" offset="0" width="64">0x0</field> + </register> + <register address="0x00003B15" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR15"> + <field Type="RW" name="CSR_PMPADDR15" offset="0" width="64">0x0</field> + </register> + </registers> + </pmp_h1> + <pmp_h2> + <registers> + <register address="0x000003A0" description="PMP configuration for 8 adress regions, bit 0 read, bit 1 write, bit 2 execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) " name="CSR_PMPCFG0"> + <field Type="RW" name="PMP0CFG" offset="0" width="8">0x9F</field> + <field Type="RW" name="PMP1CFG" offset="8" width="8">0x0</field> + <field Type="RW" name="PMP2CFG" offset="16" width="8">0x0</field> + <field Type="RW" name="PMP3CFG" offset="24" width="8">0x0</field> + <field Type="RW" name="PMP4CFG" offset="32" width="8">0x0</field> + <field Type="RW" name="PMP5CFG" offset="40" width="8">0x0</field> + <field Type="RW" name="PMP6CFG" offset="48" width="8">0x0</field> + <field Type="RW" name="PMP7CFG" offset="56" width="8">0x0</field> + </register> + <register address="0x000003A2" description="PMP configuration for 8 address regions, bit 0 read, bit 1 write, bit 2 execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) " name="CSR_PMPCFG2"> + <field Type="RW" name="PMP8CFG" offset="0" width="8">0x0</field> + <field Type="RW" name="PMP9CFG" offset="8" width="8">0x0</field> + <field Type="RW" name="PMP10CFG" offset="16" width="8">0x0</field> + <field Type="RW" name="PMP11CFG" offset="24" width="8">0x0</field> + <field Type="RW" name="PMP12CFG" offset="32" width="8">0x0</field> + <field Type="RW" name="PMP13CFG" offset="40" width="8">0x0</field> + <field Type="RW" name="PMP14CFG" offset="48" width="8">0x0</field> + <field Type="RW" name="PMP15CFG" offset="56" width="8">0x0</field> + </register> + <register address="0x000003B0" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR0"> + <field Type="RW" name="CSR_PMPADDR0" offset="0" width="64">0xFFFFFFFFFFFFFFFF</field> + </register> + <register address="0x000003B1" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR1"> + <field Type="RW" name="CSR_PMPADDR1" offset="0" width="64">0x0</field> + </register> + <register address="0x000003B2" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR2"> + <field Type="RW" name="CSR_PMPADDR2" offset="0" width="64">0x0</field> + </register> + <register address="0x000003B3" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR3"> + <field Type="RW" name="CSR_PMPADDR3" offset="0" width="64">0x0</field> + </register> + <register address="0x000003B4" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR4"> + <field Type="RW" name="CSR_PMPADDR4" offset="0" width="64">0x0</field> + </register> + <register address="0x000003B5" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR5"> + <field Type="RW" name="CSR_PMPADDR5" offset="0" width="64">0x0</field> + </register> + <register address="0x000003B6" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR6"> + <field Type="RW" name="CSR_PMPADDR6" offset="0" width="64">0x0</field> + </register> + <register address="0x000003B7" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR7"> + <field Type="RW" name="CSR_PMPADDR7" offset="0" width="64">0x0</field> + </register> + <register address="0x000003B8" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR8"> + <field Type="RW" name="CSR_PMPADDR8" offset="0" width="64">0x0</field> + </register> + <register address="0x000003B9" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR9"> + <field Type="RW" name="CSR_PMPADDR9" offset="0" width="64">0x0</field> + </register> + <register address="0x00003B10" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR10"> + <field Type="RW" name="CSR_PMPADDR10" offset="0" width="64">0x0</field> + </register> + <register address="0x00003B11" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR11"> + <field Type="RW" name="CSR_PMPADDR11" offset="0" width="64">0x0</field> + </register> + <register address="0x00003B12" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR12"> + <field Type="RW" name="CSR_PMPADDR12" offset="0" width="64">0x0</field> + </register> + <register address="0x00003B13" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR13"> + <field Type="RW" name="CSR_PMPADDR13" offset="0" width="64">0x0</field> + </register> + <register address="0x00003B14" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR14"> + <field Type="RW" name="CSR_PMPADDR14" offset="0" width="64">0x0</field> + </register> + <register address="0x00003B15" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR15"> + <field Type="RW" name="CSR_PMPADDR15" offset="0" width="64">0x0</field> + </register> + </registers> + </pmp_h2> + <pmp_h3> + <registers> + <register address="0x000003A0" description="PMP configuration for 8 adress regions, bit 0 read, bit 1 write, bit 2 execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) " name="CSR_PMPCFG0"> + <field Type="RW" name="PMP0CFG" offset="0" width="8">0x9F</field> + <field Type="RW" name="PMP1CFG" offset="8" width="8">0x0</field> + <field Type="RW" name="PMP2CFG" offset="16" width="8">0x0</field> + <field Type="RW" name="PMP3CFG" offset="24" width="8">0x0</field> + <field Type="RW" name="PMP4CFG" offset="32" width="8">0x0</field> + <field Type="RW" name="PMP5CFG" offset="40" width="8">0x0</field> + <field Type="RW" name="PMP6CFG" offset="48" width="8">0x0</field> + <field Type="RW" name="PMP7CFG" offset="56" width="8">0x0</field> + </register> + <register address="0x000003A2" description="PMP configuration for 8 address regions, bit 0 read, bit 1 write, bit 2 execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) " name="CSR_PMPCFG2"> + <field Type="RW" name="PMP8CFG" offset="0" width="8">0x0</field> + <field Type="RW" name="PMP9CFG" offset="8" width="8">0x0</field> + <field Type="RW" name="PMP10CFG" offset="16" width="8">0x0</field> + <field Type="RW" name="PMP11CFG" offset="24" width="8">0x0</field> + <field Type="RW" name="PMP12CFG" offset="32" width="8">0x0</field> + <field Type="RW" name="PMP13CFG" offset="40" width="8">0x0</field> + <field Type="RW" name="PMP14CFG" offset="48" width="8">0x0</field> + <field Type="RW" name="PMP15CFG" offset="56" width="8">0x0</field> + </register> + <register address="0x000003B0" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR0"> + <field Type="RW" name="CSR_PMPADDR0" offset="0" width="64">0xFFFFFFFFFFFFFFFF</field> + </register> + <register address="0x000003B1" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR1"> + <field Type="RW" name="CSR_PMPADDR1" offset="0" width="64">0x0</field> + </register> + <register address="0x000003B2" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR2"> + <field Type="RW" name="CSR_PMPADDR2" offset="0" width="64">0x0</field> + </register> + <register address="0x000003B3" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR3"> + <field Type="RW" name="CSR_PMPADDR3" offset="0" width="64">0x0</field> + </register> + <register address="0x000003B4" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR4"> + <field Type="RW" name="CSR_PMPADDR4" offset="0" width="64">0x0</field> + </register> + <register address="0x000003B5" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR5"> + <field Type="RW" name="CSR_PMPADDR5" offset="0" width="64">0x0</field> + </register> + <register address="0x000003B6" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR6"> + <field Type="RW" name="CSR_PMPADDR6" offset="0" width="64">0x0</field> + </register> + <register address="0x000003B7" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR7"> + <field Type="RW" name="CSR_PMPADDR7" offset="0" width="64">0x0</field> + </register> + <register address="0x000003B8" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR8"> + <field Type="RW" name="CSR_PMPADDR8" offset="0" width="64">0x0</field> + </register> + <register address="0x000003B9" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR9"> + <field Type="RW" name="CSR_PMPADDR9" offset="0" width="64">0x0</field> + </register> + <register address="0x00003B10" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR10"> + <field Type="RW" name="CSR_PMPADDR10" offset="0" width="64">0x0</field> + </register> + <register address="0x00003B11" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR11"> + <field Type="RW" name="CSR_PMPADDR11" offset="0" width="64">0x0</field> + </register> + <register address="0x00003B12" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR12"> + <field Type="RW" name="CSR_PMPADDR12" offset="0" width="64">0x0</field> + </register> + <register address="0x00003B13" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR13"> + <field Type="RW" name="CSR_PMPADDR13" offset="0" width="64">0x0</field> + </register> + <register address="0x00003B14" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR14"> + <field Type="RW" name="CSR_PMPADDR14" offset="0" width="64">0x0</field> + </register> + <register address="0x00003B15" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR15"> + <field Type="RW" name="CSR_PMPADDR15" offset="0" width="64">0x0</field> + </register> + </registers> + </pmp_h3> + <pmp_h4> + <registers> + <register address="0x000003A0" description="PMP configuration for 8 adress regions, bit 0 read, bit 1 write, bit 2 execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) " name="CSR_PMPCFG0"> + <field Type="RW" name="PMP0CFG" offset="0" width="8">0x9F</field> + <field Type="RW" name="PMP1CFG" offset="8" width="8">0x0</field> + <field Type="RW" name="PMP2CFG" offset="16" width="8">0x0</field> + <field Type="RW" name="PMP3CFG" offset="24" width="8">0x0</field> + <field Type="RW" name="PMP4CFG" offset="32" width="8">0x0</field> + <field Type="RW" name="PMP5CFG" offset="40" width="8">0x0</field> + <field Type="RW" name="PMP6CFG" offset="48" width="8">0x0</field> + <field Type="RW" name="PMP7CFG" offset="56" width="8">0x0</field> + </register> + <register address="0x000003A2" description="PMP configuration for 8 address regions, bit 0 read, bit 1 write, bit 2 execute, bit 7 disable, bits 3,4 address format (0x18 => NAPOT) " name="CSR_PMPCFG2"> + <field Type="RW" name="PMP8CFG" offset="0" width="8">0x0</field> + <field Type="RW" name="PMP9CFG" offset="8" width="8">0x0</field> + <field Type="RW" name="PMP10CFG" offset="16" width="8">0x0</field> + <field Type="RW" name="PMP11CFG" offset="24" width="8">0x0</field> + <field Type="RW" name="PMP12CFG" offset="32" width="8">0x0</field> + <field Type="RW" name="PMP13CFG" offset="40" width="8">0x0</field> + <field Type="RW" name="PMP14CFG" offset="48" width="8">0x0</field> + <field Type="RW" name="PMP15CFG" offset="56" width="8">0x0</field> + </register> + <register address="0x000003B0" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR0"> + <field Type="RW" name="CSR_PMPADDR0" offset="0" width="64">0xFFFFFFFFFFFFFFFF</field> + </register> + <register address="0x000003B1" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR1"> + <field Type="RW" name="CSR_PMPADDR1" offset="0" width="64">0x0</field> + </register> + <register address="0x000003B2" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR2"> + <field Type="RW" name="CSR_PMPADDR2" offset="0" width="64">0x0</field> + </register> + <register address="0x000003B3" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR3"> + <field Type="RW" name="CSR_PMPADDR3" offset="0" width="64">0x0</field> + </register> + <register address="0x000003B4" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR4"> + <field Type="RW" name="CSR_PMPADDR4" offset="0" width="64">0x0</field> + </register> + <register address="0x000003B5" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR5"> + <field Type="RW" name="CSR_PMPADDR5" offset="0" width="64">0x0</field> + </register> + <register address="0x000003B6" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR6"> + <field Type="RW" name="CSR_PMPADDR6" offset="0" width="64">0x0</field> + </register> + <register address="0x000003B7" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR7"> + <field Type="RW" name="CSR_PMPADDR7" offset="0" width="64">0x0</field> + </register> + <register address="0x000003B8" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR8"> + <field Type="RW" name="CSR_PMPADDR8" offset="0" width="64">0x0</field> + </register> + <register address="0x000003B9" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR9"> + <field Type="RW" name="CSR_PMPADDR9" offset="0" width="64">0x0</field> + </register> + <register address="0x00003B10" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR10"> + <field Type="RW" name="CSR_PMPADDR10" offset="0" width="64">0x0</field> + </register> + <register address="0x00003B11" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR11"> + <field Type="RW" name="CSR_PMPADDR11" offset="0" width="64">0x0</field> + </register> + <register address="0x00003B12" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR12"> + <field Type="RW" name="CSR_PMPADDR12" offset="0" width="64">0x0</field> + </register> + <register address="0x00003B13" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR13"> + <field Type="RW" name="CSR_PMPADDR13" offset="0" width="64">0x0</field> + </register> + <register address="0x00003B14" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR14"> + <field Type="RW" name="CSR_PMPADDR14" offset="0" width="64">0x0</field> + </register> + <register address="0x00003B15" description="PMP ADRESS and size, format determined from bit 3 and 4 of configuration byte in CSR_PMPCFGx" name="CSR_PMPADDR15"> + <field Type="RW" name="CSR_PMPADDR15" offset="0" width="64">0x0</field> + </register> + </registers> + </pmp_h4> + <mpu_fic0> + <registers> + <register address="0x00000000" description="mpu setup register, 64 bits" name="MPU_CFG_PMP0"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000008" description="mpu setup register, 64 bits" name="MPU_CFG_PMP1"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000016" description="pmp setup register, 64 bits" name="MPU_CFG_PMP2"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000024" description="pmp setup register, 64 bits" name="MPU_CFG_PMP3"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000032" description="pmp setup register, 64 bits" name="MPU_CFG_PMP4"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000040" description="pmp setup register, 64 bits" name="MPU_CFG_PMP5"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000048" description="pmp setup register, 64 bits" name="MPU_CFG_PMP6"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000056" description="pmp setup register, 64 bits" name="MPU_CFG_PMP7"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000064" description="pmp setup register, 64 bits" name="MPU_CFG_PMP8"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000072" description="pmp setup register, 64 bits" name="MPU_CFG_PMP9"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000080" description="pmp setup register, 64 bits" name="MPU_CFG_PMP10"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000088" description="pmp setup register, 64 bits" name="MPU_CFG_PMP11"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000096" description="pmp setup register, 64 bits" name="MPU_CFG_PMP12"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000104" description="pmp setup register, 64 bits" name="MPU_CFG_PMP13"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000112" description="pmp setup register, 64 bits" name="MPU_CFG_PMP14"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000120" description="pmp setup register, 64 bits" name="MPU_CFG_PMP15"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + </registers> + </mpu_fic0> + <mpu_fic1> + <registers> + <register address="0x00000000" description="mpu setup register, 64 bits" name="MPU_CFG_PMP0"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000008" description="mpu setup register, 64 bits" name="MPU_CFG_PMP1"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000016" description="pmp setup register, 64 bits" name="MPU_CFG_PMP2"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000024" description="pmp setup register, 64 bits" name="MPU_CFG_PMP3"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000032" description="pmp setup register, 64 bits" name="MPU_CFG_PMP4"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000040" description="pmp setup register, 64 bits" name="MPU_CFG_PMP5"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000048" description="pmp setup register, 64 bits" name="MPU_CFG_PMP6"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000056" description="pmp setup register, 64 bits" name="MPU_CFG_PMP7"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000064" description="pmp setup register, 64 bits" name="MPU_CFG_PMP8"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000072" description="pmp setup register, 64 bits" name="MPU_CFG_PMP9"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000080" description="pmp setup register, 64 bits" name="MPU_CFG_PMP10"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000088" description="pmp setup register, 64 bits" name="MPU_CFG_PMP11"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000096" description="pmp setup register, 64 bits" name="MPU_CFG_PMP12"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000104" description="pmp setup register, 64 bits" name="MPU_CFG_PMP13"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000112" description="pmp setup register, 64 bits" name="MPU_CFG_PMP14"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000120" description="pmp setup register, 64 bits" name="MPU_CFG_PMP15"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + </registers> + </mpu_fic1> + <mpu_fic2> + <registers> + <register address="0x00000000" description="mpu setup register, 64 bits" name="MPU_CFG_PMP0"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000008" description="mpu setup register, 64 bits" name="MPU_CFG_PMP1"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000016" description="pmp setup register, 64 bits" name="MPU_CFG_PMP2"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000024" description="pmp setup register, 64 bits" name="MPU_CFG_PMP3"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000032" description="pmp setup register, 64 bits" name="MPU_CFG_PMP4"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000040" description="pmp setup register, 64 bits" name="MPU_CFG_PMP5"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000048" description="pmp setup register, 64 bits" name="MPU_CFG_PMP6"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000056" description="pmp setup register, 64 bits" name="MPU_CFG_PMP7"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + </registers> + </mpu_fic2> + <mpu_crypto> + <registers> + <register address="0x00000000" description="mpu setup register, 64 bits" name="MPU_CFG_PMP0"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000008" description="mpu setup register, 64 bits" name="MPU_CFG_PMP1"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000016" description="pmp setup register, 64 bits" name="MPU_CFG_PMP2"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000024" description="pmp setup register, 64 bits" name="MPU_CFG_PMP3"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + </registers> + </mpu_crypto> + <mpu_gem0> + <registers> + <register address="0x00000000" description="mpu setup register, 64 bits" name="MPU_CFG_PMP0"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000008" description="mpu setup register, 64 bits" name="MPU_CFG_PMP1"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000016" description="pmp setup register, 64 bits" name="MPU_CFG_PMP2"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000024" description="pmp setup register, 64 bits" name="MPU_CFG_PMP3"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000032" description="pmp setup register, 64 bits" name="MPU_CFG_PMP4"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000040" description="pmp setup register, 64 bits" name="MPU_CFG_PMP5"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000048" description="pmp setup register, 64 bits" name="MPU_CFG_PMP6"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000056" description="pmp setup register, 64 bits" name="MPU_CFG_PMP7"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + </registers> + </mpu_gem0> + <mpu_gem1> + <registers> + <register address="0x00000000" description="mpu setup register, 64 bits" name="MPU_CFG_PMP0"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000008" description="mpu setup register, 64 bits" name="MPU_CFG_PMP1"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000016" description="pmp setup register, 64 bits" name="MPU_CFG_PMP2"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000024" description="pmp setup register, 64 bits" name="MPU_CFG_PMP3"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000032" description="pmp setup register, 64 bits" name="MPU_CFG_PMP4"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000040" description="pmp setup register, 64 bits" name="MPU_CFG_PMP5"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000048" description="pmp setup register, 64 bits" name="MPU_CFG_PMP6"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000056" description="pmp setup register, 64 bits" name="MPU_CFG_PMP7"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + </registers> + </mpu_gem1> + <mpu_usb> + <registers> + <register address="0x00000000" description="mpu setup register, 64 bits" name="MPU_CFG_PMP0"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000008" description="mpu setup register, 64 bits" name="MPU_CFG_PMP1"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000016" description="pmp setup register, 64 bits" name="MPU_CFG_PMP2"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000024" description="pmp setup register, 64 bits" name="MPU_CFG_PMP3"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + </registers> + </mpu_usb> + <mpu_mmc> + <registers> + <register address="0x00000000" description="mpu setup register, 64 bits" name="MPU_CFG_PMP0"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000008" description="mpu setup register, 64 bits" name="MPU_CFG_PMP1"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000016" description="pmp setup register, 64 bits" name="MPU_CFG_PMP2"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000024" description="pmp setup register, 64 bits" name="MPU_CFG_PMP3"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + </registers> + </mpu_mmc> + <mpu_scb> + <registers> + <register address="0x00000000" description="mpu setup register, 64 bits" name="MPU_CFG_PMP0"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000008" description="mpu setup register, 64 bits" name="MPU_CFG_PMP1"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000016" description="pmp setup register, 64 bits" name="MPU_CFG_PMP2"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000024" description="pmp setup register, 64 bits" name="MPU_CFG_PMP3"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000032" description="pmp setup register, 64 bits" name="MPU_CFG_PMP4"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000040" description="pmp setup register, 64 bits" name="MPU_CFG_PMP5"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000048" description="pmp setup register, 64 bits" name="MPU_CFG_PMP6"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000056" description="pmp setup register, 64 bits" name="MPU_CFG_PMP7"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + </registers> + </mpu_scb> + <mpu_trace> + <registers> + <register address="0x00000000" description="mpu setup register, 64 bits" name="MPU_CFG_PMP0"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + <register address="0x00000008" description="mpu setup register, 64 bits" name="MPU_CFG_PMP1"> + <field Type="RW" name="PMP" offset="0" width="38">0xFFFFFFFFF</field> + <field Type="RW" name="RESERVED" offset="38" width="18">0x0</field> + <field Type="RW" name="MODE" offset="56" width="8">0x1F</field> + </register> + </registers> + </mpu_trace> + <nvm_map> + <registers> + <register address="0" description="Page offset to start page of sNVM available to MSS. Each SNVM module may be stored in any of the following formats, Non-authenticated plaintext, Authenticated plaintext, Authenticated ciphertext. When the data is authenticated 236 bytes of storage per page is available. When the data is not authenticated 252 bytes may be stored. (Note: Value in decimal)" name="SNVM_MSS_START_PAGE"> + <field Type="RW" name="START_PAGE_OFFSET" offset="0" width="32">0</field> + </register> + <register address="0" description="Page offset to end page of sNVM available to MSS (Note: Value in decimal)" name="SNVM_MSS_END_PAGE"> + <field Type="RW" name="END_PAGE_OFFSET" offset="0" width="32">220</field> + </register> + <register address="0" description="Page offset to start page of sNVM available to MSS (Note: Value in decimal)" name="ENVM_MSS_START_PAGE"> + <field Type="RW" name="START_PAGE_OFFSET" offset="0" width="32">0</field> + </register> + <register address="0" description="Page offset to end page of sNVM available to MSS (Note: Value in decimal)" name="ENVM_MSS_END_PAGE"> + <field Type="RW" name="END_PAGE_OFFSET" offset="0" width="32">511</field> + </register> + </registers> + </nvm_map> + </mss_memory_map> + <mss_io> + <io_mux> + <registers> + <register address="0x00000200" description="Selects whether the peripheral is connected to the Fabric or IOMUX structure." name="IOMUX0_CR"> + <field Type="RW" name="SPI0_FABRIC" offset="0" width="1">0x1</field> + <field Type="RW" name="SPI1_FABRIC" offset="1" width="1">0x0</field> + <field Type="RW" name="I2C0_FABRIC" offset="2" width="1">0x1</field> + <field Type="RW" name="I2C1_FABRIC" offset="3" width="1">0x1</field> + <field Type="RW" name="CAN0_FABRIC" offset="4" width="1">0x1</field> + <field Type="RW" name="CAN1_FABRIC" offset="5" width="1">0x0</field> + <field Type="RW" name="QSPI_FABRIC" offset="6" width="1">0x0</field> + <field Type="RW" name="MMUART0_FABRIC" offset="7" width="1">0x1</field> + <field Type="RW" name="MMUART1_FABRIC" offset="8" width="1">0x1</field> + <field Type="RW" name="MMUART2_FABRIC" offset="9" width="1">0x1</field> + <field Type="RW" name="MMUART3_FABRIC" offset="10" width="1">0x1</field> + <field Type="RW" name="MMUART4_FABRIC" offset="11" width="1">0x1</field> + <field Type="RW" name="MDIO0_FABRIC" offset="12" width="1">0x0</field> + <field Type="RW" name="MDIO1_FABRIC" offset="13" width="1">0x0</field> + </register> + <register address="0x00000204" description="Configures the IO Mux structure for each IO pad. 0 implies SD/SDIO, 1 implies EMMC, 2 implies QSPI, 3 implies SPI,4 implies USB,5 implies MMUART,6 implies I2C,7 implies CAN,8 implies MDIO,9 implies Miscellaneous,0xA implies Reserved (Equivalent to Tristate),0xB implies GPIO ,0xC implies Fabric-test,0xD implies Logic 0,0xE implies Logic 1, 0xF implies Tristate" name="IOMUX1_CR"> + <field Type="RW" name="PAD0" offset="0" width="4">0x1</field> + <field Type="RW" name="PAD1" offset="4" width="4">0x1</field> + <field Type="RW" name="PAD2" offset="8" width="4">0x1</field> + <field Type="RW" name="PAD3" offset="12" width="4">0x1</field> + <field Type="RW" name="PAD4" offset="16" width="4">0x1</field> + <field Type="RW" name="PAD5" offset="20" width="4">0x1</field> + <field Type="RW" name="PAD6" offset="24" width="4">0x1</field> + <field Type="RW" name="PAD7" offset="28" width="4">0x1</field> + </register> + <register address="0x00000208" description="Configures the IO Mux structure for each IO pad. 0 implies SD/SDIO, 1 implies EMMC, 2 implies QSPI, 3 implies SPI,4 implies USB,5 implies MMUART,6 implies I2C,7 implies CAN,8 implies MDIO,9 implies Miscellaneous,0xA implies Reserved (Equivalent to Tristate),0xB implies GPIO ,0xC implies Fabric-test,0xD implies Logic 0,0xE implies Logic 1, 0xF implies Tristate" name="IOMUX2_CR"> + <field Type="RW" name="PAD8" offset="0" width="4">0x1</field> + <field Type="RW" name="PAD9" offset="4" width="4">0x1</field> + <field Type="RW" name="PAD10" offset="8" width="4">0x1</field> + <field Type="RW" name="PAD11" offset="12" width="4">0x1</field> + <field Type="RW" name="PAD12" offset="16" width="4">0xF</field> + <field Type="RW" name="PAD13" offset="20" width="4">0xF</field> + </register> + <register address="0x0000020C" description="Configures the IO Mux structure for each IO pad. 0 implies SD/SDIO, 1 implies EMMC, 2 implies QSPI, 3 implies SPI,4 implies USB,5 implies MMUART,6 implies I2C,7 implies CAN,8 implies MDIO,9 implies Miscellaneous,0xA implies Reserved (Equivalent to Tristate),0xB implies GPIO ,0xC implies Fabric-test,0xD implies Logic 0,0xE implies Logic 1, 0xF implies Tristate" name="IOMUX3_CR"> + <field Type="RW" name="PAD14" offset="0" width="4">0x4</field> + <field Type="RW" name="PAD15" offset="4" width="4">0x4</field> + <field Type="RW" name="PAD16" offset="8" width="4">0x4</field> + <field Type="RW" name="PAD17" offset="12" width="4">0x4</field> + <field Type="RW" name="PAD18" offset="16" width="4">0x4</field> + <field Type="RW" name="PAD19" offset="20" width="4">0x4</field> + <field Type="RW" name="PAD20" offset="24" width="4">0x4</field> + <field Type="RW" name="PAD21" offset="28" width="4">0x4</field> + </register> + <register address="0x00000210" description="Configures the IO Mux structure for each IO pad. 0 implies SD/SDIO, 1 implies EMMC, 2 implies QSPI, 3 implies SPI,4 implies USB,5 implies MMUART,6 implies I2C,7 implies CAN,8 implies MDIO,9 implies Miscellaneous,0xA implies Reserved (Equivalent to Tristate),0xB implies GPIO ,0xC implies Fabric-test,0xD implies Logic 0,0xE implies Logic 1, 0xF implies Tristate" name="IOMUX4_CR"> + <field Type="RW" name="PAD22" offset="0" width="4">0x4</field> + <field Type="RW" name="PAD23" offset="4" width="4">0x4</field> + <field Type="RW" name="PAD24" offset="8" width="4">0x4</field> + <field Type="RW" name="PAD25" offset="12" width="4">0x4</field> + <field Type="RW" name="PAD26" offset="16" width="4">0xC</field> + <field Type="RW" name="PAD27" offset="20" width="4">0xC</field> + <field Type="RW" name="PAD28" offset="24" width="4">0x8</field> + <field Type="RW" name="PAD29" offset="28" width="4">0x8</field> + </register> + <register address="0x00000214" description="Configures the IO Mux structure for each IO pad. 0 implies SD/SDIO, 1 implies EMMC, 2 implies QSPI, 3 implies SPI,4 implies USB,5 implies MMUART,6 implies I2C,7 implies CAN,8 implies MDIO,9 implies Miscellaneous,0xA implies Reserved (Equivalent to Tristate),0xB implies GPIO ,0xC implies Fabric-test,0xD implies Logic 0,0xE implies Logic 1, 0xF implies Tristate" name="IOMUX5_CR"> + <field Type="RW" name="PAD30" offset="0" width="4">0x2</field> + <field Type="RW" name="PAD31" offset="4" width="4">0x2</field> + <field Type="RW" name="PAD32" offset="8" width="4">0x2</field> + <field Type="RW" name="PAD33" offset="12" width="4">0x2</field> + <field Type="RW" name="PAD34" offset="16" width="4">0x7</field> + <field Type="RW" name="PAD35" offset="20" width="4">0x7</field> + <field Type="RW" name="PAD36" offset="24" width="4">0x7</field> + <field Type="RW" name="PAD37" offset="28" width="4">0xF</field> + </register> + <register address="0x00000218" description="Sets whether the MMC/SD Voltage select lines are inverted on entry to the IOMUX structure" name="IOMUX6_CR"> + <field Type="RW" name="VLT_SEL" offset="0" width="1">0x0</field> + <field Type="RW" name="VLT_EN" offset="1" width="1">0x0</field> + <field Type="RW" name="VLT_CMD_DIR" offset="2" width="1">0x0</field> + <field Type="RW" name="VLT_DIR_0" offset="3" width="1">0x0</field> + <field Type="RW" name="VLT_DIR_1_3" offset="4" width="1">0x0</field> + <field Type="RW" name="SD_LED" offset="5" width="1">0x0</field> + <field Type="RW" name="SD_VOLT_0" offset="6" width="1">0x0</field> + <field Type="RW" name="SD_VOLT_1" offset="7" width="1">0x0</field> + <field Type="RW" name="SD_VOLT_2" offset="8" width="1">0x0</field> + </register> + <register address="0x00000230" description="Configures the MSSIO block using SCB write" name="MSSIO_BANK4_CFG_CR"> + <field Type="RW" name="BANK_PCODE" offset="0" width="6">0xD</field> + <field Type="RW" name="RESERVED0" offset="6" width="2">0x00</field> + <field Type="RW" name="BANK_NCODE" offset="8" width="6">0xA</field> + <field Type="RW" name="RESERVED1" offset="14" width="2">0x0</field> + <field Type="RW" name="VS" offset="16" width="4">0x4</field> + <field Type="RW" name="RESERVED2" offset="20" width="12">0x0</field> + </register> + <register address="0x00000234" description="IO electrical configuration for MSSIO pad" name="MSSIO_BANK4_IO_CFG_0_1_CR"> + <field Type="RW" name="IO_CFG_0" offset="0" width="16">0x0928</field> + <field Type="RW" name="IO_CFG_1" offset="16" width="16">0x0928</field> + </register> + <register address="0x00000238" description="IO electrical configuration for MSSIO pad" name="MSSIO_BANK4_IO_CFG_2_3_CR"> + <field Type="RW" name="IO_CFG_2" offset="0" width="16">0x0928</field> + <field Type="RW" name="IO_CFG_3" offset="16" width="16">0x0928</field> + </register> + <register address="0x0000023C" description="IO electrical configuration for MSSIO pad" name="MSSIO_BANK4_IO_CFG_4_5_CR"> + <field Type="RW" name="IO_CFG_4" offset="0" width="16">0x0928</field> + <field Type="RW" name="IO_CFG_5" offset="16" width="16">0x0928</field> + </register> + <register address="0x00000240" description="IO electrical configuration for MSSIO pad" name="MSSIO_BANK4_IO_CFG_6_7_CR"> + <field Type="RW" name="IO_CFG_6" offset="0" width="16">0x0928</field> + <field Type="RW" name="IO_CFG_7" offset="16" width="16">0x0928</field> + </register> + <register address="0x00000244" description="IO electrical configuration for MSSIO pad" name="MSSIO_BANK4_IO_CFG_8_9_CR"> + <field Type="RW" name="IO_CFG_8" offset="0" width="16">0x0928</field> + <field Type="RW" name="IO_CFG_9" offset="16" width="16">0x0928</field> + </register> + <register address="0x00000248" description="IO electrical configuration for MSSIO pad" name="MSSIO_BANK4_IO_CFG_10_11_CR"> + <field Type="RW" name="IO_CFG_10" offset="0" width="16">0x0928</field> + <field Type="RW" name="IO_CFG_11" offset="16" width="16">0x0928</field> + </register> + <register address="0x0000024C" description="IO electrical configuration for MSSIO pad" name="MSSIO_BANK4_IO_CFG_12_13_CR"> + <field Type="RW" name="IO_CFG_12" offset="0" width="16">0x0928</field> + <field Type="RW" name="IO_CFG_13" offset="16" width="16">0x0928</field> + </register> + <register address="0x00000250" description="Configures the MSSIO block using SCB write" name="MSSIO_BANK2_CFG_CR"> + <field Type="RW" name="BANK_PCODE" offset="0" width="6">0x7</field> + <field Type="RW" name="RESERVED0" offset="6" width="2">0x00</field> + <field Type="RW" name="BANK_NCODE" offset="8" width="6">0x9</field> + <field Type="RW" name="RESERVED1" offset="14" width="2">0x0</field> + <field Type="RW" name="VS" offset="16" width="4">0x8</field> + <field Type="RW" name="RESERVED2" offset="20" width="12">0x0</field> + </register> + <register address="0x00000254" description="IO electrical configuration for MSSIO pad" name="MSSIO_BANK2_IO_CFG_0_1_CR"> + <field Type="RW" name="IO_CFG_0" offset="0" width="16">0x0829</field> + <field Type="RW" name="IO_CFG_1" offset="16" width="16">0x0829</field> + </register> + <register address="0x00000258" description="IO electrical configuration for MSSIO pad" name="MSSIO_BANK2_IO_CFG_2_3_CR"> + <field Type="RW" name="IO_CFG_2" offset="0" width="16">0x0829</field> + <field Type="RW" name="IO_CFG_3" offset="16" width="16">0x0829</field> + </register> + <register address="0x0000025C" description="IO electrical configuration for MSSIO pad" name="MSSIO_BANK2_IO_CFG_4_5_CR"> + <field Type="RW" name="IO_CFG_4" offset="0" width="16">0x0829</field> + <field Type="RW" name="IO_CFG_5" offset="16" width="16">0x0829</field> + </register> + <register address="0x00000260" description="IO electrical configuration for MSSIO pad" name="MSSIO_BANK2_IO_CFG_6_7_CR"> + <field Type="RW" name="IO_CFG_6" offset="0" width="16">0x0829</field> + <field Type="RW" name="IO_CFG_7" offset="16" width="16">0x0829</field> + </register> + <register address="0x00000264" description="IO electrical configuration for MSSIO pad" name="MSSIO_BANK2_IO_CFG_8_9_CR"> + <field Type="RW" name="IO_CFG_8" offset="0" width="16">0x0829</field> + <field Type="RW" name="IO_CFG_9" offset="16" width="16">0x0829</field> + </register> + <register address="0x00000268" description="IO electrical configuration for MSSIO pad" name="MSSIO_BANK2_IO_CFG_10_11_CR"> + <field Type="RW" name="IO_CFG_10" offset="0" width="16">0x0829</field> + <field Type="RW" name="IO_CFG_11" offset="16" width="16">0x0829</field> + </register> + <register address="0x0000026C" description="IO electrical configuration for MSSIO pad" name="MSSIO_BANK2_IO_CFG_12_13_CR"> + <field Type="RW" name="IO_CFG_12" offset="0" width="16">0x0829</field> + <field Type="RW" name="IO_CFG_13" offset="16" width="16">0x0829</field> + </register> + <register address="0x00000270" description="IO electrical configuration for MSSIO pad" name="MSSIO_BANK2_IO_CFG_14_15_CR"> + <field Type="RW" name="IO_CFG_14" offset="0" width="16">0x0829</field> + <field Type="RW" name="IO_CFG_15" offset="16" width="16">0x0829</field> + </register> + <register address="0x00000274" description="IO electrical configuration for MSSIO pad" name="MSSIO_BANK2_IO_CFG_16_17_CR"> + <field Type="RW" name="IO_CFG_16" offset="0" width="16">0x0829</field> + <field Type="RW" name="IO_CFG_17" offset="16" width="16">0x0829</field> + </register> + <register address="0x00000278" description="IO electrical configuration for MSSIO pad" name="MSSIO_BANK2_IO_CFG_18_19_CR"> + <field Type="RW" name="IO_CFG_18" offset="0" width="16">0x0829</field> + <field Type="RW" name="IO_CFG_19" offset="16" width="16">0x0829</field> + </register> + <register address="0x0000027C" description="IO electrical configuration for MSSIO pad" name="MSSIO_BANK2_IO_CFG_20_21_CR"> + <field Type="RW" name="IO_CFG_20" offset="0" width="16">0x0829</field> + <field Type="RW" name="IO_CFG_21" offset="16" width="16">0x0829</field> + </register> + <register address="0x00000280" description="IO electrical configuration for MSSIO pad" name="MSSIO_BANK2_IO_CFG_22_23_CR"> + <field Type="RW" name="IO_CFG_22" offset="0" width="16">0x0829</field> + <field Type="RW" name="IO_CFG_23" offset="16" width="16">0x0829</field> + </register> + <register address="0x00000278" description="default dpc values for MSSIO bank 2 " name="MSSIO_VB2_CFG"> + <field Type="RW" name="DPC_IO_CFG_IBUFMD_0" offset="0" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_IBUFMD_1" offset="1" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_IBUFMD_2" offset="2" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_DRV_0" offset="3" width="1">0x1</field> + <field Type="RW" name="DPC_IO_CFG_DRV_1" offset="4" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_DRV_2" offset="5" width="1">0x1</field> + <field Type="RW" name="DPC_IO_CFG_DRV_3" offset="6" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_CLAMP" offset="7" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_ENHYST" offset="8" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_LOCKDN_EN" offset="9" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_WPD" offset="10" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_WPU" offset="11" width="1">0x1</field> + <field Type="RW" name="DPC_IO_CFG_ATP_EN" offset="12" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_LP_PERSIST_EN" offset="13" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_LP_BYPASS_EN" offset="14" width="1">0x0</field> + <field Type="R" name="RESERVED" offset="15" width="17">0x0</field> + </register> + <register address="0x0000027C" description="default dpc values for MSSIO bank 4 " name="MSSIO_VB4_CFG"> + <field Type="RW" name="DPC_IO_CFG_IBUFMD_0" offset="0" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_IBUFMD_1" offset="1" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_IBUFMD_2" offset="2" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_DRV_0" offset="3" width="1">0x1</field> + <field Type="RW" name="DPC_IO_CFG_DRV_1" offset="4" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_DRV_2" offset="5" width="1">0x1</field> + <field Type="RW" name="DPC_IO_CFG_DRV_3" offset="6" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_CLAMP" offset="7" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_ENHYST" offset="8" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_LOCKDN_EN" offset="9" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_WPD" offset="10" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_WPU" offset="11" width="1">0x1</field> + <field Type="RW" name="DPC_IO_CFG_ATP_EN" offset="12" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_LP_PERSIST_EN" offset="13" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_LP_BYPASS_EN" offset="14" width="1">0x0</field> + <field Type="R" name="RESERVED" offset="15" width="17">0x0</field> + </register> + <register address="0x0000027C" description="Indicates if eMMC is configured for use (bit 0 == 1), If SD is configued for use (bit 1 == 1). Bit 2 indicates which one should be used by default on MSS embedded software startup ( bit2 == 0, implies default is eMMC, bit2 == 1, implies default is SD). The eMMC configuration is always defined in xml tag (io_mux, the SD configuration is always defined in xml tag (io_mux_alt). All other elements in the (o_mux) and (io_mux_alt) not releating to eMMC/SD differences should be the same values." name="MSSIO_CONFIGURATION_OPTIONS"> + <field Type="RW" name="EMMC_CONFIGURED" offset="0" width="1">0x0</field> + <field Type="RW" name="SD_CONFIGURED" offset="1" width="1">0x0</field> + <field Type="RW" name="DEFAULT_ON_START" offset="2" width="1">0x0</field> + </register> + </registers> + </io_mux> + <io_mux_alt> + <registers> + <register address="0x00000200" description="Selects whether the peripheral is connected to the Fabric or IOMUX structure." name="ALT_IOMUX0_CR"> + <field Type="RW" name="SPI0_FABRIC" offset="0" width="1">0x0</field> + <field Type="RW" name="SPI1_FABRIC" offset="1" width="1">0x0</field> + <field Type="RW" name="I2C0_FABRIC" offset="2" width="1">0x0</field> + <field Type="RW" name="I2C1_FABRIC" offset="3" width="1">0x0</field> + <field Type="RW" name="CAN0_FABRIC" offset="4" width="1">0x0</field> + <field Type="RW" name="CAN1_FABRIC" offset="5" width="1">0x0</field> + <field Type="RW" name="QSPI_FABRIC" offset="6" width="1">0x0</field> + <field Type="RW" name="MMUART0_FABRIC" offset="7" width="1">0x0</field> + <field Type="RW" name="MMUART1_FABRIC" offset="8" width="1">0x0</field> + <field Type="RW" name="MMUART2_FABRIC" offset="9" width="1">0x0</field> + <field Type="RW" name="MMUART3_FABRIC" offset="10" width="1">0x0</field> + <field Type="RW" name="MMUART4_FABRIC" offset="11" width="1">0x0</field> + <field Type="RW" name="MDIO0_FABRIC" offset="12" width="1">0x0</field> + <field Type="RW" name="MDIO1_FABRIC" offset="13" width="1">0x0</field> + </register> + <register address="0x00000204" description="Configures the IO Mux structure for each IO pad. 0 implies SD/SDIO, 1 implies EMMC, 2 implies QSPI, 3 implies SPI,4 implies USB,5 implies MMUART,6 implies I2C,7 implies CAN,8 implies MDIO,9 implies Miscellaneous,0xA implies Reserved (Equivalent to Tristate),0xB implies GPIO ,0xC implies Fabric-test,0xD implies Logic 0,0xE implies Logic 1, 0xF implies Tristate" name="ALT_IOMUX1_CR"> + <field Type="RW" name="PAD0" offset="0" width="4">0x0</field> + <field Type="RW" name="PAD1" offset="4" width="4">0x0</field> + <field Type="RW" name="PAD2" offset="8" width="4">0x0</field> + <field Type="RW" name="PAD3" offset="12" width="4">0x0</field> + <field Type="RW" name="PAD4" offset="16" width="4">0x0</field> + <field Type="RW" name="PAD5" offset="20" width="4">0x0</field> + <field Type="RW" name="PAD6" offset="24" width="4">0x0</field> + <field Type="RW" name="PAD7" offset="28" width="4">0x0</field> + </register> + <register address="0x00000208" description="Configures the IO Mux structure for each IO pad. 0 implies SD/SDIO, 1 implies EMMC, 2 implies QSPI, 3 implies SPI,4 implies USB,5 implies MMUART,6 implies I2C,7 implies CAN,8 implies MDIO,9 implies Miscellaneous,0xA implies Reserved (Equivalent to Tristate),0xB implies GPIO ,0xC implies Fabric-test,0xD implies Logic 0,0xE implies Logic 1, 0xF implies Tristate" name="ALT_IOMUX2_CR"> + <field Type="RW" name="PAD8" offset="0" width="4">0x0</field> + <field Type="RW" name="PAD9" offset="4" width="4">0x0</field> + <field Type="RW" name="PAD10" offset="8" width="4">0x0</field> + <field Type="RW" name="PAD11" offset="12" width="4">0x0</field> + <field Type="RW" name="PAD12" offset="16" width="4">0x0</field> + <field Type="RW" name="PAD13" offset="20" width="4">0x0</field> + </register> + <register address="0x0000020C" description="Configures the IO Mux structure for each IO pad. 0 implies SD/SDIO, 1 implies EMMC, 2 implies QSPI, 3 implies SPI,4 implies USB,5 implies MMUART,6 implies I2C,7 implies CAN,8 implies MDIO,9 implies Miscellaneous,0xA implies Reserved (Equivalent to Tristate),0xB implies GPIO ,0xC implies Fabric-test,0xD implies Logic 0,0xE implies Logic 1, 0xF implies Tristate" name="ALT_IOMUX3_CR"> + <field Type="RW" name="PAD14" offset="0" width="4">0x0</field> + <field Type="RW" name="PAD15" offset="4" width="4">0x0</field> + <field Type="RW" name="PAD16" offset="8" width="4">0x0</field> + <field Type="RW" name="PAD17" offset="12" width="4">0x0</field> + <field Type="RW" name="PAD18" offset="16" width="4">0x0</field> + <field Type="RW" name="PAD19" offset="20" width="4">0x0</field> + <field Type="RW" name="PAD20" offset="24" width="4">0x0</field> + <field Type="RW" name="PAD21" offset="28" width="4">0x0</field> + </register> + <register address="0x00000210" description="Configures the IO Mux structure for each IO pad. 0 implies SD/SDIO, 1 implies EMMC, 2 implies QSPI, 3 implies SPI,4 implies USB,5 implies MMUART,6 implies I2C,7 implies CAN,8 implies MDIO,9 implies Miscellaneous,0xA implies Reserved (Equivalent to Tristate),0xB implies GPIO ,0xC implies Fabric-test,0xD implies Logic 0,0xE implies Logic 1, 0xF implies Tristate" name="ALT_IOMUX4_CR"> + <field Type="RW" name="PAD22" offset="0" width="4">0x0</field> + <field Type="RW" name="PAD23" offset="4" width="4">0x0</field> + <field Type="RW" name="PAD24" offset="8" width="4">0x0</field> + <field Type="RW" name="PAD25" offset="12" width="4">0x0</field> + <field Type="RW" name="PAD26" offset="16" width="4">0x0</field> + <field Type="RW" name="PAD27" offset="20" width="4">0x0</field> + <field Type="RW" name="PAD28" offset="24" width="4">0x0</field> + <field Type="RW" name="PAD29" offset="28" width="4">0x0</field> + </register> + <register address="0x00000214" description="Configures the IO Mux structure for each IO pad. 0 implies SD/SDIO, 1 implies EMMC, 2 implies QSPI, 3 implies SPI,4 implies USB,5 implies MMUART,6 implies I2C,7 implies CAN,8 implies MDIO,9 implies Miscellaneous,0xA implies Reserved (Equivalent to Tristate),0xB implies GPIO ,0xC implies Fabric-test,0xD implies Logic 0,0xE implies Logic 1, 0xF implies Tristate" name="ALT_IOMUX5_CR"> + <field Type="RW" name="PAD30" offset="0" width="4">0x0</field> + <field Type="RW" name="PAD31" offset="4" width="4">0x0</field> + <field Type="RW" name="PAD32" offset="8" width="4">0x0</field> + <field Type="RW" name="PAD33" offset="12" width="4">0x0</field> + <field Type="RW" name="PAD34" offset="16" width="4">0x0</field> + <field Type="RW" name="PAD35" offset="20" width="4">0x0</field> + <field Type="RW" name="PAD36" offset="24" width="4">0x0</field> + <field Type="RW" name="PAD37" offset="28" width="4">0x0</field> + </register> + <register address="0x00000218" description="Sets whether the MMC/SD Voltage select lines are inverted on entry to the IOMUX structure" name="ALT_IOMUX6_CR"> + <field Type="RW" name="VLT_SEL" offset="0" width="1">0x0</field> + <field Type="RW" name="VLT_EN" offset="1" width="1">0x0</field> + <field Type="RW" name="VLT_CMD_DIR" offset="2" width="1">0x0</field> + <field Type="RW" name="VLT_DIR_0" offset="3" width="1">0x0</field> + <field Type="RW" name="VLT_DIR_1_3" offset="4" width="1">0x0</field> + <field Type="RW" name="SD_LED" offset="5" width="1">0x0</field> + <field Type="RW" name="SD_VOLT_0" offset="6" width="1">0x0</field> + <field Type="RW" name="SD_VOLT_1" offset="7" width="1">0x0</field> + <field Type="RW" name="SD_VOLT_2" offset="8" width="1">0x0</field> + </register> + <register address="0x00000230" description="Configures the MSSIO block using SCB write" name="ALT_MSSIO_BANK4_CFG_CR"> + <field Type="RW" name="BANK_PCODE" offset="0" width="6">0x3F</field> + <field Type="RW" name="RESERVED0" offset="6" width="2">0x00</field> + <field Type="RW" name="BANK_NCODE" offset="8" width="6">0x3F</field> + <field Type="RW" name="RESERVED1" offset="14" width="2">0x0</field> + <field Type="RW" name="VS" offset="16" width="4">0x0</field> + <field Type="RW" name="RESERVED2" offset="20" width="12">0x0</field> + </register> + <register address="0x00000234" description="IO electrical configuration for MSSIO pad" name="ALT_MSSIO_BANK4_IO_CFG_0_1_CR"> + <field Type="RW" name="IO_CFG_0" offset="0" width="16">0x0</field> + <field Type="RW" name="IO_CFG_1" offset="16" width="16">0x0</field> + </register> + <register address="0x00000238" description="IO electrical configuration for MSSIO pad" name="ALT_MSSIO_BANK4_IO_CFG_2_3_CR"> + <field Type="RW" name="IO_CFG_2" offset="0" width="16">0x0</field> + <field Type="RW" name="IO_CFG_3" offset="16" width="16">0x0</field> + </register> + <register address="0x0000023C" description="IO electrical configuration for MSSIO pad" name="ALT_MSSIO_BANK4_IO_CFG_4_5_CR"> + <field Type="RW" name="IO_CFG_4" offset="0" width="16">0x0</field> + <field Type="RW" name="IO_CFG_5" offset="16" width="16">0x0</field> + </register> + <register address="0x00000240" description="IO electrical configuration for MSSIO pad" name="ALT_MSSIO_BANK4_IO_CFG_6_7_CR"> + <field Type="RW" name="IO_CFG_6" offset="0" width="16">0x0</field> + <field Type="RW" name="IO_CFG_7" offset="16" width="16">0x0</field> + </register> + <register address="0x00000244" description="IO electrical configuration for MSSIO pad" name="ALT_MSSIO_BANK4_IO_CFG_8_9_CR"> + <field Type="RW" name="IO_CFG_8" offset="0" width="16">0x0</field> + <field Type="RW" name="IO_CFG_9" offset="16" width="16">0x0</field> + </register> + <register address="0x00000248" description="IO electrical configuration for MSSIO pad" name="ALT_MSSIO_BANK4_IO_CFG_10_11_CR"> + <field Type="RW" name="IO_CFG_10" offset="0" width="16">0x0</field> + <field Type="RW" name="IO_CFG_11" offset="16" width="16">0x0</field> + </register> + <register address="0x0000024C" description="IO electrical configuration for MSSIO pad" name="ALT_MSSIO_BANK4_IO_CFG_12_13_CR"> + <field Type="RW" name="IO_CFG_12" offset="0" width="16">0x0</field> + <field Type="RW" name="IO_CFG_13" offset="16" width="16">0x0</field> + </register> + <register address="0x00000250" description="Configures the MSSIO block using SCB write" name="ALT_MSSIO_BANK2_CFG_CR"> + <field Type="RW" name="BANK_PCODE" offset="0" width="6">0x3F</field> + <field Type="RW" name="RESERVED0" offset="6" width="2">0x00</field> + <field Type="RW" name="BANK_NCODE" offset="8" width="6">0x3F</field> + <field Type="RW" name="RESERVED1" offset="14" width="2">0x0</field> + <field Type="RW" name="VS" offset="16" width="4">0x0</field> + <field Type="RW" name="RESERVED2" offset="20" width="12">0x0</field> + </register> + <register address="0x00000254" description="IO electrical configuration for MSSIO pad" name="ALT_MSSIO_BANK2_IO_CFG_0_1_CR"> + <field Type="RW" name="IO_CFG_0" offset="0" width="16">0x0</field> + <field Type="RW" name="IO_CFG_1" offset="16" width="16">0x0</field> + </register> + <register address="0x00000258" description="IO electrical configuration for MSSIO pad" name="ALT_MSSIO_BANK2_IO_CFG_2_3_CR"> + <field Type="RW" name="IO_CFG_2" offset="0" width="16">0x0</field> + <field Type="RW" name="IO_CFG_3" offset="16" width="16">0x0</field> + </register> + <register address="0x0000025C" description="IO electrical configuration for MSSIO pad" name="ALT_MSSIO_BANK2_IO_CFG_4_5_CR"> + <field Type="RW" name="IO_CFG_4" offset="0" width="16">0x0</field> + <field Type="RW" name="IO_CFG_5" offset="16" width="16">0x0</field> + </register> + <register address="0x00000260" description="IO electrical configuration for MSSIO pad" name="ALT_MSSIO_BANK2_IO_CFG_6_7_CR"> + <field Type="RW" name="IO_CFG_6" offset="0" width="16">0x0</field> + <field Type="RW" name="IO_CFG_7" offset="16" width="16">0x0</field> + </register> + <register address="0x00000264" description="IO electrical configuration for MSSIO pad" name="ALT_MSSIO_BANK2_IO_CFG_8_9_CR"> + <field Type="RW" name="IO_CFG_8" offset="0" width="16">0x0</field> + <field Type="RW" name="IO_CFG_9" offset="16" width="16">0x0</field> + </register> + <register address="0x00000268" description="IO electrical configuration for MSSIO pad" name="ALT_MSSIO_BANK2_IO_CFG_10_11_CR"> + <field Type="RW" name="IO_CFG_10" offset="0" width="16">0x0</field> + <field Type="RW" name="IO_CFG_11" offset="16" width="16">0x0</field> + </register> + <register address="0x0000026C" description="IO electrical configuration for MSSIO pad" name="ALT_MSSIO_BANK2_IO_CFG_12_13_CR"> + <field Type="RW" name="IO_CFG_12" offset="0" width="16">0x0</field> + <field Type="RW" name="IO_CFG_13" offset="16" width="16">0x0</field> + </register> + <register address="0x00000270" description="IO electrical configuration for MSSIO pad" name="ALT_MSSIO_BANK2_IO_CFG_14_15_CR"> + <field Type="RW" name="IO_CFG_14" offset="0" width="16">0x0</field> + <field Type="RW" name="IO_CFG_15" offset="16" width="16">0x0</field> + </register> + <register address="0x00000274" description="IO electrical configuration for MSSIO pad" name="ALT_MSSIO_BANK2_IO_CFG_16_17_CR"> + <field Type="RW" name="IO_CFG_16" offset="0" width="16">0x0</field> + <field Type="RW" name="IO_CFG_17" offset="16" width="16">0x0</field> + </register> + <register address="0x00000278" description="IO electrical configuration for MSSIO pad" name="ALT_MSSIO_BANK2_IO_CFG_18_19_CR"> + <field Type="RW" name="IO_CFG_18" offset="0" width="16">0x0</field> + <field Type="RW" name="IO_CFG_19" offset="16" width="16">0x0</field> + </register> + <register address="0x0000027C" description="IO electrical configuration for MSSIO pad" name="ALT_MSSIO_BANK2_IO_CFG_20_21_CR"> + <field Type="RW" name="IO_CFG_20" offset="0" width="16">0x0</field> + <field Type="RW" name="IO_CFG_21" offset="16" width="16">0x0</field> + </register> + <register address="0x00000280" description="IO electrical configuration for MSSIO pad" name="ALT_MSSIO_BANK2_IO_CFG_22_23_CR"> + <field Type="RW" name="IO_CFG_22" offset="0" width="16">0x0</field> + <field Type="RW" name="IO_CFG_23" offset="16" width="16">0x0</field> + </register> + <register address="0x00000278" description="default dpc values for MSSIO bank 2 " name="ALT_MSSIO_VB2_CFG"> + <field Type="RW" name="DPC_IO_CFG_IBUFMD_0" offset="0" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_IBUFMD_1" offset="1" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_IBUFMD_2" offset="2" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_DRV_0" offset="3" width="1">0x1</field> + <field Type="RW" name="DPC_IO_CFG_DRV_1" offset="4" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_DRV_2" offset="5" width="1">0x1</field> + <field Type="RW" name="DPC_IO_CFG_DRV_3" offset="6" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_CLAMP" offset="7" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_ENHYST" offset="8" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_LOCKDN_EN" offset="9" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_WPD" offset="10" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_WPU" offset="11" width="1">0x1</field> + <field Type="RW" name="DPC_IO_CFG_ATP_EN" offset="12" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_LP_PERSIST_EN" offset="13" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_LP_BYPASS_EN" offset="14" width="1">0x0</field> + <field Type="R" name="RESERVED" offset="15" width="17">0x0</field> + </register> + <register address="0x0000027C" description="default dpc values for MSSIO bank 4 " name="ALT_MSSIO_VB4_CFG"> + <field Type="RW" name="DPC_IO_CFG_IBUFMD_0" offset="0" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_IBUFMD_1" offset="1" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_IBUFMD_2" offset="2" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_DRV_0" offset="3" width="1">0x1</field> + <field Type="RW" name="DPC_IO_CFG_DRV_1" offset="4" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_DRV_2" offset="5" width="1">0x1</field> + <field Type="RW" name="DPC_IO_CFG_DRV_3" offset="6" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_CLAMP" offset="7" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_ENHYST" offset="8" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_LOCKDN_EN" offset="9" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_WPD" offset="10" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_WPU" offset="11" width="1">0x1</field> + <field Type="RW" name="DPC_IO_CFG_ATP_EN" offset="12" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_LP_PERSIST_EN" offset="13" width="1">0x0</field> + <field Type="RW" name="DPC_IO_CFG_LP_BYPASS_EN" offset="14" width="1">0x0</field> + <field Type="R" name="RESERVED" offset="15" width="17">0x0</field> + </register> + </registers> + </io_mux_alt> + <hsio> + <registers> + <register address="0x00000000" description="User trim options- set option to 1 to use" name="TRIM_OPTIONS"> + <field Type="" name="TRIM_DDR_OPTION" offset="0" width="1">0x0</field> + <field Type="" name="TRIM_SGMII_OPTION" offset="1" width="1">0x0</field> + </register> + <register address="0x00000000" description="Manual trim values" name="DDR_IOC_REG0"> + <field Type="RW" name="BANK_PCODE" offset="0" width="6">0x0</field> + <field Type="RW" name="BANK_NCODE" offset="6" width="6">0x0</field> + </register> + <register address="0x00000000" description="Manual trim values" name="SGMII_IOC_REG0"> + <field Type="RW" name="BANK_PCODE" offset="0" width="6">0x0</field> + <field Type="RW" name="BANK_NCODE" offset="6" width="6">0x0</field> + </register> + </registers> + </hsio> + </mss_io> + <mss_sgmii> + <tip> + <registers> + <register address="0x00000004" description="SGMII mode control (SEU)" name="SGMII_MODE"> + <field Type="RW" name="REG_PLL_EN" offset="0" width="1">0x1</field> + <field Type="RW" name="REG_DLL_EN" offset="1" width="1">0x1</field> + <field Type="RW" name="REG_PVT_EN" offset="2" width="1">0x1</field> + <field Type="RW" name="REG_BC_VRGEN_EN" offset="3" width="1">0x1</field> + <field Type="RW" name="REG_TX0_EN" offset="4" width="1">0x1</field> + <field Type="RW" name="REG_RX0_EN" offset="5" width="1">0x1</field> + <field Type="RW" name="REG_TX1_EN" offset="6" width="1">0x1</field> + <field Type="RW" name="REG_RX1_EN" offset="7" width="1">0x1</field> + <field Type="RW" name="REG_DLL_LOCK_FLT" offset="8" width="2">0x2</field> + <field Type="RW" name="REG_DLL_ADJ_CODE" offset="10" width="4">0x9</field> + <field Type="RW" name="REG_CH0_CDR_RESET_B" offset="14" width="1">0x1</field> + <field Type="RW" name="REG_CH1_CDR_RESET_B" offset="15" width="1">0x1</field> + <field Type="RW" name="REG_BC_VRGEN" offset="16" width="6">0x00</field> + <field Type="RW" name="REG_CDR_MOVE_STEP" offset="22" width="1">0x1</field> + <field Type="RW" name="REG_REFCLK_EN_RDIFF" offset="23" width="1">0x1</field> + <field Type="RW" name="REG_BC_VS" offset="24" width="4">0x8</field> + <field Type="RW" name="REG_REFCLK_EN_UDRIVE_P" offset="28" width="1">0x0</field> + <field Type="RW" name="REG_REFCLK_EN_INS_HYST_P" offset="29" width="1">0x0</field> + <field Type="RW" name="REG_REFCLK_EN_UDRIVE_N" offset="30" width="1">0x0</field> + <field Type="RW" name="REG_REFCLK_EN_INS_HYST_N" offset="31" width="1">0x0</field> + </register> + <register address="0x00000008" description="PLL control register (SEU)" name="PLL_CNTL"> + <field Type="RW" name="REG_PLL_POSTDIV" offset="0" width="7">0x1</field> + <field Type="RO" name="ARO_PLL0_LOCK" offset="7" width="1"> + </field> + <field Type="RW" name="REG_PLL_RFDIV" offset="8" width="6">0x1</field> + <field Type="RW" name="REG_PLL_REG_RFCLK_SEL" offset="14" width="1">0x0</field> + <field Type="RW" name="REG_PLL_LP_REQUIRES_LOCK" offset="15" width="1">0x0</field> + <field Type="RW" name="REG_PLL_INTIN" offset="16" width="12">0x14</field> + <field Type="RW" name="REG_PLL_BWI" offset="28" width="2">0x0</field> + <field Type="RW" name="REG_PLL_BWP" offset="30" width="2">0x2</field> + </register> + <register address="0x0000000C" description="Channel0 control register" name="CH0_CNTL"> + <field Type="RW" name="REG_TX0_WPU_P" offset="0" width="1">0x0</field> + <field Type="RW" name="REG_TX0_WPD_P" offset="1" width="1">0x0</field> + <field Type="RW" name="REG_TX0_SLEW_P" offset="2" width="2">0x0</field> + <field Type="RW" name="REG_TX0_DRV_P" offset="4" width="4">0x7</field> + <field Type="RW" name="REG_TX0_ODT_P" offset="8" width="4">0x7</field> + <field Type="RW" name="REG_TX0_ODT_STATIC_P" offset="12" width="3">0x7</field> + <field Type="RW" name="REG_RX0_TIM_LONG" offset="15" width="1">0x0</field> + <field Type="RW" name="REG_RX0_WPU_P" offset="16" width="1">0x0</field> + <field Type="RW" name="REG_RX0_WPD_P" offset="17" width="1">0x0</field> + <field Type="RW" name="REG_RX0_IBUFMD_P" offset="18" width="3">0x4</field> + <field Type="RW" name="REG_RX0_EYEWIDTH_P" offset="21" width="3">0x7</field> + <field Type="RW" name="REG_RX0_ODT_P" offset="24" width="4">0x7</field> + <field Type="RW" name="REG_RX0_ODT_STATIC_P" offset="28" width="3">0x3</field> + <field Type="RW" name="REG_RX0_EN_FLAG_N" offset="31" width="1">0x0</field> + </register> + <register address="0x00000010" description="Channel1 control register" name="CH1_CNTL"> + <field Type="RW" name="REG_TX1_WPU_P" offset="0" width="1">0x0</field> + <field Type="RW" name="REG_TX1_WPD_P" offset="1" width="1">0x0</field> + <field Type="RW" name="REG_TX1_SLEW_P" offset="2" width="2">0x0</field> + <field Type="RW" name="REG_TX1_DRV_P" offset="4" width="4">0x7</field> + <field Type="RW" name="REG_TX1_ODT_P" offset="8" width="4">0x7</field> + <field Type="RW" name="REG_TX1_ODT_STATIC_P" offset="12" width="3">0x7</field> + <field Type="RW" name="REG_RX1_TIM_LONG" offset="15" width="1">0x0</field> + <field Type="RW" name="REG_RX1_WPU_P" offset="16" width="1">0x0</field> + <field Type="RW" name="REG_RX1_WPD_P" offset="17" width="1">0x0</field> + <field Type="RW" name="REG_RX1_IBUFMD_P" offset="18" width="3">0x4</field> + <field Type="RW" name="REG_RX1_EYEWIDTH_P" offset="21" width="3">0x7</field> + <field Type="RW" name="REG_RX1_ODT_P" offset="24" width="4">0x7</field> + <field Type="RW" name="REG_RX1_ODT_STATIC_P" offset="28" width="3">0x3</field> + <field Type="RW" name="REG_RX1_EN_FLAG_N" offset="31" width="1">0x0</field> + </register> + <register address="0x00000014" description="Recalibration control register" name="RECAL_CNTL"> + <field Type="RW" name="REG_RECAL_DIFF_RANGE" offset="0" width="5">0x8</field> + <field Type="RW" name="REG_RECAL_START_EN" offset="5" width="1">0x0</field> + <field Type="RW" name="REG_PVT_CALIB_START" offset="6" width="1">0x1</field> + <field Type="RW" name="REG_PVT_CALIB_LOCK" offset="7" width="1">0x1</field> + <field Type="RW" name="REG_RECAL_UPD" offset="8" width="1">0x0</field> + <field Type="RW" name="BC_VRGEN_DIRECTION" offset="9" width="1">0x0</field> + <field Type="RW" name="BC_VRGEN_LOAD" offset="10" width="1">0x0</field> + <field Type="RW" name="BC_VRGEN_MOVE" offset="11" width="1">0x0</field> + <field Type="RW" name="REG_PVT_REG_CALIB_CLKDIV" offset="12" width="2">0x2</field> + <field Type="RW" name="REG_PVT_REG_CALIB_DIFFR_VSEL" offset="14" width="2">0x0</field> + <field Type="RO" name="SRO_DLL_90_CODE" offset="16" width="7"> + </field> + <field Type="RO" name="SRO_DLL_LOCK" offset="23" width="1"> + </field> + <field Type="RO" name="SRO_DLL_ST_CODE" offset="24" width="7"> + </field> + <field Type="RO" name="SRO_RECAL_START" offset="31" width="1"> + </field> + </register> + <register address="0x00000018" description="Clock input and routing control registers" name="CLK_CNTL"> + <field Type="RW" name="REG_REFCLK_EN_TERM_P" offset="0" width="2">0x0</field> + <field Type="RW" name="REG_REFCLK_EN_RXMODE_P" offset="2" width="2">0x3</field> + <field Type="RW" name="REG_REFCLK_EN_TERM_N" offset="4" width="2">0x0</field> + <field Type="RW" name="REG_REFCLK_EN_RXMODE_N" offset="6" width="2">0x3</field> + <field Type="RW" name="REG_REFCLK_CLKBUF_EN_PULLUP" offset="8" width="1">0x0</field> + <field Type="RW" name="REG_CLKMUX_FCLK_SEL" offset="9" width="3">0x0</field> + <field Type="RW" name="REG_CLKMUX_PLL0_RFCLK0_SEL" offset="12" width="2">0x1</field> + <field Type="RW" name="REG_CLKMUX_PLL0_RFCLK1_SEL" offset="14" width="2">0x1</field> + <field Type="RW" name="REG_CLKMUX_SPARE0" offset="16" width="16">0xf000</field> + </register> + <register address="0x0000001C" description="Dynamic control registers" name="DYN_CNTL"> + <field Type="RW" name="REG_PLL_DYNEN" offset="0" width="1">0x0</field> + <field Type="RW" name="REG_DLL_DYNEN" offset="1" width="1">0x0</field> + <field Type="RW" name="REG_PVT_DYNEN" offset="2" width="1">0x0</field> + <field Type="RW" name="REG_BC_DYNEN" offset="3" width="1">0x0</field> + <field Type="RW" name="REG_CLKMUX_DYNEN" offset="4" width="1">0x0</field> + <field Type="RW" name="REG_LANE0_DYNEN" offset="5" width="1">0x0</field> + <field Type="RW" name="REG_LANE1_DYNEN" offset="6" width="1">0x0</field> + <field Type="RO" name="BC_VRGEN_OOR" offset="7" width="1"> + </field> + <field Type="RW" name="REG_PLL_SOFT_RESET_PERIPH" offset="8" width="1">0x0</field> + <field Type="RW" name="REG_DLL_SOFT_RESET_PERIPH" offset="9" width="1">0x0</field> + <field Type="RW" name="REG_PVT_SOFT_RESET_PERIPH" offset="10" width="1">0x0</field> + <field Type="RW" name="REG_BC_SOFT_RESET_PERIPH" offset="11" width="1">0x0</field> + <field Type="RW" name="REG_CLKMUX_SOFT_RESET_PERIPH" offset="12" width="1">0x0</field> + <field Type="RW" name="REG_LANE0_SOFT_RESET_PERIPH" offset="13" width="1">0x0</field> + <field Type="RW" name="REG_LANE1_SOFT_RESET_PERIPH" offset="14" width="1">0x0</field> + <field Type="RO" name="PVT_CALIB_STATUS" offset="15" width="1"> + </field> + <field Type="RO" name="ARO_PLL0_VCO0PH_SEL" offset="16" width="3"> + </field> + <field Type="RO" name="ARO_PLL0_VCO1PH_SEL" offset="19" width="3"> + </field> + <field Type="RO" name="ARO_PLL0_VCO2PH_SEL" offset="22" width="3"> + </field> + <field Type="RO" name="ARO_PLL0_VCO3PH_SEL" offset="25" width="3"> + </field> + <field Type="RO" name="ARO_REF_DIFFR" offset="28" width="4"> + </field> + </register> + <register address="0x00000020" description="PVT calibrator status registers" name="PVT_STAT"> + <field Type="RO" name="ARO_REF_PCODE" offset="0" width="6"> + </field> + <field Type="RO" name="ARO_IOEN_BNK" offset="6" width="1"> + </field> + <field Type="RO" name="ARO_IOEN_BNK_B" offset="7" width="1"> + </field> + <field Type="RO" name="ARO_REF_NCODE" offset="8" width="6"> + </field> + <field Type="RO" name="ARO_CALIB_STATUS" offset="14" width="1"> + </field> + <field Type="RO" name="ARO_CALIB_STATUS_B" offset="15" width="1"> + </field> + <field Type="RO" name="ARO_PCODE" offset="16" width="6"> + </field> + <field Type="RO" name="ARO_CALIB_INTRPT" offset="22" width="1"> + </field> + <field Type="RO" name="PVT_CALIB_INTRPT" offset="23" width="1"> + </field> + <field Type="RO" name="ARO_NCODE" offset="24" width="6"> + </field> + <field Type="RW" name="PVT_CALIB_LOCK" offset="30" width="1">0x0</field> + <field Type="RW" name="PVT_CALIB_START" offset="31" width="1">0x0</field> + </register> + <register address="0x00000024" description="Spare control register" name="SPARE_CNTL"> + <field Type="RW" name="REG_SPARE" offset="0" width="32">0xFF000000</field> + </register> + <register address="0x00000028" description="Spare status register" name="SPARE_STAT"> + <field Type="RO" name="SRO_SPARE" offset="0" width="32"> + </field> + </register> + </registers> + </tip> + </mss_sgmii> + <mss_ddr> + <options> + <registers> + <register address="0" description="Tip config: Referenced receivers in the CA bus are turned on for CA training. These burn static power.(0x01 => turn off ; 0x00 => no action )" name="CA_BUS_RX_OFF_POST_TRAINING"> + <field Type="RW" name="CA_BUS_RX_OFF_POST_TRAINING" offset="0" width="1">0x1</field> + </register> + <register address="4" description="Tip config: 1 => 1 rank, 3 => 2 ranks" name="USER_INPUT_PHY_RANKS_TO_TRAIN"> + <field Type="RW" name="USER_INPUT_PHY_RANKS_TO_TRAIN" offset="0" width="2">0x1</field> + </register> + <register address="8" description="Tip config: Pick what trainings we want performed by the TIP, default is 0x1F" name="TRAINING_SKIP_SETTING"> + <field Type="RW" name="SKIP_BCLKSCLK_TIP_TRAINING" offset="0" width="1">0x0</field> + <field Type="RW" name="SKIP_ADDCMD_TIP_TRAINING" offset="1" width="1">0x1</field> + <field Type="RW" name="SKIP_WRLVL_TIP_TRAINING" offset="2" width="1">0x0</field> + <field Type="RW" name="SKIP_RDGATE_TIP_TRAINING" offset="3" width="1">0x0</field> + <field Type="RW" name="SKIP_DQ_DQS_OPT_TIP_TRAINING" offset="4" width="1">0x0</field> + </register> + <register address="C" description="Tip config: default: 0x2,0x4,0x0,0x1F,0x1F" name="TIP_CFG_PARAMS"> + <field Type="RW" name="ADDCMD_OFFSET" offset="0" width="3">0x2</field> + <field Type="RW" name="BCKLSCLK_OFFSET" offset="3" width="3">0x5</field> + <field Type="RW" name="WRCALIB_WRITE_COUNT" offset="6" width="7"> 0x0</field> + <field Type="RW" name="READ_GATE_MIN_READS" offset="13" width="8">0x7F</field> + <field Type="RW" name="ADDRCMD_WAIT_COUNT" offset="22" width="8"> 0x1F</field> + </register> + <register address="10" description="in simulation we need to set this to 2, for hardware it will be dependent on the trace lengths" name="TIP_CONFIG_PARAMS_BCLK_VCOPHS_OFFSET"> + <field Type="RW" name="TIP_CONFIG_PARAMS_BCLK_VCOPHS" offset="0" width="32">0x02</field> + </register> + </registers> + </options> + <io_bank> + <registers> + <register address="0x00000004" description="DPC Bits Register" name="DPC_BITS"> + <field Type="RW" name="DPC_VS" offset="0" width="4">0x2</field> + <field Type="RW" name="DPC_VRGEN_H" offset="4" width="6">0x2</field> + <field Type="RW" name="DPC_VRGEN_EN_H" offset="10" width="1">0x1</field> + <field Type="RW" name="DPC_MOVE_EN_H" offset="11" width="1">0x0</field> + <field Type="RW" name="DPC_VRGEN_V" offset="12" width="6">0xC</field> + <field Type="RW" name="DPC_VRGEN_EN_V" offset="18" width="1">0x1</field> + <field Type="RW" name="DPC_MOVE_EN_V" offset="19" width="1">0x0</field> + <field Type="RSVD" name="RESERVE01" offset="20" width="12">0x0</field> + </register> + <register address="0x00000008" description="Need to be set by software in all modes but OFF mode. Decoding options should follow ODT_STR table, depends on drive STR setting" name="RPC_ODT_DQ"> + <field Type="RW" name="RPC_ODT_DQ" offset="0" width="32">0x6</field> + </register> + <register address="0x00000012" description="Need to be set by software in all modes but OFF mode. Decoding options should follow ODT_STR table, depends on drive STR setting" name="RPC_ODT_DQS"> + <field Type="RW" name="RPC_ODT_DQS" offset="0" width="32">0x6</field> + </register> + <register address="0x00000016" description="Need to be set by software in all modes but OFF mode. Decoding options should follow ODT_STR table, depends on drive STR setting" name="RPC_ODT_ADDCMD"> + <field Type="RW" name="RPC_ODT_ADDCMD" offset="0" width="32">0x2</field> + </register> + <register address="0x00000020" description="Need to be set by software in all modes but OFF mode. Decoding options should follow ODT_STR table, depends on drive STR setting" name="RPC_ODT_CLK"> + <field Type="RW" name="RPC_ODT_CLK" offset="0" width="32">0x2</field> + </register> + <register address="0x00000024" description="0x2000 73A8 (rpc10_ODT)" name="RPC_ODT_STATIC_DQ"> + <field Type="RW" name="RPC_ODT_STATIC_DQ" offset="0" width="32">0x5</field> + </register> + <register address="0x00000028" description="0x2000 73AC (rpc11_ODT)" name="RPC_ODT_STATIC_DQS"> + <field Type="RW" name="RPC_ODT_STATIC_DQS" offset="0" width="32">0x5</field> + </register> + <register address="0x00000032" description="0x2000 739C (rpc7_ODT)" name="RPC_ODT_STATIC_ADDCMD"> + <field Type="RW" name="RPC_ODT_STATIC_ADDCMD" offset="0" width="32">0x7</field> + </register> + <register address="0x00000036" description="0x2000 73A4 (rpc9_ODT)" name="RPC_ODT_STATIC_CLKP"> + <field Type="RW" name="RPC_ODT_STATIC_CLKP" offset="0" width="32">0x7</field> + </register> + <register address="0x00000040" description="0x2000 73A0 (rpc8_ODT)" name="RPC_ODT_STATIC_CLKN"> + <field Type="RW" name="RPC_ODT_STATIC_CLKN" offset="0" width="32">0x7</field> + </register> + <register address="0x00000044" description="0x2000 757C (rpc95)" name="RPC_IBUFMD_ADDCMD"> + <field Type="RW" name="RPC_IBUFMD_ADDCMD" offset="0" width="32">0x3</field> + </register> + <register address="0x00000048" description="0x2000 7580 (rpc96)" name="RPC_IBUFMD_CLK"> + <field Type="RW" name="RPC_IBUFMD_CLK" offset="0" width="32">0x4</field> + </register> + <register address="0x00000052" description="0x2000 7584 (rpc97)" name="RPC_IBUFMD_DQ"> + <field Type="RW" name="RPC_IBUFMD_DQ" offset="0" width="32">0x3</field> + </register> + <register address="0x00000056" description="0x2000 7588 (rpc98)" name="RPC_IBUFMD_DQS"> + <field Type="RW" name="RPC_IBUFMD_DQS" offset="0" width="32">0x4</field> + </register> + <register address="0x00000060" description="bits 15:14 connect to pc_ibufmx DQ/DQS/DM bits 13:12 connect to pc_ibufmx CA/CK Check at ioa pc bit" name="RPC_SPARE0_DQ"> + <field Type="RW" name="RPC_SPARE0_DQ" offset="0" width="32">0x8000</field> + </register> + <register address="0x00000064" description="Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5." name="RPC_EN_ADDCMD0_OVRT9"> + <field Type="RW" name="MSS_DDR_CK0" offset="0" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_CK_N0" offset="1" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_A0" offset="2" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_A1" offset="3" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_A2" offset="4" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_A3" offset="5" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_A4" offset="6" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_A5" offset="7" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_A6" offset="8" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_A7" offset="9" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_A8" offset="10" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_A9" offset="11" width="1">0x1</field> + </register> + <register address="0x00000064" description="Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5." name="RPC_EN_ADDCMD1_OVRT10"> + <field Type="RW" name="MSS_DDR_CK1" offset="0" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_CK_N1" offset="1" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_A10" offset="2" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_A11" offset="3" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_A12" offset="4" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_A13" offset="5" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_A14" offset="6" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_A15" offset="7" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_A16" offset="8" width="1">0x1</field> + <field Type="RW" name="MSS_DDR3_WE_N" offset="9" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_BA0" offset="10" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_BA1" offset="11" width="1">0x1</field> + </register> + <register address="0x00000064" description="Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. " name="RPC_EN_ADDCMD2_OVRT11"> + <field Type="RW" name="MSS_DDR_RAM_RST_N" offset="0" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_BG0" offset="1" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_BG1" offset="2" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_CS0" offset="3" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_CKE0" offset="4" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_ODT0" offset="5" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_CS1" offset="6" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_CKE1" offset="7" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_ODT1" offset="8" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_ACT_N" offset="9" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_PARITY" offset="10" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_ALERT_N" offset="11" width="1">0x1</field> + </register> + <register address="0x00000064" description="Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5." name="RPC_EN_DATA0_OVRT12"> + <field Type="RW" name="MSS_DDR_DQ0" offset="0" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ1" offset="1" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ2" offset="2" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ3" offset="3" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQS_P0" offset="4" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQS_N0" offset="5" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ4" offset="6" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ5" offset="7" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ6" offset="8" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ7" offset="9" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DM0" offset="10" width="1">0x0</field> + </register> + <register address="0x00000064" description="Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5." name="RPC_EN_DATA1_OVRT13"> + <field Type="RW" name="MSS_DDR_DQ8" offset="0" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ9" offset="1" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ10" offset="2" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ11" offset="3" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQS_P1" offset="4" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQS_N1" offset="5" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ12" offset="6" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ13" offset="7" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ14" offset="8" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ15" offset="9" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DM1" offset="10" width="1">0x0</field> + </register> + <register address="0x00000064" description="Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5." name="RPC_EN_DATA2_OVRT14"> + <field Type="RW" name="MSS_DDR_DQ16" offset="0" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ17" offset="1" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ18" offset="2" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ19" offset="3" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQS_P2" offset="4" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQS_N2" offset="5" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ20" offset="6" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ21" offset="7" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ22" offset="8" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ23" offset="9" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DM2" offset="10" width="1">0x0</field> + </register> + <register address="0x00000064" description="Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5." name="RPC_EN_DATA3_OVRT15"> + <field Type="RW" name="MSS_DDR_DQ24" offset="0" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ25" offset="1" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ26" offset="2" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ27" offset="3" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQS_P3" offset="4" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQS_N3" offset="5" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ28" offset="6" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ29" offset="7" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ30" offset="8" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ31" offset="9" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DM3" offset="10" width="1">0x0</field> + </register> + <register address="0x00000064" description="Overrides the I/O, used to disable specific DDR I/0. Each bit corresponding to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5." name="RPC_EN_ECC_OVRT16"> + <field Type="RW" name="MSS_DDR_DQ32" offset="0" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQ33" offset="1" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQ34" offset="2" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQ35" offset="3" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQS_P4" offset="4" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQS_N4" offset="5" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DM4" offset="6" width="1">0x1</field> + </register> + <register address="0x00000064" description="Sets pull-downs when override enabled. Each bit corresponding to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5." name="RPC235_WPD_ADD_CMD0"> + <field Type="RW" name="MSS_DDR_CK0" offset="0" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_CK_N0" offset="1" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_A0" offset="2" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_A1" offset="3" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_A2" offset="4" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_A3" offset="5" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_A4" offset="6" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_A5" offset="7" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_A6" offset="8" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_A7" offset="9" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_A8" offset="10" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_A9" offset="11" width="1">0x0</field> + </register> + <register address="0x00000064" description="Sets pull-downs when override enabled. Each bit corresponding to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5." name="RPC236_WPD_ADD_CMD1"> + <field Type="RW" name="MSS_DDR_CK1" offset="0" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_CK_N1" offset="1" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_A10" offset="2" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_A11" offset="3" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_A12" offset="4" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_A13" offset="5" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_A14" offset="6" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_A15" offset="7" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_A16" offset="8" width="1">0x0</field> + <field Type="RW" name="MSS_DDR3_WE_N" offset="9" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_BA0" offset="10" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_BA1" offset="11" width="1">0x0</field> + </register> + <register address="0x00000064" description="Sets pull-downs when override enabled. Each bit corresponding to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5. Note: For LPDDR4 need to over-ride MSS_DDR_ODT0 and MSS_DDR_ODT1 and eanble PU i.e. (set OVR_EN ==1 , wpu == 0 , wpd == 1 )" name="RPC237_WPD_ADD_CMD2"> + <field Type="RW" name="MSS_DDR_RAM_RST_N" offset="0" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_BG0" offset="1" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_BG1" offset="2" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_CS0" offset="3" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_CKE0" offset="4" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_ODT0" offset="5" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_CS1" offset="6" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_CKE1" offset="7" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_ODT1" offset="8" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_ACT_N" offset="9" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_PARITY" offset="10" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_ALERT_N" offset="11" width="1">0x0</field> + </register> + <register address="0x00000064" description="Sets pull-downs when override enabled. Each bit corresponding to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5." name="RPC238_WPD_DATA0"> + <field Type="RW" name="MSS_DDR_DQ0" offset="0" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ1" offset="1" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ2" offset="2" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ3" offset="3" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQS_P0" offset="4" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQS_N0" offset="5" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ4" offset="6" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ5" offset="7" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ6" offset="8" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ7" offset="9" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DM0" offset="10" width="1">0x0</field> + </register> + <register address="0x00000064" description="Sets pull-downs when override enabled. Each bit corresponding to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5." name="RPC239_WPD_DATA1"> + <field Type="RW" name="MSS_DDR_DQ8" offset="0" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ9" offset="1" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ10" offset="2" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ11" offset="3" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQS_P1" offset="4" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQS_N1" offset="5" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ12" offset="6" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ13" offset="7" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ14" offset="8" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ15" offset="9" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DM1" offset="10" width="1">0x0</field> + </register> + <register address="0x00000064" description="Sets pull-downs when override enabled. Each bit corresponding to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5." name="RPC240_WPD_DATA2"> + <field Type="RW" name="MSS_DDR_DQ16" offset="0" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ17" offset="1" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ18" offset="2" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ19" offset="3" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQS_P2" offset="4" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQS_N2" offset="5" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ20" offset="6" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ21" offset="7" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ22" offset="8" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ23" offset="9" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DM2" offset="10" width="1">0x0</field> + </register> + <register address="0x00000064" description="Sets pull-downs when override enabled. Each bit corresponding to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5." name="RPC241_WPD_DATA3"> + <field Type="RW" name="MSS_DDR_DQ24" offset="0" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ25" offset="1" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ26" offset="2" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ27" offset="3" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQS_P3" offset="4" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQS_N3" offset="5" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ28" offset="6" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ29" offset="7" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ30" offset="8" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ31" offset="9" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DM3" offset="10" width="1">0x0</field> + </register> + <register address="0x00000064" description="Sets pull-downs when override enabled. Each bit corresponding to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5." name="RPC242_WPD_ECC"> + <field Type="RW" name="MSS_DDR_DQ32" offset="0" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ33" offset="1" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ34" offset="2" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQ35" offset="3" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQS_P4" offset="4" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DQS_N4" offset="5" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_DM4" offset="6" width="1">0x0</field> + </register> + <register address="0x00000064" description="Sets pull-ups when override enabled. Each bit corresponding to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5." name="RPC243_WPU_ADD_CMD0"> + <field Type="RW" name="MSS_DDR_CK0" offset="0" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_CK_N0" offset="1" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_A0" offset="2" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_A1" offset="3" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_A2" offset="4" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_A3" offset="5" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_A4" offset="6" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_A5" offset="7" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_A6" offset="8" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_A7" offset="9" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_A8" offset="10" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_A9" offset="11" width="1">0x1</field> + </register> + <register address="0x00000064" description="Sets pull-ups when override enabled. Each bit corresponding to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5." name="RPC244_WPU_ADD_CMD1"> + <field Type="RW" name="MSS_DDR_CK1" offset="0" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_CK_N1" offset="1" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_A10" offset="2" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_A11" offset="3" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_A12" offset="4" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_A13" offset="5" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_A14" offset="6" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_A15" offset="7" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_A16" offset="8" width="1">0x1</field> + <field Type="RW" name="MSS_DDR3_WE_N" offset="9" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_BA0" offset="10" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_BA1" offset="11" width="1">0x1</field> + </register> + <register address="0x00000064" description="Sets pull-ups when override enabled. Each bit corresponding to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5." name="RPC245_WPU_ADD_CMD2"> + <field Type="RW" name="MSS_DDR_RAM_RST_N" offset="0" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_BG0" offset="1" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_BG1" offset="2" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_CS0" offset="3" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_CKE0" offset="4" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_ODT0" offset="5" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_CS1" offset="6" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_CKE1" offset="7" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_ODT1" offset="8" width="1">0x0</field> + <field Type="RW" name="MSS_DDR_ACT_N" offset="9" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_PARITY" offset="10" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_ALERT_N" offset="11" width="1">0x1</field> + </register> + <register address="0x00000064" description="Sets pull-ups when override enabled. Each bit corresponding to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5." name="RPC246_WPU_DATA0"> + <field Type="RW" name="MSS_DDR_DQ0" offset="0" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQ1" offset="1" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQ2" offset="2" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQ3" offset="3" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQS_P0" offset="4" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQS_N0" offset="5" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQ4" offset="6" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQ5" offset="7" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQ6" offset="8" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQ7" offset="9" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DM0" offset="10" width="1">0x1</field> + </register> + <register address="0x00000064" description="Sets pull-ups when override enabled. Each bit corresponding to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5." name="RPC247_WPU_DATA1"> + <field Type="RW" name="MSS_DDR_DQ8" offset="0" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQ9" offset="1" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQ10" offset="2" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQ11" offset="3" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQS_P1" offset="4" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQS_N1" offset="5" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQ12" offset="6" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQ13" offset="7" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQ14" offset="8" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQ15" offset="9" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DM1" offset="10" width="1">0x1</field> + </register> + <register address="0x00000064" description="Sets pull-ups when override enabled. Each bit corresponding to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5." name="RPC248_WPU_DATA2"> + <field Type="RW" name="MSS_DDR_DQ16" offset="0" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQ17" offset="1" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQ18" offset="2" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQ19" offset="3" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQS_P2" offset="4" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQS_N2" offset="5" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQ20" offset="6" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQ21" offset="7" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQ22" offset="8" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQ23" offset="9" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DM2" offset="10" width="1">0x1</field> + </register> + <register address="0x00000064" description="Sets pull-ups when override enabled. Each bit corresponding to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5." name="RPC249_WPU_DATA3"> + <field Type="RW" name="MSS_DDR_DQ24" offset="0" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQ25" offset="1" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQ26" offset="2" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQ27" offset="3" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQS_P3" offset="4" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQS_N3" offset="5" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQ28" offset="6" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQ29" offset="7" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQ30" offset="8" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQ31" offset="9" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DM3" offset="10" width="1">0x1</field> + </register> + <register address="0x00000064" description="Sets pull-ups when override enabled. Each bit corresponding to an IO in corresponding IOG lane, starting from p_pair0 to n_pair5." name="RPC250_WPU_ECC"> + <field Type="RW" name="MSS_DDR_DQ32" offset="0" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQ33" offset="1" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQ34" offset="2" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQ35" offset="3" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQS_P4" offset="4" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DQS_N4" offset="5" width="1">0x1</field> + <field Type="RW" name="MSS_DDR_DM4" offset="6" width="1">0x1</field> + </register> + </registers> + </io_bank> + <mode> + <registers> + <register address="0x00000004" description="DDRPHY MODE (binary)- 000 ddr3, 001 ddr33L, 010 ddr4, 011 LPDDR3, 100 LPDDR4, 111 OFF_MODE" name="DDRPHY_MODE"> + <field Type="RW" name="DDRMODE" offset="0" width="3">0x4</field> + <field Type="RW" name="ECC" offset="3" width="1">0x0</field> + <field Type="RW" name="CRC" offset="4" width="1">0x0</field> + <field Type="RW" name="BUS_WIDTH" offset="5" width="3">0x1</field> + <field Type="RW" name="DMI_DBI" offset="8" width="1">0x1</field> + <field Type="RW" name="DQ_DRIVE" offset="9" width="2">0x1</field> + <field Type="RW" name="DQS_DRIVE" offset="11" width="2">0x1</field> + <field Type="RW" name="ADD_CMD_DRIVE" offset="13" width="2">0x2</field> + <field Type="RW" name="CLOCK_OUT_DRIVE" offset="15" width="2">0x2</field> + <field Type="RW" name="DQ_TERMINATION" offset="17" width="2">0x0</field> + <field Type="RW" name="DQS_TERMINATION" offset="19" width="2">0x0</field> + <field Type="RW" name="ADD_CMD_INPUT_PIN_TERMINATION" offset="21" width="2">0x0</field> + <field Type="RW" name="PRESET_ODT_CLK" offset="23" width="2">0x0</field> + <field Type="RW" name="POWER_DOWN" offset="25" width="1">0x0</field> + <field Type="RW" name="RANK" offset="26" width="1">0x0</field> + <field Type="RSVD" name="RESERVED" offset="27" width="5">0x0</field> + </register> + <register address="0x00000008" description="number of lanes used for data- does not include ECC, infer from mode register" name="DATA_LANES_USED"> + <field Type="RW" name="DATA_LANES" offset="0" width="3">0x4</field> + </register> + </registers> + </mode> + <off_mode> + <registers> + <register address="0x00000004" description="DDRPHY MODE Register, ddr off" name="DDRPHY_MODE_OFF"> + <field Type="RW" name="DDRMODE" offset="0" width="3">0x0</field> + <field Type="RW" name="ECC" offset="3" width="1">0x0</field> + <field Type="RW" name="CRC" offset="4" width="1">0x0</field> + <field Type="RW" name="BUS_WIDTH" offset="5" width="3">0x0</field> + <field Type="RW" name="DMI_DBI" offset="8" width="1">0x0</field> + <field Type="RW" name="DQ_DRIVE" offset="9" width="2">0x0</field> + <field Type="RW" name="DQS_DRIVE" offset="11" width="2">0x0</field> + <field Type="RW" name="ADD_CMD_DRIVE" offset="13" width="2">0x0</field> + <field Type="RW" name="CLOCK_OUT_DRIVE" offset="15" width="2">0x0</field> + <field Type="RW" name="DQ_TERMINATION" offset="17" width="2">0x0</field> + <field Type="RW" name="DQS_TERMINATION" offset="19" width="2">0x0</field> + <field Type="RW" name="ADD_CMD_INPUT_PIN_TERMINATION" offset="21" width="2">0x0</field> + <field Type="RW" name="PRESET_ODT_CLK" offset="23" width="2">0x0</field> + <field Type="RW" name="POWER_DOWN" offset="25" width="1">0x0</field> + <field Type="RW" name="RANK" offset="26" width="1">0x0</field> + <field Type="RSVD" name="RESERVED" offset="27" width="5">0x0</field> + </register> + <register address="0x00000004" description="DPC Bits Register off mode" name="DPC_BITS_OFF_MODE"> + <field Type="RW" name="DPC_VS" offset="0" width="4">0x0</field> + <field Type="RW" name="DPC_VRGEN_H" offset="4" width="6">0x0</field> + <field Type="RW" name="DPC_VRGEN_EN_H" offset="10" width="1">0x0</field> + <field Type="RW" name="DPC_MOVE_EN_H" offset="11" width="1">0x0</field> + <field Type="RW" name="DPC_VRGEN_V" offset="12" width="6">0x0</field> + <field Type="RW" name="DPC_VRGEN_EN_V" offset="18" width="1">0x0</field> + <field Type="RW" name="DPC_MOVE_EN_V" offset="19" width="1">0x0</field> + <field Type="RSVD" name="RESERVE01" offset="20" width="12">0x0</field> + </register> + </registers> + </off_mode> + <segs> + <registers> + <register address="0x00000000" description="Cached access at 0x00_8000_0000 (-0x80+0x00) " name="SEG0_0"> + <field Type="RW" name="ADDRESS_OFFSET" offset="0" width="15">0x7F80</field> + <field Type="RW" name="RESERVED" offset="15" width="16">0x0</field> + <field Type="RW" name="LOCKED" offset="31" width="1">0x1</field> + </register> + <register address="0x00000004" description="Cached access at 0x10_0000_000" name="SEG0_1"> + <field Type="RW" name="ADDRESS_OFFSET" offset="0" width="15">0x7030</field> + <field Type="RW" name="RESERVED" offset="15" width="16">0x0</field> + <field Type="RW" name="LOCKED" offset="31" width="1">0x1</field> + </register> + <register address="0x00000008" description="not used" name="SEG0_2"> + <field Type="RW" name="ADDRESS_OFFSET" offset="0" width="15">0x0</field> + <field Type="RW" name="RESERVED" offset="15" width="16">0x0</field> + <field Type="RW" name="LOCKED" offset="31" width="1">0x0</field> + </register> + <register address="0x00000012" description="not used" name="SEG0_3"> + <field Type="RW" name="ADDRESS_OFFSET" offset="0" width="15">0x0</field> + <field Type="RW" name="RESERVED" offset="15" width="16">0x0</field> + <field Type="RW" name="LOCKED" offset="31" width="1">0x0</field> + </register> + <register address="0x00000016" description="not used" name="SEG0_4"> + <field Type="RW" name="ADDRESS_OFFSET" offset="0" width="15">0x0</field> + <field Type="RW" name="RESERVED" offset="15" width="16">0x0</field> + <field Type="RW" name="LOCKED" offset="31" width="1">0x0</field> + </register> + <register address="0x00000020" description="not used" name="SEG0_5"> + <field Type="RW" name="ADDRESS_OFFSET" offset="0" width="15">0x0</field> + <field Type="RW" name="RESERVED" offset="15" width="6">0x0</field> + <field Type="RW" name="LOCKED" offset="31" width="1">0x0</field> + </register> + <register address="0x00000024" description="not used" name="SEG0_6"> + <field Type="RW" name="ADDRESS_OFFSET" offset="0" width="15">0x0</field> + <field Type="RW" name="RESERVED" offset="15" width="16">0x0</field> + <field Type="RW" name="LOCKED" offset="31" width="1">0x0</field> + </register> + <register address="0x00000028" description="not used" name="SEG0_7"> + <field Type="RW" name="ADDRESS_OFFSET" offset="0" width="15">0x0</field> + <field Type="RW" name="RESERVED" offset="15" width="16">0x0</field> + <field Type="RW" name="LOCKED" offset="31" width="1">0x0</field> + </register> + <register address="0x00000000" description="not used" name="SEG1_0"> + <field Type="RW" name="ADDRESS_OFFSET" offset="0" width="15">0x0</field> + <field Type="RW" name="RESERVED" offset="15" width="16">0x0</field> + <field Type="RW" name="LOCKED" offset="31" width="1">0x0</field> + </register> + <register address="0x00000004" description="not used" name="SEG1_1"> + <field Type="RW" name="ADDRESS_OFFSET" offset="0" width="15">0x0</field> + <field Type="RW" name="RESERVED" offset="15" width="16">0x0</field> + <field Type="RW" name="LOCKED" offset="31" width="1">0x0</field> + </register> + <register address="0x00000008" description="Non-Cached access at 0x00_c000_0000" name="SEG1_2"> + <field Type="RW" name="ADDRESS_OFFSET" offset="0" width="15">0x7FB0</field> + <field Type="RW" name="RESERVED" offset="15" width="16">0x0</field> + <field Type="RW" name="LOCKED" offset="31" width="1">0x1</field> + </register> + <register address="0x00000012" description="Non-Cached access at 0x14_0000_0000" name="SEG1_3"> + <field Type="RW" name="ADDRESS_OFFSET" offset="0" width="15">0x0</field> + <field Type="RW" name="RESERVED" offset="15" width="16">0x0</field> + <field Type="RW" name="LOCKED" offset="31" width="1">0x1</field> + </register> + <register address="0x00000016" description="Non-Cached WCB access at 0x00_d000_0000" name="SEG1_4"> + <field Type="RW" name="ADDRESS_OFFSET" offset="0" width="15">0x7FA0</field> + <field Type="RW" name="RESERVED" offset="15" width="16">0x0</field> + <field Type="RW" name="LOCKED" offset="31" width="1">0x1</field> + </register> + <register address="0x00000020" description="Non-Cached WCB 0x18_0000_0000" name="SEG1_5"> + <field Type="RW" name="ADDRESS_OFFSET" offset="0" width="15">0x0</field> + <field Type="RW" name="RESERVED" offset="15" width="6">0x0</field> + <field Type="RW" name="LOCKED" offset="31" width="1">0x1</field> + </register> + <register address="0x00000024" description="Trace - Trace not in use here so can be left as 0" name="SEG1_6"> + <field Type="RW" name="ADDRESS_OFFSET" offset="0" width="15">0x0</field> + <field Type="RW" name="RESERVED" offset="15" width="16">0x0</field> + <field Type="RW" name="LOCKED" offset="31" width="1">0x0</field> + </register> + <register address="0x00000028" description="not used" name="SEG1_7"> + <field Type="RW" name="ADDRESS_OFFSET" offset="0" width="15">0x0</field> + <field Type="RW" name="RESERVED" offset="15" width="16">0x0</field> + <field Type="RW" name="LOCKED" offset="31" width="1">0x0</field> + </register> + </registers> + </segs> + <ddrc> + <registers> + <register address="0x00002400" description="IP Blk = ADDR_MAP Access=RW " name="CFG_MANUAL_ADDRESS_MAP"> + <field Type="RW" name="CFG_MANUAL_ADDRESS_MAP" offset="0" width="32">0x0</field> + </register> + <register address="0x00002404" description="IP Blk = ADDR_MAP Access=RW " name="CFG_CHIPADDR_MAP"> + <field Type="RW" name="CFG_CHIPADDR_MAP" offset="0" width="32">0x00001D</field> + </register> + <register address="0x00002408" description="IP Blk = ADDR_MAP Access=RW " name="CFG_CIDADDR_MAP"> + <field Type="RW" name="CFG_CIDADDR_MAP" offset="0" width="32">0x00000000</field> + </register> + <register address="0x0000240C" description="IP Blk = ADDR_MAP Access=RW " name="CFG_MB_AUTOPCH_COL_BIT_POS_LOW"> + <field Type="RW" name="CFG_MB_AUTOPCH_COL_BIT_POS_LOW" offset="0" width="32">0x00000004</field> + </register> + <register address="0x00002410" description="IP Blk = ADDR_MAP Access=RW " name="CFG_MB_AUTOPCH_COL_BIT_POS_HIGH"> + <field Type="RW" name="CFG_MB_AUTOPCH_COL_BIT_POS_HIGH" offset="0" width="32">0x0000000A</field> + </register> + <register address="0x00002414" description="IP Blk = ADDR_MAP Access=RW " name="CFG_BANKADDR_MAP_0"> + <field Type="RW" name="CFG_BANKADDR_MAP_0" offset="0" width="32">0x00C2CA</field> + </register> + <register address="0x00002418" description="IP Blk = ADDR_MAP Access=RW " name="CFG_BANKADDR_MAP_1"> + <field Type="RW" name="CFG_BANKADDR_MAP_1" offset="0" width="32">0x0</field> + </register> + <register address="0x0000241C" description="IP Blk = ADDR_MAP Access=RW " name="CFG_ROWADDR_MAP_0"> + <field Type="RW" name="CFG_ROWADDR_MAP_0" offset="0" width="32">0x9140F38D</field> + </register> + <register address="0x00002420" description="IP Blk = ADDR_MAP Access=RW " name="CFG_ROWADDR_MAP_1"> + <field Type="RW" name="CFG_ROWADDR_MAP_1" offset="0" width="32">0x75955134</field> + </register> + <register address="0x00002424" description="IP Blk = ADDR_MAP Access=RW " name="CFG_ROWADDR_MAP_2"> + <field Type="RW" name="CFG_ROWADDR_MAP_2" offset="0" width="32">0x71B69961</field> + </register> + <register address="0x00002428" description="IP Blk = ADDR_MAP Access=RW " name="CFG_ROWADDR_MAP_3"> + <field Type="RW" name="CFG_ROWADDR_MAP_3" offset="0" width="32">0x000</field> + </register> + <register address="0x0000242C" description="IP Blk = ADDR_MAP Access=RW " name="CFG_COLADDR_MAP_0"> + <field Type="RW" name="CFG_COLADDR_MAP_0" offset="0" width="32">0x440C2040</field> + </register> + <register address="0x00002430" description="IP Blk = ADDR_MAP Access=RW " name="CFG_COLADDR_MAP_1"> + <field Type="RW" name="CFG_COLADDR_MAP_1" offset="0" width="32">0x02481C61</field> + </register> + <register address="0x00002434" description="IP Blk = ADDR_MAP Access=RW " name="CFG_COLADDR_MAP_2"> + <field Type="RW" name="CFG_COLADDR_MAP_2" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00002800" description="IP Blk = MC_BASE3 Access=RW " name="CFG_VRCG_ENABLE"> + <field Type="RW" name="CFG_VRCG_ENABLE" offset="0" width="32">0x00000140</field> + </register> + <register address="0x00002804" description="IP Blk = MC_BASE3 Access=RW " name="CFG_VRCG_DISABLE"> + <field Type="RW" name="CFG_VRCG_DISABLE" offset="0" width="32">0x000000A0</field> + </register> + <register address="0x00002808" description="IP Blk = MC_BASE3 Access=RW " name="CFG_WRITE_LATENCY_SET"> + <field Type="RW" name="CFG_WRITE_LATENCY_SET" offset="0" width="32">0x00000000</field> + </register> + <register address="0x0000280C" description="IP Blk = MC_BASE3 Access=RW " name="CFG_THERMAL_OFFSET"> + <field Type="RW" name="CFG_THERMAL_OFFSET" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00002810" description="IP Blk = MC_BASE3 Access=RW " name="CFG_SOC_ODT"> + <field Type="RW" name="CFG_SOC_ODT" offset="0" width="32">0x6</field> + </register> + <register address="0x00002814" description="IP Blk = MC_BASE3 Access=RW " name="CFG_ODTE_CK"> + <field Type="RW" name="CFG_ODTE_CK" offset="0" width="32">0x0</field> + </register> + <register address="0x00002818" description="IP Blk = MC_BASE3 Access=RW " name="CFG_ODTE_CS"> + <field Type="RW" name="CFG_ODTE_CS" offset="0" width="32">0x0</field> + </register> + <register address="0x0000281C" description="IP Blk = MC_BASE3 Access=RW " name="CFG_ODTD_CA"> + <field Type="RW" name="CFG_ODTD_CA" offset="0" width="32">0x0</field> + </register> + <register address="0x00002820" description="IP Blk = MC_BASE3 Access=RW " name="CFG_LPDDR4_FSP_OP"> + <field Type="RW" name="CFG_LPDDR4_FSP_OP" offset="0" width="32">0x1</field> + </register> + <register address="0x00002824" description="IP Blk = MC_BASE3 Access=RW " name="CFG_GENERATE_REFRESH_ON_SRX"> + <field Type="RW" name="CFG_GENERATE_REFRESH_ON_SRX" offset="0" width="32">0x00000001</field> + </register> + <register address="0x00002828" description="IP Blk = MC_BASE3 Access=RW " name="CFG_DBI_CL"> + <field Type="RW" name="CFG_DBI_CL" offset="0" width="32">0x00000016</field> + </register> + <register address="0x0000282C" description="IP Blk = MC_BASE3 Access=RW " name="CFG_NON_DBI_CL"> + <field Type="RW" name="CFG_NON_DBI_CL" offset="0" width="32">0x00000016</field> + </register> + <register address="0x00002830" description="IP Blk = MC_BASE3 Access=RW " name="INIT_FORCE_WRITE_DATA_0"> + <field Type="RW" name="INIT_FORCE_WRITE_DATA_0" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00003C00" description="IP Blk = MC_BASE1 Access=RW " name="CFG_WRITE_CRC"> + <field Type="RW" name="CFG_WRITE_CRC" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00003C04" description="IP Blk = MC_BASE1 Access=RW " name="CFG_MPR_READ_FORMAT"> + <field Type="RW" name="CFG_MPR_READ_FORMAT" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00003C08" description="IP Blk = MC_BASE1 Access=RW " name="CFG_WR_CMD_LAT_CRC_DM"> + <field Type="RW" name="CFG_WR_CMD_LAT_CRC_DM" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00003C0C" description="IP Blk = MC_BASE1 Access=RW " name="CFG_FINE_GRAN_REF_MODE"> + <field Type="RW" name="CFG_FINE_GRAN_REF_MODE" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00003C10" description="IP Blk = MC_BASE1 Access=RW " name="CFG_TEMP_SENSOR_READOUT"> + <field Type="RW" name="CFG_TEMP_SENSOR_READOUT" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00003C14" description="IP Blk = MC_BASE1 Access=RW " name="CFG_PER_DRAM_ADDR_EN"> + <field Type="RW" name="CFG_PER_DRAM_ADDR_EN" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00003C18" description="IP Blk = MC_BASE1 Access=RW " name="CFG_GEARDOWN_MODE"> + <field Type="RW" name="CFG_GEARDOWN_MODE" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00003C1C" description="IP Blk = MC_BASE1 Access=RW " name="CFG_WR_PREAMBLE"> + <field Type="RW" name="CFG_WR_PREAMBLE" offset="0" width="32">0x1</field> + </register> + <register address="0x00003C20" description="IP Blk = MC_BASE1 Access=RW " name="CFG_RD_PREAMBLE"> + <field Type="RW" name="CFG_RD_PREAMBLE" offset="0" width="32">0x0</field> + </register> + <register address="0x00003C24" description="IP Blk = MC_BASE1 Access=RW " name="CFG_RD_PREAMB_TRN_MODE"> + <field Type="RW" name="CFG_RD_PREAMB_TRN_MODE" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00003C28" description="IP Blk = MC_BASE1 Access=RW " name="CFG_SR_ABORT"> + <field Type="RW" name="CFG_SR_ABORT" offset="0" width="32">0x0</field> + </register> + <register address="0x00003C2C" description="IP Blk = MC_BASE1 Access=RW " name="CFG_CS_TO_CMDADDR_LATENCY"> + <field Type="RW" name="CFG_CS_TO_CMDADDR_LATENCY" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00003C30" description="IP Blk = MC_BASE1 Access=RW " name="CFG_INT_VREF_MON"> + <field Type="RW" name="CFG_INT_VREF_MON" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00003C34" description="IP Blk = MC_BASE1 Access=RW " name="CFG_TEMP_CTRL_REF_MODE"> + <field Type="RW" name="CFG_TEMP_CTRL_REF_MODE" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00003C38" description="IP Blk = MC_BASE1 Access=RW " name="CFG_TEMP_CTRL_REF_RANGE"> + <field Type="RW" name="CFG_TEMP_CTRL_REF_RANGE" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00003C3C" description="IP Blk = MC_BASE1 Access=RW " name="CFG_MAX_PWR_DOWN_MODE"> + <field Type="RW" name="CFG_MAX_PWR_DOWN_MODE" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00003C40" description="IP Blk = MC_BASE1 Access=RW " name="CFG_READ_DBI"> + <field Type="RW" name="CFG_READ_DBI" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00003C44" description="IP Blk = MC_BASE1 Access=RW " name="CFG_WRITE_DBI"> + <field Type="RW" name="CFG_WRITE_DBI" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00003C48" description="IP Blk = MC_BASE1 Access=RW " name="CFG_DATA_MASK"> + <field Type="RW" name="CFG_DATA_MASK" offset="0" width="32">0x1</field> + </register> + <register address="0x00003C4C" description="IP Blk = MC_BASE1 Access=RW " name="CFG_CA_PARITY_PERSIST_ERR"> + <field Type="RW" name="CFG_CA_PARITY_PERSIST_ERR" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00003C50" description="IP Blk = MC_BASE1 Access=RW " name="CFG_RTT_PARK"> + <field Type="RW" name="CFG_RTT_PARK" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00003C54" description="IP Blk = MC_BASE1 Access=RW " name="CFG_ODT_INBUF_4_PD"> + <field Type="RW" name="CFG_ODT_INBUF_4_PD" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00003C58" description="IP Blk = MC_BASE1 Access=RW " name="CFG_CA_PARITY_ERR_STATUS"> + <field Type="RW" name="CFG_CA_PARITY_ERR_STATUS" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00003C5C" description="IP Blk = MC_BASE1 Access=RW " name="CFG_CRC_ERROR_CLEAR"> + <field Type="RW" name="CFG_CRC_ERROR_CLEAR" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00003C60" description="IP Blk = MC_BASE1 Access=RW " name="CFG_CA_PARITY_LATENCY"> + <field Type="RW" name="CFG_CA_PARITY_LATENCY" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00003C64" description="IP Blk = MC_BASE1 Access=RW " name="CFG_CCD_S"> + <field Type="RW" name="CFG_CCD_S" offset="0" width="32">0x00000005</field> + </register> + <register address="0x00003C68" description="IP Blk = MC_BASE1 Access=RW " name="CFG_CCD_L"> + <field Type="RW" name="CFG_CCD_L" offset="0" width="32">0x00000006</field> + </register> + <register address="0x00003C6C" description="IP Blk = MC_BASE1 Access=RW " name="CFG_VREFDQ_TRN_ENABLE"> + <field Type="RW" name="CFG_VREFDQ_TRN_ENABLE" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00003C70" description="IP Blk = MC_BASE1 Access=RW " name="CFG_VREFDQ_TRN_RANGE"> + <field Type="RW" name="CFG_VREFDQ_TRN_RANGE" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00003C74" description="IP Blk = MC_BASE1 Access=RW " name="CFG_VREFDQ_TRN_VALUE"> + <field Type="RW" name="CFG_VREFDQ_TRN_VALUE" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00003C78" description="IP Blk = MC_BASE1 Access=RW " name="CFG_RRD_S"> + <field Type="RW" name="CFG_RRD_S" offset="0" width="32">0x00000004</field> + </register> + <register address="0x00003C7C" description="IP Blk = MC_BASE1 Access=RW " name="CFG_RRD_L"> + <field Type="RW" name="CFG_RRD_L" offset="0" width="32">0x00000003</field> + </register> + <register address="0x00003C80" description="IP Blk = MC_BASE1 Access=RW " name="CFG_WTR_S"> + <field Type="RW" name="CFG_WTR_S" offset="0" width="32">0x00000003</field> + </register> + <register address="0x00003C84" description="IP Blk = MC_BASE1 Access=RW " name="CFG_WTR_L"> + <field Type="RW" name="CFG_WTR_L" offset="0" width="32">0x00000003</field> + </register> + <register address="0x00003C88" description="IP Blk = MC_BASE1 Access=RW " name="CFG_WTR_S_CRC_DM"> + <field Type="RW" name="CFG_WTR_S_CRC_DM" offset="0" width="32">0x00000003</field> + </register> + <register address="0x00003C8C" description="IP Blk = MC_BASE1 Access=RW " name="CFG_WTR_L_CRC_DM"> + <field Type="RW" name="CFG_WTR_L_CRC_DM" offset="0" width="32">0x00000003</field> + </register> + <register address="0x00003C90" description="IP Blk = MC_BASE1 Access=RW " name="CFG_WR_CRC_DM"> + <field Type="RW" name="CFG_WR_CRC_DM" offset="0" width="32">0x00000006</field> + </register> + <register address="0x00003C94" description="IP Blk = MC_BASE1 Access=RW " name="CFG_RFC1"> + <field Type="RW" name="CFG_RFC1" offset="0" width="32">0x00000036</field> + </register> + <register address="0x00003C98" description="IP Blk = MC_BASE1 Access=RW " name="CFG_RFC2"> + <field Type="RW" name="CFG_RFC2" offset="0" width="32">0x00000036</field> + </register> + <register address="0x00003C9C" description="IP Blk = MC_BASE1 Access=RW " name="CFG_RFC4"> + <field Type="RW" name="CFG_RFC4" offset="0" width="32">0x00000036</field> + </register> + <register address="0x00003CC4" description="IP Blk = MC_BASE1 Access=RW " name="CFG_NIBBLE_DEVICES"> + <field Type="RW" name="CFG_NIBBLE_DEVICES" offset="0" width="32">0x0</field> + </register> + <register address="0x00003CE0" description="IP Blk = MC_BASE1 Access=RW " name="CFG_BIT_MAP_INDEX_CS0_0"> + <field Type="RW" name="CFG_BIT_MAP_INDEX_CS0_0" offset="0" width="32">0x81881881</field> + </register> + <register address="0x00003CE4" description="IP Blk = MC_BASE1 Access=RW " name="CFG_BIT_MAP_INDEX_CS0_1"> + <field Type="RW" name="CFG_BIT_MAP_INDEX_CS0_1" offset="0" width="32">0x00008818</field> + </register> + <register address="0x00003CE8" description="IP Blk = MC_BASE1 Access=RW " name="CFG_BIT_MAP_INDEX_CS1_0"> + <field Type="RW" name="CFG_BIT_MAP_INDEX_CS1_0" offset="0" width="32">0xa92a92a9</field> + </register> + <register address="0x00003CEC" description="IP Blk = MC_BASE1 Access=RW " name="CFG_BIT_MAP_INDEX_CS1_1"> + <field Type="RW" name="CFG_BIT_MAP_INDEX_CS1_1" offset="0" width="32">0x00002a92</field> + </register> + <register address="0x00003CF0" description="IP Blk = MC_BASE1 Access=RW " name="CFG_BIT_MAP_INDEX_CS2_0"> + <field Type="RW" name="CFG_BIT_MAP_INDEX_CS2_0" offset="0" width="32">0xc28c28c2</field> + </register> + <register address="0x00003CF4" description="IP Blk = MC_BASE1 Access=RW " name="CFG_BIT_MAP_INDEX_CS2_1"> + <field Type="RW" name="CFG_BIT_MAP_INDEX_CS2_1" offset="0" width="32">0x00008c28</field> + </register> + <register address="0x00003CF8" description="IP Blk = MC_BASE1 Access=RW " name="CFG_BIT_MAP_INDEX_CS3_0"> + <field Type="RW" name="CFG_BIT_MAP_INDEX_CS3_0" offset="0" width="32">0xea2ea2ea</field> + </register> + <register address="0x00003CFC" description="IP Blk = MC_BASE1 Access=RW " name="CFG_BIT_MAP_INDEX_CS3_1"> + <field Type="RW" name="CFG_BIT_MAP_INDEX_CS3_1" offset="0" width="32">0x00002ea2</field> + </register> + <register address="0x00003D00" description="IP Blk = MC_BASE1 Access=RW " name="CFG_BIT_MAP_INDEX_CS4_0"> + <field Type="RW" name="CFG_BIT_MAP_INDEX_CS4_0" offset="0" width="32">0x03903903</field> + </register> + <register address="0x00003D04" description="IP Blk = MC_BASE1 Access=RW " name="CFG_BIT_MAP_INDEX_CS4_1"> + <field Type="RW" name="CFG_BIT_MAP_INDEX_CS4_1" offset="0" width="32">0x00009039</field> + </register> + <register address="0x00003D08" description="IP Blk = MC_BASE1 Access=RW " name="CFG_BIT_MAP_INDEX_CS5_0"> + <field Type="RW" name="CFG_BIT_MAP_INDEX_CS5_0" offset="0" width="32">0x2b32b32b</field> + </register> + <register address="0x00003D0C" description="IP Blk = MC_BASE1 Access=RW " name="CFG_BIT_MAP_INDEX_CS5_1"> + <field Type="RW" name="CFG_BIT_MAP_INDEX_CS5_1" offset="0" width="32">0x000032b3</field> + </register> + <register address="0x00003D10" description="IP Blk = MC_BASE1 Access=RW " name="CFG_BIT_MAP_INDEX_CS6_0"> + <field Type="RW" name="CFG_BIT_MAP_INDEX_CS6_0" offset="0" width="32">0x44944944</field> + </register> + <register address="0x00003D14" description="IP Blk = MC_BASE1 Access=RW " name="CFG_BIT_MAP_INDEX_CS6_1"> + <field Type="RW" name="CFG_BIT_MAP_INDEX_CS6_1" offset="0" width="32">0x00009449</field> + </register> + <register address="0x00003D18" description="IP Blk = MC_BASE1 Access=RW " name="CFG_BIT_MAP_INDEX_CS7_0"> + <field Type="RW" name="CFG_BIT_MAP_INDEX_CS7_0" offset="0" width="32">0x6c36c36c</field> + </register> + <register address="0x00003D1C" description="IP Blk = MC_BASE1 Access=RW " name="CFG_BIT_MAP_INDEX_CS7_1"> + <field Type="RW" name="CFG_BIT_MAP_INDEX_CS7_1" offset="0" width="32">0x000036c3</field> + </register> + <register address="0x00003D20" description="IP Blk = MC_BASE1 Access=RW " name="CFG_BIT_MAP_INDEX_CS8_0"> + <field Type="RW" name="CFG_BIT_MAP_INDEX_CS8_0" offset="0" width="32">0x85985985</field> + </register> + <register address="0x00003D24" description="IP Blk = MC_BASE1 Access=RW " name="CFG_BIT_MAP_INDEX_CS8_1"> + <field Type="RW" name="CFG_BIT_MAP_INDEX_CS8_1" offset="0" width="32">0x00009859</field> + </register> + <register address="0x00003D28" description="IP Blk = MC_BASE1 Access=RW " name="CFG_BIT_MAP_INDEX_CS9_0"> + <field Type="RW" name="CFG_BIT_MAP_INDEX_CS9_0" offset="0" width="32">0xad3ad3ad</field> + </register> + <register address="0x00003D2C" description="IP Blk = MC_BASE1 Access=RW " name="CFG_BIT_MAP_INDEX_CS9_1"> + <field Type="RW" name="CFG_BIT_MAP_INDEX_CS9_1" offset="0" width="32">0x00003ad3</field> + </register> + <register address="0x00003D30" description="IP Blk = MC_BASE1 Access=RW " name="CFG_BIT_MAP_INDEX_CS10_0"> + <field Type="RW" name="CFG_BIT_MAP_INDEX_CS10_0" offset="0" width="32">0xc69c69c6</field> + </register> + <register address="0x00003D34" description="IP Blk = MC_BASE1 Access=RW " name="CFG_BIT_MAP_INDEX_CS10_1"> + <field Type="RW" name="CFG_BIT_MAP_INDEX_CS10_1" offset="0" width="32">0x00009c69</field> + </register> + <register address="0x00003D38" description="IP Blk = MC_BASE1 Access=RW " name="CFG_BIT_MAP_INDEX_CS11_0"> + <field Type="RW" name="CFG_BIT_MAP_INDEX_CS11_0" offset="0" width="32">0xee3ee3ee</field> + </register> + <register address="0x00003D3C" description="IP Blk = MC_BASE1 Access=RW " name="CFG_BIT_MAP_INDEX_CS11_1"> + <field Type="RW" name="CFG_BIT_MAP_INDEX_CS11_1" offset="0" width="32">0x00003ee3</field> + </register> + <register address="0x00003D40" description="IP Blk = MC_BASE1 Access=RW " name="CFG_BIT_MAP_INDEX_CS12_0"> + <field Type="RW" name="CFG_BIT_MAP_INDEX_CS12_0" offset="0" width="32">0x07a07a07</field> + </register> + <register address="0x00003D44" description="IP Blk = MC_BASE1 Access=RW " name="CFG_BIT_MAP_INDEX_CS12_1"> + <field Type="RW" name="CFG_BIT_MAP_INDEX_CS12_1" offset="0" width="32">0x0000a07a</field> + </register> + <register address="0x00003D48" description="IP Blk = MC_BASE1 Access=RW " name="CFG_BIT_MAP_INDEX_CS13_0"> + <field Type="RW" name="CFG_BIT_MAP_INDEX_CS13_0" offset="0" width="32">0x2f42f42f</field> + </register> + <register address="0x00003D4C" description="IP Blk = MC_BASE1 Access=RW " name="CFG_BIT_MAP_INDEX_CS13_1"> + <field Type="RW" name="CFG_BIT_MAP_INDEX_CS13_1" offset="0" width="32">0x000042f4</field> + </register> + <register address="0x00003D50" description="IP Blk = MC_BASE1 Access=RW " name="CFG_BIT_MAP_INDEX_CS14_0"> + <field Type="RW" name="CFG_BIT_MAP_INDEX_CS14_0" offset="0" width="32">0x48a48a48</field> + </register> + <register address="0x00003D54" description="IP Blk = MC_BASE1 Access=RW " name="CFG_BIT_MAP_INDEX_CS14_1"> + <field Type="RW" name="CFG_BIT_MAP_INDEX_CS14_1" offset="0" width="32">0x0000a48a</field> + </register> + <register address="0x00003D58" description="IP Blk = MC_BASE1 Access=RW " name="CFG_BIT_MAP_INDEX_CS15_0"> + <field Type="RW" name="CFG_BIT_MAP_INDEX_CS15_0" offset="0" width="32">0x70470470</field> + </register> + <register address="0x00003D5C" description="IP Blk = MC_BASE1 Access=RW " name="CFG_BIT_MAP_INDEX_CS15_1"> + <field Type="RW" name="CFG_BIT_MAP_INDEX_CS15_1" offset="0" width="32">0x00004704</field> + </register> + <register address="0x00003D60" description="IP Blk = MC_BASE1 Access=RW " name="CFG_NUM_LOGICAL_RANKS_PER_3DS"> + <field Type="RW" name="CFG_NUM_LOGICAL_RANKS_PER_3DS" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00003D64" description="IP Blk = MC_BASE1 Access=RW " name="CFG_RFC_DLR1"> + <field Type="RW" name="CFG_RFC_DLR1" offset="0" width="32">0x00000048</field> + </register> + <register address="0x00003D68" description="IP Blk = MC_BASE1 Access=RW " name="CFG_RFC_DLR2"> + <field Type="RW" name="CFG_RFC_DLR2" offset="0" width="32">0x0000002C</field> + </register> + <register address="0x00003D6C" description="IP Blk = MC_BASE1 Access=RW " name="CFG_RFC_DLR4"> + <field Type="RW" name="CFG_RFC_DLR4" offset="0" width="32">0x00000020</field> + </register> + <register address="0x00003D70" description="IP Blk = MC_BASE1 Access=RW " name="CFG_RRD_DLR"> + <field Type="RW" name="CFG_RRD_DLR" offset="0" width="32">0x00000004</field> + </register> + <register address="0x00003D74" description="IP Blk = MC_BASE1 Access=RW " name="CFG_FAW_DLR"> + <field Type="RW" name="CFG_FAW_DLR" offset="0" width="32">0x00000010</field> + </register> + <register address="0x00003D98" description="IP Blk = MC_BASE1 Access=RW " name="CFG_ADVANCE_ACTIVATE_READY"> + <field Type="RW" name="CFG_ADVANCE_ACTIVATE_READY" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00004000" description="IP Blk = MC_BASE2 Access=RW " name="CTRLR_SOFT_RESET_N"> + <field Type="RW" name="CTRLR_SOFT_RESET_N" offset="0" width="32">0x1</field> + </register> + <register address="0x00004008" description="IP Blk = MC_BASE2 Access=RW " name="CFG_LOOKAHEAD_PCH"> + <field Type="RW" name="CFG_LOOKAHEAD_PCH" offset="0" width="32">0x0</field> + </register> + <register address="0x0000400C" description="IP Blk = MC_BASE2 Access=RW " name="CFG_LOOKAHEAD_ACT"> + <field Type="RW" name="CFG_LOOKAHEAD_ACT" offset="0" width="32">0x0</field> + </register> + <register address="0x00004010" description="IP Blk = MC_BASE2 Access=RW " name="INIT_AUTOINIT_DISABLE"> + <field Type="RW" name="INIT_AUTOINIT_DISABLE" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00004014" description="IP Blk = MC_BASE2 Access=RW " name="INIT_FORCE_RESET"> + <field Type="RW" name="INIT_FORCE_RESET" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00004018" description="IP Blk = MC_BASE2 Access=RW " name="INIT_GEARDOWN_EN"> + <field Type="RW" name="INIT_GEARDOWN_EN" offset="0" width="32">0x00000000</field> + </register> + <register address="0x0000401C" description="IP Blk = MC_BASE2 Access=RW " name="INIT_DISABLE_CKE"> + <field Type="RW" name="INIT_DISABLE_CKE" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00004020" description="IP Blk = MC_BASE2 Access=RW " name="INIT_CS"> + <field Type="RW" name="INIT_CS" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00004024" description="IP Blk = MC_BASE2 Access=RW " name="INIT_PRECHARGE_ALL"> + <field Type="RW" name="INIT_PRECHARGE_ALL" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00004028" description="IP Blk = MC_BASE2 Access=RW " name="INIT_REFRESH"> + <field Type="RW" name="INIT_REFRESH" offset="0" width="32">0x00000000</field> + </register> + <register address="0x0000402C" description="IP Blk = MC_BASE2 Access=RW " name="INIT_ZQ_CAL_REQ"> + <field Type="RW" name="INIT_ZQ_CAL_REQ" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00004034" description="IP Blk = MC_BASE2 Access=RW " name="CFG_BL"> + <field Type="RW" name="CFG_BL" offset="0" width="32">0x0</field> + </register> + <register address="0x00004038" description="IP Blk = MC_BASE2 Access=RW " name="CTRLR_INIT"> + <field Type="RW" name="CTRLR_INIT" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00004040" description="IP Blk = MC_BASE2 Access=RW " name="CFG_AUTO_REF_EN"> + <field Type="RW" name="CFG_AUTO_REF_EN" offset="0" width="32">0x1</field> + </register> + <register address="0x00004044" description="IP Blk = MC_BASE2 Access=RW " name="CFG_RAS"> + <field Type="RW" name="CFG_RAS" offset="0" width="32">0x22</field> + </register> + <register address="0x00004048" description="IP Blk = MC_BASE2 Access=RW " name="CFG_RCD"> + <field Type="RW" name="CFG_RCD" offset="0" width="32">0xF</field> + </register> + <register address="0x0000404C" description="IP Blk = MC_BASE2 Access=RW " name="CFG_RRD"> + <field Type="RW" name="CFG_RRD" offset="0" width="32">0x8</field> + </register> + <register address="0x00004050" description="IP Blk = MC_BASE2 Access=RW " name="CFG_RP"> + <field Type="RW" name="CFG_RP" offset="0" width="32">0x11</field> + </register> + <register address="0x00004054" description="IP Blk = MC_BASE2 Access=RW " name="CFG_RC"> + <field Type="RW" name="CFG_RC" offset="0" width="32">0x33</field> + </register> + <register address="0x00004058" description="IP Blk = MC_BASE2 Access=RW " name="CFG_FAW"> + <field Type="RW" name="CFG_FAW" offset="0" width="32">0x20</field> + </register> + <register address="0x0000405C" description="IP Blk = MC_BASE2 Access=RW " name="CFG_RFC"> + <field Type="RW" name="CFG_RFC" offset="0" width="32">0x130</field> + </register> + <register address="0x00004060" description="IP Blk = MC_BASE2 Access=RW " name="CFG_RTP"> + <field Type="RW" name="CFG_RTP" offset="0" width="32">0x8</field> + </register> + <register address="0x00004064" description="IP Blk = MC_BASE2 Access=RW " name="CFG_WR"> + <field Type="RW" name="CFG_WR" offset="0" width="32">0x10</field> + </register> + <register address="0x00004068" description="IP Blk = MC_BASE2 Access=RW " name="CFG_WTR"> + <field Type="RW" name="CFG_WTR" offset="0" width="32">0x8</field> + </register> + <register address="0x00004070" description="IP Blk = MC_BASE2 Access=RW " name="CFG_PASR"> + <field Type="RW" name="CFG_PASR" offset="0" width="32">0x0</field> + </register> + <register address="0x00004074" description="IP Blk = MC_BASE2 Access=RW " name="CFG_XP"> + <field Type="RW" name="CFG_XP" offset="0" width="32">0x6</field> + </register> + <register address="0x00004078" description="IP Blk = MC_BASE2 Access=RW " name="CFG_XSR"> + <field Type="RW" name="CFG_XSR" offset="0" width="32">0x1F</field> + </register> + <register address="0x00004080" description="IP Blk = MC_BASE2 Access=RW " name="CFG_CL"> + <field Type="RW" name="CFG_CL" offset="0" width="32">0x5</field> + </register> + <register address="0x00004088" description="IP Blk = MC_BASE2 Access=RW " name="CFG_READ_TO_WRITE"> + <field Type="RW" name="CFG_READ_TO_WRITE" offset="0" width="32">0xF</field> + </register> + <register address="0x0000408C" description="IP Blk = MC_BASE2 Access=RW " name="CFG_WRITE_TO_WRITE"> + <field Type="RW" name="CFG_WRITE_TO_WRITE" offset="0" width="32">0xF</field> + </register> + <register address="0x00004090" description="IP Blk = MC_BASE2 Access=RW " name="CFG_READ_TO_READ"> + <field Type="RW" name="CFG_READ_TO_READ" offset="0" width="32">0xF</field> + </register> + <register address="0x00004094" description="IP Blk = MC_BASE2 Access=RW " name="CFG_WRITE_TO_READ"> + <field Type="RW" name="CFG_WRITE_TO_READ" offset="0" width="32">0x1F</field> + </register> + <register address="0x00004098" description="IP Blk = MC_BASE2 Access=RW " name="CFG_READ_TO_WRITE_ODT"> + <field Type="RW" name="CFG_READ_TO_WRITE_ODT" offset="0" width="32">0x1</field> + </register> + <register address="0x0000409C" description="IP Blk = MC_BASE2 Access=RW " name="CFG_WRITE_TO_WRITE_ODT"> + <field Type="RW" name="CFG_WRITE_TO_WRITE_ODT" offset="0" width="32">0x0</field> + </register> + <register address="0x000040A0" description="IP Blk = MC_BASE2 Access=RW " name="CFG_READ_TO_READ_ODT"> + <field Type="RW" name="CFG_READ_TO_READ_ODT" offset="0" width="32">0x1</field> + </register> + <register address="0x000040A4" description="IP Blk = MC_BASE2 Access=RW " name="CFG_WRITE_TO_READ_ODT"> + <field Type="RW" name="CFG_WRITE_TO_READ_ODT" offset="0" width="32">0x1</field> + </register> + <register address="0x000040A8" description="IP Blk = MC_BASE2 Access=RW " name="CFG_MIN_READ_IDLE"> + <field Type="RW" name="CFG_MIN_READ_IDLE" offset="0" width="32">0x7</field> + </register> + <register address="0x000040AC" description="IP Blk = MC_BASE2 Access=RW " name="CFG_MRD"> + <field Type="RW" name="CFG_MRD" offset="0" width="32">0xC</field> + </register> + <register address="0x000040B0" description="IP Blk = MC_BASE2 Access=RW " name="CFG_BT"> + <field Type="RW" name="CFG_BT" offset="0" width="32">0x0</field> + </register> + <register address="0x000040B4" description="IP Blk = MC_BASE2 Access=RW " name="CFG_DS"> + <field Type="RW" name="CFG_DS" offset="0" width="32">0x6</field> + </register> + <register address="0x000040B8" description="IP Blk = MC_BASE2 Access=RW " name="CFG_QOFF"> + <field Type="RW" name="CFG_QOFF" offset="0" width="32">0x0</field> + </register> + <register address="0x000040C4" description="IP Blk = MC_BASE2 Access=RW " name="CFG_RTT"> + <field Type="RW" name="CFG_RTT" offset="0" width="32">0x2</field> + </register> + <register address="0x000040C8" description="IP Blk = MC_BASE2 Access=RW " name="CFG_DLL_DISABLE"> + <field Type="RW" name="CFG_DLL_DISABLE" offset="0" width="32">0x0</field> + </register> + <register address="0x000040CC" description="IP Blk = MC_BASE2 Access=RW " name="CFG_REF_PER"> + <field Type="RW" name="CFG_REF_PER" offset="0" width="32">0xC34</field> + </register> + <register address="0x000040D0" description="IP Blk = MC_BASE2 Access=RW " name="CFG_STARTUP_DELAY"> + <field Type="RW" name="CFG_STARTUP_DELAY" offset="0" width="32">0x27100</field> + </register> + <register address="0x000040D4" description="IP Blk = MC_BASE2 Access=RW " name="CFG_MEM_COLBITS"> + <field Type="RW" name="CFG_MEM_COLBITS" offset="0" width="32">0xA</field> + </register> + <register address="0x000040D8" description="IP Blk = MC_BASE2 Access=RW " name="CFG_MEM_ROWBITS"> + <field Type="RW" name="CFG_MEM_ROWBITS" offset="0" width="32">0x10</field> + </register> + <register address="0x000040DC" description="IP Blk = MC_BASE2 Access=RW " name="CFG_MEM_BANKBITS"> + <field Type="RW" name="CFG_MEM_BANKBITS" offset="0" width="32">0x3</field> + </register> + <register address="0x000040E0" description="IP Blk = MC_BASE2 Access=RW " name="CFG_ODT_RD_MAP_CS0"> + <field Type="RW" name="CFG_ODT_RD_MAP_CS0" offset="0" width="32">0x0</field> + </register> + <register address="0x000040E4" description="IP Blk = MC_BASE2 Access=RW " name="CFG_ODT_RD_MAP_CS1"> + <field Type="RW" name="CFG_ODT_RD_MAP_CS1" offset="0" width="32">0x0</field> + </register> + <register address="0x000040E8" description="IP Blk = MC_BASE2 Access=RW " name="CFG_ODT_RD_MAP_CS2"> + <field Type="RW" name="CFG_ODT_RD_MAP_CS2" offset="0" width="32">0x0</field> + </register> + <register address="0x000040EC" description="IP Blk = MC_BASE2 Access=RW " name="CFG_ODT_RD_MAP_CS3"> + <field Type="RW" name="CFG_ODT_RD_MAP_CS3" offset="0" width="32">0x0</field> + </register> + <register address="0x000040F0" description="IP Blk = MC_BASE2 Access=RW " name="CFG_ODT_RD_MAP_CS4"> + <field Type="RW" name="CFG_ODT_RD_MAP_CS4" offset="0" width="32">0x0</field> + </register> + <register address="0x000040F4" description="IP Blk = MC_BASE2 Access=RW " name="CFG_ODT_RD_MAP_CS5"> + <field Type="RW" name="CFG_ODT_RD_MAP_CS5" offset="0" width="32">0x0</field> + </register> + <register address="0x000040F8" description="IP Blk = MC_BASE2 Access=RW " name="CFG_ODT_RD_MAP_CS6"> + <field Type="RW" name="CFG_ODT_RD_MAP_CS6" offset="0" width="32">0x0</field> + </register> + <register address="0x000040FC" description="IP Blk = MC_BASE2 Access=RW " name="CFG_ODT_RD_MAP_CS7"> + <field Type="RW" name="CFG_ODT_RD_MAP_CS7" offset="0" width="32">0x0</field> + </register> + <register address="0x00004120" description="IP Blk = MC_BASE2 Access=RW " name="CFG_ODT_WR_MAP_CS0"> + <field Type="RW" name="CFG_ODT_WR_MAP_CS0" offset="0" width="32">0x0</field> + </register> + <register address="0x00004124" description="IP Blk = MC_BASE2 Access=RW " name="CFG_ODT_WR_MAP_CS1"> + <field Type="RW" name="CFG_ODT_WR_MAP_CS1" offset="0" width="32">0x0</field> + </register> + <register address="0x00004128" description="IP Blk = MC_BASE2 Access=RW " name="CFG_ODT_WR_MAP_CS2"> + <field Type="RW" name="CFG_ODT_WR_MAP_CS2" offset="0" width="32">0x0</field> + </register> + <register address="0x0000412C" description="IP Blk = MC_BASE2 Access=RW " name="CFG_ODT_WR_MAP_CS3"> + <field Type="RW" name="CFG_ODT_WR_MAP_CS3" offset="0" width="32">0x0</field> + </register> + <register address="0x00004130" description="IP Blk = MC_BASE2 Access=RW " name="CFG_ODT_WR_MAP_CS4"> + <field Type="RW" name="CFG_ODT_WR_MAP_CS4" offset="0" width="32">0x0</field> + </register> + <register address="0x00004134" description="IP Blk = MC_BASE2 Access=RW " name="CFG_ODT_WR_MAP_CS5"> + <field Type="RW" name="CFG_ODT_WR_MAP_CS5" offset="0" width="32">0x0</field> + </register> + <register address="0x00004138" description="IP Blk = MC_BASE2 Access=RW " name="CFG_ODT_WR_MAP_CS6"> + <field Type="RW" name="CFG_ODT_WR_MAP_CS6" offset="0" width="32">0x0</field> + </register> + <register address="0x0000413C" description="IP Blk = MC_BASE2 Access=RW " name="CFG_ODT_WR_MAP_CS7"> + <field Type="RW" name="CFG_ODT_WR_MAP_CS7" offset="0" width="32">0x0</field> + </register> + <register address="0x00004160" description="IP Blk = MC_BASE2 Access=RW " name="CFG_ODT_RD_TURN_ON"> + <field Type="RW" name="CFG_ODT_RD_TURN_ON" offset="0" width="32">0x0</field> + </register> + <register address="0x00004164" description="IP Blk = MC_BASE2 Access=RW " name="CFG_ODT_WR_TURN_ON"> + <field Type="RW" name="CFG_ODT_WR_TURN_ON" offset="0" width="32">0x0</field> + </register> + <register address="0x00004168" description="IP Blk = MC_BASE2 Access=RW " name="CFG_ODT_RD_TURN_OFF"> + <field Type="RW" name="CFG_ODT_RD_TURN_OFF" offset="0" width="32">0x0</field> + </register> + <register address="0x0000416C" description="IP Blk = MC_BASE2 Access=RW " name="CFG_ODT_WR_TURN_OFF"> + <field Type="RW" name="CFG_ODT_WR_TURN_OFF" offset="0" width="32">0x0</field> + </register> + <register address="0x00004178" description="IP Blk = MC_BASE2 Access=RW " name="CFG_EMR3"> + <field Type="RW" name="CFG_EMR3" offset="0" width="32">0x0</field> + </register> + <register address="0x0000417C" description="IP Blk = MC_BASE2 Access=RW " name="CFG_TWO_T"> + <field Type="RW" name="CFG_TWO_T" offset="0" width="32">0x0</field> + </register> + <register address="0x00004180" description="IP Blk = MC_BASE2 Access=RW " name="CFG_TWO_T_SEL_CYCLE"> + <field Type="RW" name="CFG_TWO_T_SEL_CYCLE" offset="0" width="32">0x1</field> + </register> + <register address="0x00004184" description="IP Blk = MC_BASE2 Access=RW " name="CFG_REGDIMM"> + <field Type="RW" name="CFG_REGDIMM" offset="0" width="32">0x0</field> + </register> + <register address="0x00004188" description="IP Blk = MC_BASE2 Access=RW " name="CFG_MOD"> + <field Type="RW" name="CFG_MOD" offset="0" width="32">0xC</field> + </register> + <register address="0x0000418C" description="IP Blk = MC_BASE2 Access=RW " name="CFG_XS"> + <field Type="RW" name="CFG_XS" offset="0" width="32">0x5</field> + </register> + <register address="0x00004190" description="IP Blk = MC_BASE2 Access=RW " name="CFG_XSDLL"> + <field Type="RW" name="CFG_XSDLL" offset="0" width="32">0x00000200</field> + </register> + <register address="0x00004194" description="IP Blk = MC_BASE2 Access=RW " name="CFG_XPR"> + <field Type="RW" name="CFG_XPR" offset="0" width="32">0x5</field> + </register> + <register address="0x00004198" description="IP Blk = MC_BASE2 Access=RW " name="CFG_AL_MODE"> + <field Type="RW" name="CFG_AL_MODE" offset="0" width="32">0x0</field> + </register> + <register address="0x0000419C" description="IP Blk = MC_BASE2 Access=RW " name="CFG_CWL"> + <field Type="RW" name="CFG_CWL" offset="0" width="32">0x5</field> + </register> + <register address="0x000041A0" description="IP Blk = MC_BASE2 Access=RW " name="CFG_BL_MODE"> + <field Type="RW" name="CFG_BL_MODE" offset="0" width="32">0x0</field> + </register> + <register address="0x000041A4" description="IP Blk = MC_BASE2 Access=RW " name="CFG_TDQS"> + <field Type="RW" name="CFG_TDQS" offset="0" width="32">0x0</field> + </register> + <register address="0x000041A8" description="IP Blk = MC_BASE2 Access=RW " name="CFG_RTT_WR"> + <field Type="RW" name="CFG_RTT_WR" offset="0" width="32">0x0</field> + </register> + <register address="0x000041AC" description="IP Blk = MC_BASE2 Access=RW " name="CFG_LP_ASR"> + <field Type="RW" name="CFG_LP_ASR" offset="0" width="32">0x00000000</field> + </register> + <register address="0x000041B0" description="IP Blk = MC_BASE2 Access=RW " name="CFG_AUTO_SR"> + <field Type="RW" name="CFG_AUTO_SR" offset="0" width="32">0x0</field> + </register> + <register address="0x000041B4" description="IP Blk = MC_BASE2 Access=RW " name="CFG_SRT"> + <field Type="RW" name="CFG_SRT" offset="0" width="32">0x0</field> + </register> + <register address="0x000041B8" description="IP Blk = MC_BASE2 Access=RW " name="CFG_ADDR_MIRROR"> + <field Type="RW" name="CFG_ADDR_MIRROR" offset="0" width="32">0x0</field> + </register> + <register address="0x000041BC" description="IP Blk = MC_BASE2 Access=RW " name="CFG_ZQ_CAL_TYPE"> + <field Type="RW" name="CFG_ZQ_CAL_TYPE" offset="0" width="32">0x1</field> + </register> + <register address="0x000041C0" description="IP Blk = MC_BASE2 Access=RW " name="CFG_ZQ_CAL_PER"> + <field Type="RW" name="CFG_ZQ_CAL_PER" offset="0" width="32">0x27100</field> + </register> + <register address="0x000041C4" description="IP Blk = MC_BASE2 Access=RW " name="CFG_AUTO_ZQ_CAL_EN"> + <field Type="RW" name="CFG_AUTO_ZQ_CAL_EN" offset="0" width="32">0x0</field> + </register> + <register address="0x000041C8" description="IP Blk = MC_BASE2 Access=RW " name="CFG_MEMORY_TYPE"> + <field Type="RW" name="CFG_MEMORY_TYPE" offset="0" width="32">0x400</field> + </register> + <register address="0x000041CC" description="IP Blk = MC_BASE2 Access=RW " name="CFG_ONLY_SRANK_CMDS"> + <field Type="RW" name="CFG_ONLY_SRANK_CMDS" offset="0" width="32">0x0</field> + </register> + <register address="0x000041D0" description="IP Blk = MC_BASE2 Access=RW " name="CFG_NUM_RANKS"> + <field Type="RW" name="CFG_NUM_RANKS" offset="0" width="32">0x1</field> + </register> + <register address="0x000041D4" description="IP Blk = MC_BASE2 Access=RW " name="CFG_QUAD_RANK"> + <field Type="RW" name="CFG_QUAD_RANK" offset="0" width="32">0x0</field> + </register> + <register address="0x000041DC" description="IP Blk = MC_BASE2 Access=RW " name="CFG_EARLY_RANK_TO_WR_START"> + <field Type="RW" name="CFG_EARLY_RANK_TO_WR_START" offset="0" width="32">0x0</field> + </register> + <register address="0x000041E0" description="IP Blk = MC_BASE2 Access=RW " name="CFG_EARLY_RANK_TO_RD_START"> + <field Type="RW" name="CFG_EARLY_RANK_TO_RD_START" offset="0" width="32">0x0</field> + </register> + <register address="0x000041E4" description="IP Blk = MC_BASE2 Access=RW " name="CFG_PASR_BANK"> + <field Type="RW" name="CFG_PASR_BANK" offset="0" width="32">0x00000000</field> + </register> + <register address="0x000041E8" description="IP Blk = MC_BASE2 Access=RW " name="CFG_PASR_SEG"> + <field Type="RW" name="CFG_PASR_SEG" offset="0" width="32">0x00000000</field> + </register> + <register address="0x000041EC" description="IP Blk = MC_BASE2 Access=RW " name="INIT_MRR_MODE"> + <field Type="RW" name="INIT_MRR_MODE" offset="0" width="32">0x00000000</field> + </register> + <register address="0x000041F0" description="IP Blk = MC_BASE2 Access=RW " name="INIT_MR_W_REQ"> + <field Type="RW" name="INIT_MR_W_REQ" offset="0" width="32">0x00000000</field> + </register> + <register address="0x000041F4" description="IP Blk = MC_BASE2 Access=RW " name="INIT_MR_ADDR"> + <field Type="RW" name="INIT_MR_ADDR" offset="0" width="32">0x00000000</field> + </register> + <register address="0x000041F8" description="IP Blk = MC_BASE2 Access=RW " name="INIT_MR_WR_DATA"> + <field Type="RW" name="INIT_MR_WR_DATA" offset="0" width="32">0x00000000</field> + </register> + <register address="0x000041FC" description="IP Blk = MC_BASE2 Access=RW " name="INIT_MR_WR_MASK"> + <field Type="RW" name="INIT_MR_WR_MASK" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00004200" description="IP Blk = MC_BASE2 Access=RW " name="INIT_NOP"> + <field Type="RW" name="INIT_NOP" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00004204" description="IP Blk = MC_BASE2 Access=RW " name="CFG_INIT_DURATION"> + <field Type="RW" name="CFG_INIT_DURATION" offset="0" width="32">0x640</field> + </register> + <register address="0x00004208" description="IP Blk = MC_BASE2 Access=RW " name="CFG_ZQINIT_CAL_DURATION"> + <field Type="RW" name="CFG_ZQINIT_CAL_DURATION" offset="0" width="32">0x0</field> + </register> + <register address="0x0000420C" description="IP Blk = MC_BASE2 Access=RW " name="CFG_ZQ_CAL_L_DURATION"> + <field Type="RW" name="CFG_ZQ_CAL_L_DURATION" offset="0" width="32">0x0</field> + </register> + <register address="0x00004210" description="IP Blk = MC_BASE2 Access=RW " name="CFG_ZQ_CAL_S_DURATION"> + <field Type="RW" name="CFG_ZQ_CAL_S_DURATION" offset="0" width="32">0x0</field> + </register> + <register address="0x00004214" description="IP Blk = MC_BASE2 Access=RW " name="CFG_ZQ_CAL_R_DURATION"> + <field Type="RW" name="CFG_ZQ_CAL_R_DURATION" offset="0" width="32">0x28</field> + </register> + <register address="0x00004218" description="IP Blk = MC_BASE2 Access=RW " name="CFG_MRR"> + <field Type="RW" name="CFG_MRR" offset="0" width="32">0x8</field> + </register> + <register address="0x0000421C" description="IP Blk = MC_BASE2 Access=RW " name="CFG_MRW"> + <field Type="RW" name="CFG_MRW" offset="0" width="32">0xA</field> + </register> + <register address="0x00004220" description="IP Blk = MC_BASE2 Access=RW " name="CFG_ODT_POWERDOWN"> + <field Type="RW" name="CFG_ODT_POWERDOWN" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00004224" description="IP Blk = MC_BASE2 Access=RW " name="CFG_WL"> + <field Type="RW" name="CFG_WL" offset="0" width="32">0x8</field> + </register> + <register address="0x00004228" description="IP Blk = MC_BASE2 Access=RW " name="CFG_RL"> + <field Type="RW" name="CFG_RL" offset="0" width="32">0xE</field> + </register> + <register address="0x0000422C" description="IP Blk = MC_BASE2 Access=RW " name="CFG_CAL_READ_PERIOD"> + <field Type="RW" name="CFG_CAL_READ_PERIOD" offset="0" width="32">0x0</field> + </register> + <register address="0x00004230" description="IP Blk = MC_BASE2 Access=RW " name="CFG_NUM_CAL_READS"> + <field Type="RW" name="CFG_NUM_CAL_READS" offset="0" width="32">0x1</field> + </register> + <register address="0x00004234" description="IP Blk = MC_BASE2 Access=RW " name="INIT_SELF_REFRESH"> + <field Type="RW" name="INIT_SELF_REFRESH" offset="0" width="32">0x00000000</field> + </register> + <register address="0x0000423C" description="IP Blk = MC_BASE2 Access=RW " name="INIT_POWER_DOWN"> + <field Type="RW" name="INIT_POWER_DOWN" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00004244" description="IP Blk = MC_BASE2 Access=RW " name="INIT_FORCE_WRITE"> + <field Type="RW" name="INIT_FORCE_WRITE" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00004248" description="IP Blk = MC_BASE2 Access=RW " name="INIT_FORCE_WRITE_CS"> + <field Type="RW" name="INIT_FORCE_WRITE_CS" offset="0" width="32">0x00000000</field> + </register> + <register address="0x0000424C" description="IP Blk = MC_BASE2 Access=RW " name="CFG_CTRLR_INIT_DISABLE"> + <field Type="RW" name="CFG_CTRLR_INIT_DISABLE" offset="0" width="32">0x0</field> + </register> + <register address="0x00004258" description="IP Blk = MC_BASE2 Access=RW " name="INIT_RDIMM_COMPLETE"> + <field Type="RW" name="INIT_RDIMM_COMPLETE" offset="0" width="32">0x00000000</field> + </register> + <register address="0x0000425C" description="IP Blk = MC_BASE2 Access=RW " name="CFG_RDIMM_LAT"> + <field Type="RW" name="CFG_RDIMM_LAT" offset="0" width="32">0x0</field> + </register> + <register address="0x00004260" description="IP Blk = MC_BASE2 Access=RW " name="CFG_RDIMM_BSIDE_INVERT"> + <field Type="RW" name="CFG_RDIMM_BSIDE_INVERT" offset="0" width="32">0x00000001</field> + </register> + <register address="0x00004264" description="IP Blk = MC_BASE2 Access=RW " name="CFG_LRDIMM"> + <field Type="RW" name="CFG_LRDIMM" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00004268" description="IP Blk = MC_BASE2 Access=RW " name="INIT_MEMORY_RESET_MASK"> + <field Type="RW" name="INIT_MEMORY_RESET_MASK" offset="0" width="32">0x00000000</field> + </register> + <register address="0x0000426C" description="IP Blk = MC_BASE2 Access=RW " name="CFG_RD_PREAMB_TOGGLE"> + <field Type="RW" name="CFG_RD_PREAMB_TOGGLE" offset="0" width="32">0x0</field> + </register> + <register address="0x00004270" description="IP Blk = MC_BASE2 Access=RW " name="CFG_RD_POSTAMBLE"> + <field Type="RW" name="CFG_RD_POSTAMBLE" offset="0" width="32">0x0</field> + </register> + <register address="0x00004274" description="IP Blk = MC_BASE2 Access=RW " name="CFG_PU_CAL"> + <field Type="RW" name="CFG_PU_CAL" offset="0" width="32">0x1</field> + </register> + <register address="0x00004278" description="IP Blk = MC_BASE2 Access=RW " name="CFG_DQ_ODT"> + <field Type="RW" name="CFG_DQ_ODT" offset="0" width="32">0x2</field> + </register> + <register address="0x0000427C" description="IP Blk = MC_BASE2 Access=RW " name="CFG_CA_ODT"> + <field Type="RW" name="CFG_CA_ODT" offset="0" width="32">0x4</field> + </register> + <register address="0x00004280" description="IP Blk = MC_BASE2 Access=RW " name="CFG_ZQLATCH_DURATION"> + <field Type="RW" name="CFG_ZQLATCH_DURATION" offset="0" width="32">0x18</field> + </register> + <register address="0x00004284" description="IP Blk = MC_BASE2 Access=RW " name="INIT_CAL_SELECT"> + <field Type="RW" name="INIT_CAL_SELECT" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00004288" description="IP Blk = MC_BASE2 Access=RW " name="INIT_CAL_L_R_REQ"> + <field Type="RW" name="INIT_CAL_L_R_REQ" offset="0" width="32">0x00000000</field> + </register> + <register address="0x0000428C" description="IP Blk = MC_BASE2 Access=RW " name="INIT_CAL_L_B_SIZE"> + <field Type="RW" name="INIT_CAL_L_B_SIZE" offset="0" width="32">0x00000000</field> + </register> + <register address="0x000042A0" description="IP Blk = MC_BASE2 Access=RW " name="INIT_RWFIFO"> + <field Type="RW" name="INIT_RWFIFO" offset="0" width="32">0x00000000</field> + </register> + <register address="0x000042A4" description="IP Blk = MC_BASE2 Access=RW " name="INIT_RD_DQCAL"> + <field Type="RW" name="INIT_RD_DQCAL" offset="0" width="32">0x00000000</field> + </register> + <register address="0x000042A8" description="IP Blk = MC_BASE2 Access=RW " name="INIT_START_DQSOSC"> + <field Type="RW" name="INIT_START_DQSOSC" offset="0" width="32">0x00000000</field> + </register> + <register address="0x000042AC" description="IP Blk = MC_BASE2 Access=RW " name="INIT_STOP_DQSOSC"> + <field Type="RW" name="INIT_STOP_DQSOSC" offset="0" width="32">0x00000000</field> + </register> + <register address="0x000042B0" description="IP Blk = MC_BASE2 Access=RW " name="INIT_ZQ_CAL_START"> + <field Type="RW" name="INIT_ZQ_CAL_START" offset="0" width="32">0x00000000</field> + </register> + <register address="0x000042B4" description="IP Blk = MC_BASE2 Access=RW " name="CFG_WR_POSTAMBLE"> + <field Type="RW" name="CFG_WR_POSTAMBLE" offset="0" width="32">0x0</field> + </register> + <register address="0x000042BC" description="IP Blk = MC_BASE2 Access=RW " name="INIT_CAL_L_ADDR_0"> + <field Type="RW" name="INIT_CAL_L_ADDR_0" offset="0" width="32">0x00000000</field> + </register> + <register address="0x000042C0" description="IP Blk = MC_BASE2 Access=RW " name="INIT_CAL_L_ADDR_1"> + <field Type="RW" name="INIT_CAL_L_ADDR_1" offset="0" width="32">0x00000000</field> + </register> + <register address="0x000042C4" description="IP Blk = MC_BASE2 Access=RW " name="CFG_CTRLUPD_TRIG"> + <field Type="RW" name="CFG_CTRLUPD_TRIG" offset="0" width="32">0x0</field> + </register> + <register address="0x000042C8" description="IP Blk = MC_BASE2 Access=RW " name="CFG_CTRLUPD_START_DELAY"> + <field Type="RW" name="CFG_CTRLUPD_START_DELAY" offset="0" width="32">0x0</field> + </register> + <register address="0x000042CC" description="IP Blk = MC_BASE2 Access=RW " name="CFG_DFI_T_CTRLUPD_MAX"> + <field Type="RW" name="CFG_DFI_T_CTRLUPD_MAX" offset="0" width="32">0x0</field> + </register> + <register address="0x000042D0" description="IP Blk = MC_BASE2 Access=RW " name="CFG_CTRLR_BUSY_SEL"> + <field Type="RW" name="CFG_CTRLR_BUSY_SEL" offset="0" width="32">0x00000000</field> + </register> + <register address="0x000042D4" description="IP Blk = MC_BASE2 Access=RW " name="CFG_CTRLR_BUSY_VALUE"> + <field Type="RW" name="CFG_CTRLR_BUSY_VALUE" offset="0" width="32">0x00000000</field> + </register> + <register address="0x000042D8" description="IP Blk = MC_BASE2 Access=RW " name="CFG_CTRLR_BUSY_TURN_OFF_DELAY"> + <field Type="RW" name="CFG_CTRLR_BUSY_TURN_OFF_DELAY" offset="0" width="32">0x00000000</field> + </register> + <register address="0x000042DC" description="IP Blk = MC_BASE2 Access=RW " name="CFG_CTRLR_BUSY_SLOW_RESTART_WINDOW"> + <field Type="RW" name="CFG_CTRLR_BUSY_SLOW_RESTART_WINDOW" offset="0" width="32">0x00000000</field> + </register> + <register address="0x000042E0" description="IP Blk = MC_BASE2 Access=RW " name="CFG_CTRLR_BUSY_RESTART_HOLDOFF"> + <field Type="RW" name="CFG_CTRLR_BUSY_RESTART_HOLDOFF" offset="0" width="32">0x00000000</field> + </register> + <register address="0x000042E4" description="IP Blk = MC_BASE2 Access=RW " name="CFG_PARITY_RDIMM_DELAY"> + <field Type="RW" name="CFG_PARITY_RDIMM_DELAY" offset="0" width="32">0x0</field> + </register> + <register address="0x000042E8" description="IP Blk = MC_BASE2 Access=RW " name="CFG_CTRLR_BUSY_ENABLE"> + <field Type="RW" name="CFG_CTRLR_BUSY_ENABLE" offset="0" width="32">0x00000000</field> + </register> + <register address="0x000042EC" description="IP Blk = MC_BASE2 Access=RW " name="CFG_ASYNC_ODT"> + <field Type="RW" name="CFG_ASYNC_ODT" offset="0" width="32">0x00000000</field> + </register> + <register address="0x000042F0" description="IP Blk = MC_BASE2 Access=RW " name="CFG_ZQ_CAL_DURATION"> + <field Type="RW" name="CFG_ZQ_CAL_DURATION" offset="0" width="32">0x320</field> + </register> + <register address="0x000042F4" description="IP Blk = MC_BASE2 Access=RW " name="CFG_MRRI"> + <field Type="RW" name="CFG_MRRI" offset="0" width="32">0x12</field> + </register> + <register address="0x000042F8" description="IP Blk = MC_BASE2 Access=RW " name="INIT_ODT_FORCE_EN"> + <field Type="RW" name="INIT_ODT_FORCE_EN" offset="0" width="32">0x00000000</field> + </register> + <register address="0x000042FC" description="IP Blk = MC_BASE2 Access=RW " name="INIT_ODT_FORCE_RANK"> + <field Type="RW" name="INIT_ODT_FORCE_RANK" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00004300" description="IP Blk = MC_BASE2 Access=RW " name="CFG_PHYUPD_ACK_DELAY"> + <field Type="RW" name="CFG_PHYUPD_ACK_DELAY" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00004304" description="IP Blk = MC_BASE2 Access=RW " name="CFG_MIRROR_X16_BG0_BG1"> + <field Type="RW" name="CFG_MIRROR_X16_BG0_BG1" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00004308" description="IP Blk = MC_BASE2 Access=RW " name="INIT_PDA_MR_W_REQ"> + <field Type="RW" name="INIT_PDA_MR_W_REQ" offset="0" width="32">0x00000000</field> + </register> + <register address="0x0000430C" description="IP Blk = MC_BASE2 Access=RW " name="INIT_PDA_NIBBLE_SELECT"> + <field Type="RW" name="INIT_PDA_NIBBLE_SELECT" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00004310" description="IP Blk = MC_BASE2 Access=RW " name="CFG_DRAM_CLK_DISABLE_IN_SELF_REFRESH"> + <field Type="RW" name="CFG_DRAM_CLK_DISABLE_IN_SELF_REFRESH" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00004314" description="IP Blk = MC_BASE2 Access=RW " name="CFG_CKSRE"> + <field Type="RW" name="CFG_CKSRE" offset="0" width="32">0x00000008</field> + </register> + <register address="0x00004318" description="IP Blk = MC_BASE2 Access=RW " name="CFG_CKSRX"> + <field Type="RW" name="CFG_CKSRX" offset="0" width="32">0x0000000b</field> + </register> + <register address="0x0000431C" description="IP Blk = MC_BASE2 Access=RW " name="CFG_RCD_STAB"> + <field Type="RW" name="CFG_RCD_STAB" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00004320" description="IP Blk = MC_BASE2 Access=RW " name="CFG_DFI_T_CTRL_DELAY"> + <field Type="RW" name="CFG_DFI_T_CTRL_DELAY" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00004324" description="IP Blk = MC_BASE2 Access=RW " name="CFG_DFI_T_DRAM_CLK_ENABLE"> + <field Type="RW" name="CFG_DFI_T_DRAM_CLK_ENABLE" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00004328" description="IP Blk = MC_BASE2 Access=RW " name="CFG_IDLE_TIME_TO_SELF_REFRESH"> + <field Type="RW" name="CFG_IDLE_TIME_TO_SELF_REFRESH" offset="0" width="32">0x00000000</field> + </register> + <register address="0x0000432C" description="IP Blk = MC_BASE2 Access=RW " name="CFG_IDLE_TIME_TO_POWER_DOWN"> + <field Type="RW" name="CFG_IDLE_TIME_TO_POWER_DOWN" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00004330" description="IP Blk = MC_BASE2 Access=RW " name="CFG_BURST_RW_REFRESH_HOLDOFF"> + <field Type="RW" name="CFG_BURST_RW_REFRESH_HOLDOFF" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00004384" description="IP Blk = MC_BASE2 Access=RW " name="CFG_BG_INTERLEAVE"> + <field Type="RW" name="CFG_BG_INTERLEAVE" offset="0" width="32">0x00000001</field> + </register> + <register address="0x000043FC" description="IP Blk = MC_BASE2 Access=RW " name="CFG_REFRESH_DURING_PHY_TRAINING"> + <field Type="RW" name="CFG_REFRESH_DURING_PHY_TRAINING" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00004C00" description="IP Blk = MPFE Access=RW " name="CFG_STARVE_TIMEOUT_P0"> + <field Type="RW" name="CFG_STARVE_TIMEOUT_P0" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00004C04" description="IP Blk = MPFE Access=RW " name="CFG_STARVE_TIMEOUT_P1"> + <field Type="RW" name="CFG_STARVE_TIMEOUT_P1" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00004C08" description="IP Blk = MPFE Access=RW " name="CFG_STARVE_TIMEOUT_P2"> + <field Type="RW" name="CFG_STARVE_TIMEOUT_P2" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00004C0C" description="IP Blk = MPFE Access=RW " name="CFG_STARVE_TIMEOUT_P3"> + <field Type="RW" name="CFG_STARVE_TIMEOUT_P3" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00004C10" description="IP Blk = MPFE Access=RW " name="CFG_STARVE_TIMEOUT_P4"> + <field Type="RW" name="CFG_STARVE_TIMEOUT_P4" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00004C14" description="IP Blk = MPFE Access=RW " name="CFG_STARVE_TIMEOUT_P5"> + <field Type="RW" name="CFG_STARVE_TIMEOUT_P5" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00004C18" description="IP Blk = MPFE Access=RW " name="CFG_STARVE_TIMEOUT_P6"> + <field Type="RW" name="CFG_STARVE_TIMEOUT_P6" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00004C1C" description="IP Blk = MPFE Access=RW " name="CFG_STARVE_TIMEOUT_P7"> + <field Type="RW" name="CFG_STARVE_TIMEOUT_P7" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00005000" description="IP Blk = REORDER Access=RW " name="CFG_REORDER_EN"> + <field Type="RW" name="CFG_REORDER_EN" offset="0" width="32">0x00000001</field> + </register> + <register address="0x00005004" description="IP Blk = REORDER Access=RW " name="CFG_REORDER_QUEUE_EN"> + <field Type="RW" name="CFG_REORDER_QUEUE_EN" offset="0" width="32">0x00000001</field> + </register> + <register address="0x00005008" description="IP Blk = REORDER Access=RW " name="CFG_INTRAPORT_REORDER_EN"> + <field Type="RW" name="CFG_INTRAPORT_REORDER_EN" offset="0" width="32">0x00000000</field> + </register> + <register address="0x0000500C" description="IP Blk = REORDER Access=RW " name="CFG_MAINTAIN_COHERENCY"> + <field Type="RW" name="CFG_MAINTAIN_COHERENCY" offset="0" width="32">0x00000001</field> + </register> + <register address="0x00005010" description="IP Blk = REORDER Access=RW " name="CFG_Q_AGE_LIMIT"> + <field Type="RW" name="CFG_Q_AGE_LIMIT" offset="0" width="32">0x000000FF</field> + </register> + <register address="0x00005018" description="IP Blk = REORDER Access=RW " name="CFG_RO_CLOSED_PAGE_POLICY"> + <field Type="RW" name="CFG_RO_CLOSED_PAGE_POLICY" offset="0" width="32">0x00000000</field> + </register> + <register address="0x0000501C" description="IP Blk = REORDER Access=RW " name="CFG_REORDER_RW_ONLY"> + <field Type="RW" name="CFG_REORDER_RW_ONLY" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00005020" description="IP Blk = REORDER Access=RW " name="CFG_RO_PRIORITY_EN"> + <field Type="RW" name="CFG_RO_PRIORITY_EN" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00005400" description="IP Blk = RMW Access=RW " name="CFG_DM_EN"> + <field Type="RW" name="CFG_DM_EN" offset="0" width="32">0x1</field> + </register> + <register address="0x00005404" description="IP Blk = RMW Access=RW " name="CFG_RMW_EN"> + <field Type="RW" name="CFG_RMW_EN" offset="0" width="32">0x0</field> + </register> + <register address="0x00005800" description="IP Blk = ECC Access=RW " name="CFG_ECC_CORRECTION_EN"> + <field Type="RW" name="CFG_ECC_CORRECTION_EN" offset="0" width="32">0x0</field> + </register> + <register address="0x00005840" description="IP Blk = ECC Access=RW " name="CFG_ECC_BYPASS"> + <field Type="RW" name="CFG_ECC_BYPASS" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00005844" description="IP Blk = ECC Access=RW " name="INIT_WRITE_DATA_1B_ECC_ERROR_GEN"> + <field Type="RW" name="INIT_WRITE_DATA_1B_ECC_ERROR_GEN" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00005848" description="IP Blk = ECC Access=RW " name="INIT_WRITE_DATA_2B_ECC_ERROR_GEN"> + <field Type="RW" name="INIT_WRITE_DATA_2B_ECC_ERROR_GEN" offset="0" width="32">0x00000000</field> + </register> + <register address="0x0000585C" description="IP Blk = ECC Access=RW " name="CFG_ECC_1BIT_INT_THRESH"> + <field Type="RW" name="CFG_ECC_1BIT_INT_THRESH" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00005C00" description="IP Blk = READ_CAPT Access=RW " name="INIT_READ_CAPTURE_ADDR"> + <field Type="RW" name="INIT_READ_CAPTURE_ADDR" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00006400" description="IP Blk = MTA Access=RW " name="CFG_ERROR_GROUP_SEL"> + <field Type="RW" name="CFG_ERROR_GROUP_SEL" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00006404" description="IP Blk = MTA Access=RW " name="CFG_DATA_SEL"> + <field Type="RW" name="CFG_DATA_SEL" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00006408" description="IP Blk = MTA Access=RW " name="CFG_TRIG_MODE"> + <field Type="RW" name="CFG_TRIG_MODE" offset="0" width="32">0x00000000</field> + </register> + <register address="0x0000640C" description="IP Blk = MTA Access=RW " name="CFG_POST_TRIG_CYCS"> + <field Type="RW" name="CFG_POST_TRIG_CYCS" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00006410" description="IP Blk = MTA Access=RW " name="CFG_TRIG_MASK"> + <field Type="RW" name="CFG_TRIG_MASK" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00006414" description="IP Blk = MTA Access=RW " name="CFG_EN_MASK"> + <field Type="RW" name="CFG_EN_MASK" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00006418" description="IP Blk = MTA Access=RW " name="MTC_ACQ_ADDR"> + <field Type="RW" name="MTC_ACQ_ADDR" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00006430" description="IP Blk = MTA Access=RW " name="CFG_TRIG_MT_ADDR_0"> + <field Type="RW" name="CFG_TRIG_MT_ADDR_0" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00006434" description="IP Blk = MTA Access=RW " name="CFG_TRIG_MT_ADDR_1"> + <field Type="RW" name="CFG_TRIG_MT_ADDR_1" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00006438" description="IP Blk = MTA Access=RW " name="CFG_TRIG_ERR_MASK_0"> + <field Type="RW" name="CFG_TRIG_ERR_MASK_0" offset="0" width="32">0x00000000</field> + </register> + <register address="0x0000643C" description="IP Blk = MTA Access=RW " name="CFG_TRIG_ERR_MASK_1"> + <field Type="RW" name="CFG_TRIG_ERR_MASK_1" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00006440" description="IP Blk = MTA Access=RW " name="CFG_TRIG_ERR_MASK_2"> + <field Type="RW" name="CFG_TRIG_ERR_MASK_2" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00006444" description="IP Blk = MTA Access=RW " name="CFG_TRIG_ERR_MASK_3"> + <field Type="RW" name="CFG_TRIG_ERR_MASK_3" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00006448" description="IP Blk = MTA Access=RW " name="CFG_TRIG_ERR_MASK_4"> + <field Type="RW" name="CFG_TRIG_ERR_MASK_4" offset="0" width="32">0x00000000</field> + </register> + <register address="0x0000644C" description="IP Blk = MTA Access=RW " name="MTC_ACQ_WR_DATA_0"> + <field Type="RW" name="MTC_ACQ_WR_DATA_0" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00006450" description="IP Blk = MTA Access=RW " name="MTC_ACQ_WR_DATA_1"> + <field Type="RW" name="MTC_ACQ_WR_DATA_1" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00006454" description="IP Blk = MTA Access=RW " name="MTC_ACQ_WR_DATA_2"> + <field Type="RW" name="MTC_ACQ_WR_DATA_2" offset="0" width="32">0x00000000</field> + </register> + <register address="0x0000652C" description="IP Blk = MTA Access=RW " name="CFG_PRE_TRIG_CYCS"> + <field Type="RW" name="CFG_PRE_TRIG_CYCS" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00006550" description="IP Blk = MTA Access=RW " name="CFG_DATA_SEL_FIRST_ERROR"> + <field Type="RW" name="CFG_DATA_SEL_FIRST_ERROR" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00007C00" description="IP Blk = DYN_WIDTH_ADJ Access=RW " name="CFG_DQ_WIDTH"> + <field Type="RW" name="CFG_DQ_WIDTH" offset="0" width="32">0x0</field> + </register> + <register address="0x00007C04" description="IP Blk = DYN_WIDTH_ADJ Access=RW " name="CFG_ACTIVE_DQ_SEL"> + <field Type="RW" name="CFG_ACTIVE_DQ_SEL" offset="0" width="32">0x00000000</field> + </register> + <register address="0x0000800C" description="IP Blk = CA_PAR_ERR Access=RW " name="INIT_CA_PARITY_ERROR_GEN_REQ"> + <field Type="RW" name="INIT_CA_PARITY_ERROR_GEN_REQ" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00008010" description="IP Blk = CA_PAR_ERR Access=RW " name="INIT_CA_PARITY_ERROR_GEN_CMD"> + <field Type="RW" name="INIT_CA_PARITY_ERROR_GEN_CMD" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00010000" description="IP Blk = DFI Access=RW " name="CFG_DFI_T_RDDATA_EN"> + <field Type="RW" name="CFG_DFI_T_RDDATA_EN" offset="0" width="32">0x15</field> + </register> + <register address="0x00010004" description="IP Blk = DFI Access=RW " name="CFG_DFI_T_PHY_RDLAT"> + <field Type="RW" name="CFG_DFI_T_PHY_RDLAT" offset="0" width="32">0x6</field> + </register> + <register address="0x00010008" description="IP Blk = DFI Access=RW " name="CFG_DFI_T_PHY_WRLAT"> + <field Type="RW" name="CFG_DFI_T_PHY_WRLAT" offset="0" width="32">0x3</field> + </register> + <register address="0x0001000C" description="IP Blk = DFI Access=RW " name="CFG_DFI_PHYUPD_EN"> + <field Type="RW" name="CFG_DFI_PHYUPD_EN" offset="0" width="32">0x00000001</field> + </register> + <register address="0x00010010" description="IP Blk = DFI Access=RW " name="INIT_DFI_LP_DATA_REQ"> + <field Type="RW" name="INIT_DFI_LP_DATA_REQ" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00010014" description="IP Blk = DFI Access=RW " name="INIT_DFI_LP_CTRL_REQ"> + <field Type="RW" name="INIT_DFI_LP_CTRL_REQ" offset="0" width="32">0x00000000</field> + </register> + <register address="0x0001001C" description="IP Blk = DFI Access=RW " name="INIT_DFI_LP_WAKEUP"> + <field Type="RW" name="INIT_DFI_LP_WAKEUP" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00010020" description="IP Blk = DFI Access=RW " name="INIT_DFI_DRAM_CLK_DISABLE"> + <field Type="RW" name="INIT_DFI_DRAM_CLK_DISABLE" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00010030" description="IP Blk = DFI Access=RW " name="CFG_DFI_DATA_BYTE_DISABLE"> + <field Type="RW" name="CFG_DFI_DATA_BYTE_DISABLE" offset="0" width="32">0x00000000</field> + </register> + <register address="0x0001003C" description="IP Blk = DFI Access=RW " name="CFG_DFI_LVL_SEL"> + <field Type="RW" name="CFG_DFI_LVL_SEL" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00010040" description="IP Blk = DFI Access=RW " name="CFG_DFI_LVL_PERIODIC"> + <field Type="RW" name="CFG_DFI_LVL_PERIODIC" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00010044" description="IP Blk = DFI Access=RW " name="CFG_DFI_LVL_PATTERN"> + <field Type="RW" name="CFG_DFI_LVL_PATTERN" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00010050" description="IP Blk = DFI Access=RW " name="PHY_DFI_INIT_START"> + <field Type="RW" name="PHY_DFI_INIT_START" offset="0" width="32">0x1</field> + </register> + <register address="0x00012C18" description="IP Blk = AXI_IF Access=RW " name="CFG_AXI_START_ADDRESS_AXI1_0"> + <field Type="RW" name="CFG_AXI_START_ADDRESS_AXI1_0" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00012C1C" description="IP Blk = AXI_IF Access=RW " name="CFG_AXI_START_ADDRESS_AXI1_1"> + <field Type="RW" name="CFG_AXI_START_ADDRESS_AXI1_1" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00012C20" description="IP Blk = AXI_IF Access=RW " name="CFG_AXI_START_ADDRESS_AXI2_0"> + <field Type="RW" name="CFG_AXI_START_ADDRESS_AXI2_0" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00012C24" description="IP Blk = AXI_IF Access=RW " name="CFG_AXI_START_ADDRESS_AXI2_1"> + <field Type="RW" name="CFG_AXI_START_ADDRESS_AXI2_1" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00012F18" description="IP Blk = AXI_IF Access=RW " name="CFG_AXI_END_ADDRESS_AXI1_0"> + <field Type="RW" name="CFG_AXI_END_ADDRESS_AXI1_0" offset="0" width="32">0x7FFFFFFF</field> + </register> + <register address="0x00012F1C" description="IP Blk = AXI_IF Access=RW " name="CFG_AXI_END_ADDRESS_AXI1_1"> + <field Type="RW" name="CFG_AXI_END_ADDRESS_AXI1_1" offset="0" width="32">0x0</field> + </register> + <register address="0x00012F20" description="IP Blk = AXI_IF Access=RW " name="CFG_AXI_END_ADDRESS_AXI2_0"> + <field Type="RW" name="CFG_AXI_END_ADDRESS_AXI2_0" offset="0" width="32">0x7FFFFFFF</field> + </register> + <register address="0x00012F24" description="IP Blk = AXI_IF Access=RW " name="CFG_AXI_END_ADDRESS_AXI2_1"> + <field Type="RW" name="CFG_AXI_END_ADDRESS_AXI2_1" offset="0" width="32">0x0</field> + </register> + <register address="0x00013218" description="IP Blk = AXI_IF Access=RW " name="CFG_MEM_START_ADDRESS_AXI1_0"> + <field Type="RW" name="CFG_MEM_START_ADDRESS_AXI1_0" offset="0" width="32">0x00000000</field> + </register> + <register address="0x0001321C" description="IP Blk = AXI_IF Access=RW " name="CFG_MEM_START_ADDRESS_AXI1_1"> + <field Type="RW" name="CFG_MEM_START_ADDRESS_AXI1_1" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00013220" description="IP Blk = AXI_IF Access=RW " name="CFG_MEM_START_ADDRESS_AXI2_0"> + <field Type="RW" name="CFG_MEM_START_ADDRESS_AXI2_0" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00013224" description="IP Blk = AXI_IF Access=RW " name="CFG_MEM_START_ADDRESS_AXI2_1"> + <field Type="RW" name="CFG_MEM_START_ADDRESS_AXI2_1" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00013514" description="IP Blk = AXI_IF Access=RW " name="CFG_ENABLE_BUS_HOLD_AXI1"> + <field Type="RW" name="CFG_ENABLE_BUS_HOLD_AXI1" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00013518" description="IP Blk = AXI_IF Access=RW " name="CFG_ENABLE_BUS_HOLD_AXI2"> + <field Type="RW" name="CFG_ENABLE_BUS_HOLD_AXI2" offset="0" width="32">0x00000000</field> + </register> + <register address="0x00013690" description="IP Blk = AXI_IF Access=RW " name="CFG_AXI_AUTO_PCH"> + <field Type="RW" name="CFG_AXI_AUTO_PCH" offset="0" width="32">0x00000000</field> + </register> + <register address="0x0003C000" description="IP Blk = csr_custom Access=RW " name="PHY_RESET_CONTROL"> + <field Type="RW" name="PHY_RESET_CONTROL" offset="0" width="32">0x8001</field> + </register> + <register address="0x0003C004" description="IP Blk = csr_custom Access=RW " name="PHY_PC_RANK"> + <field Type="RW" name="PHY_PC_RANK" offset="0" width="32">0x1</field> + </register> + <register address="0x0003C008" description="IP Blk = csr_custom Access=RW " name="PHY_RANKS_TO_TRAIN"> + <field Type="RW" name="PHY_RANKS_TO_TRAIN" offset="0" width="32">0x1</field> + </register> + <register address="0x0003C00C" description="IP Blk = csr_custom Access=RW " name="PHY_WRITE_REQUEST"> + <field Type="RW" name="PHY_WRITE_REQUEST" offset="0" width="32">0x00000000</field> + </register> + <register address="0x0003C014" description="IP Blk = csr_custom Access=RW " name="PHY_READ_REQUEST"> + <field Type="RW" name="PHY_READ_REQUEST" offset="0" width="32">0x00000000</field> + </register> + <register address="0x0003C01C" description="IP Blk = csr_custom Access=RW " name="PHY_WRITE_LEVEL_DELAY"> + <field Type="RW" name="PHY_WRITE_LEVEL_DELAY" offset="0" width="32">0x00000000</field> + </register> + <register address="0x0003C020" description="IP Blk = csr_custom Access=RW " name="PHY_GATE_TRAIN_DELAY"> + <field Type="RW" name="PHY_GATE_TRAIN_DELAY" offset="0" width="32">0x3F</field> + </register> + <register address="0x0003C024" description="IP Blk = csr_custom Access=RW " name="PHY_EYE_TRAIN_DELAY"> + <field Type="RW" name="PHY_EYE_TRAIN_DELAY" offset="0" width="32">0x3F</field> + </register> + <register address="0x0003C028" description="IP Blk = csr_custom Access=RW " name="PHY_EYE_PAT"> + <field Type="RW" name="PHY_EYE_PAT" offset="0" width="32">0x00000000</field> + </register> + <register address="0x0003C02C" description="IP Blk = csr_custom Access=RW " name="PHY_START_RECAL"> + <field Type="RW" name="PHY_START_RECAL" offset="0" width="32">0x00000000</field> + </register> + <register address="0x0003C030" description="IP Blk = csr_custom Access=RW " name="PHY_CLR_DFI_LVL_PERIODIC"> + <field Type="RW" name="PHY_CLR_DFI_LVL_PERIODIC" offset="0" width="32">0x00000000</field> + </register> + <register address="0x0003C034" description="IP Blk = csr_custom Access=RW " name="PHY_TRAIN_STEP_ENABLE"> + <field Type="RW" name="PHY_TRAIN_STEP_ENABLE" offset="0" width="32">0x18</field> + </register> + <register address="0x0003C038" description="IP Blk = csr_custom Access=RW " name="PHY_LPDDR_DQ_CAL_PAT"> + <field Type="RW" name="PHY_LPDDR_DQ_CAL_PAT" offset="0" width="32">0x00000000</field> + </register> + <register address="0x0003C03C" description="IP Blk = csr_custom Access=RW " name="PHY_INDPNDT_TRAINING"> + <field Type="RW" name="PHY_INDPNDT_TRAINING" offset="0" width="32">0x1</field> + </register> + <register address="0x0003C040" description="IP Blk = csr_custom Access=RW " name="PHY_ENCODED_QUAD_CS"> + <field Type="RW" name="PHY_ENCODED_QUAD_CS" offset="0" width="32">0x00000000</field> + </register> + <register address="0x0003C044" description="IP Blk = csr_custom Access=RW " name="PHY_HALF_CLK_DLY_ENABLE"> + <field Type="RW" name="PHY_HALF_CLK_DLY_ENABLE" offset="0" width="32">0x00000000</field> + </register> + </registers> + </ddrc> + </mss_ddr> + <mss_clocks> + <clocks> + <registers> + <register address="0" description="Ref Clock rate in MHz" name="MSS_EXT_SGMII_REF_CLK"> + <field Type="RW" name="MSS_EXT_SGMII_REF_CLK" offset="0" width="32">125000000</field> + </register> + <register address="0" description="CPU Clock rate in MHz" name="MSS_COREPLEX_CPU_CLK"> + <field Type="RW" name="MSS_COREPLEX_CPU_CLK" offset="0" width="32">600000000</field> + </register> + <register address="0" description="System Clock rate in MHz static power." name="MSS_SYSTEM_CLK"> + <field Type="RW" name="MSS_SYSTEM_CLK" offset="0" width="32">600000000</field> + </register> + <register address="0" description="RTC toggle Clock rate in MHz static power." name="MSS_RTC_TOGGLE_CLK"> + <field Type="RW" name="MSS_RTC_TOGGLE_CLK" offset="0" width="32">1000000</field> + </register> + <register address="0" description="AXI Clock rate in MHz static power." name="MSS_AXI_CLK"> + <field Type="RW" name="MSS_AXI_CLK" offset="0" width="32">300000000</field> + </register> + <register address="0" description="AXI Clock rate in MHz static power." name="MSS_APB_AHB_CLK"> + <field Type="RW" name="MSS_APB_AHB_CLK" offset="0" width="32">150000000</field> + </register> + </registers> + </clocks> + <mss_sys> + <registers> + <register address="0x00000008" description="Master clock config (00=/1 01=/2 10=/4 11=/8 )" name="CLOCK_CONFIG_CR"> + <field Type="RW" name="DIVIDER_CPU" offset="0" width="2">0x0</field> + <field Type="RW" name="DIVIDER_AXI" offset="2" width="2">0x1</field> + <field Type="RW" name="DIVIDER_APB_AHB" offset="4" width="2">0x2</field> + </register> + <register address="0x0000000C" description="RTC clock divider" name="RTC_CLOCK_CR"> + <field Type="RW" name="PERIOD" offset="0" width="12">0x7D</field> + </register> + <register address="0x000000B8" description="ENVM AHB Controller setup - - Clock period = (Value+1) * (1000/AHBFREQMHZ) e.g. 7 will generate a 40ns period 25MHz clock if the AHB clock is 200MHz" name="ENVM_CR"> + <field Type="RW" name="CLOCK_PERIOD" offset="0" width="6">0x6</field> + <field Type="RW" name="CLOCK_CONTINUOUS" offset="8" width="1">0x0</field> + <field Type="RW" name="CLOCK_SUPPRESS" offset="9" width="1">0x0</field> + <field Type="RW" name="READAHEAD" offset="16" width="1">0x1</field> + <field Type="RW" name="SLOWREAD" offset="17" width="1">0x0</field> + <field Type="RW" name="INTERRUPT_ENABLE" offset="18" width="1">0x1</field> + <field Type="RW" name="TIMER" offset="24" width="8">0x40</field> + </register> + </registers> + </mss_sys> + <mss_pll> + <registers> + <register address="0x00000004" description="PLL control register" name="PLL_CTRL"> + <field Type="RW" name="REG_POWERDOWN_B" offset="0" width="1">0x1</field> + <field Type="RW" name="REG_RFDIV_EN" offset="1" width="1">0x1</field> + <field Type="RW" name="REG_DIVQ0_EN" offset="2" width="1">0x1</field> + <field Type="RW" name="REG_DIVQ1_EN" offset="3" width="1">0x0</field> + <field Type="RW" name="REG_DIVQ2_EN" offset="4" width="1">0x1</field> + <field Type="RW" name="REG_DIVQ3_EN" offset="5" width="1">0x1</field> + <field Type="RW" name="REG_RFCLK_SEL" offset="6" width="1">0x0</field> + <field Type="RW" name="RESETONLOCK" offset="7" width="1">0x0</field> + <field Type="RW" name="BYPCK_SEL" offset="8" width="4">0x0</field> + <field Type="RW" name="REG_BYPASS_GO_B" offset="12" width="1">0x0</field> + <field Type="RSVD" name="RESERVE10" offset="13" width="3">0x0</field> + <field Type="RW" name="REG_BYPASSPRE" offset="16" width="4">0x0</field> + <field Type="RW" name="REG_BYPASSPOST" offset="20" width="4">0x0</field> + <field Type="RW" name="LP_REQUIRES_LOCK" offset="24" width="1">0x1</field> + <field Type="RO" name="LOCK" offset="25" width="1">0x0</field> + <field Type="RW" name="LOCK_INT_EN" offset="26" width="1">0x0</field> + <field Type="RW" name="UNLOCK_INT_EN" offset="27" width="1">0x0</field> + <field Type="SW1C" name="LOCK_INT" offset="28" width="1">0x0</field> + <field Type="SW1C" name="UNLOCK_INT" offset="29" width="1">0x0</field> + <field Type="RSVD" name="RESERVE11" offset="30" width="1">0x0</field> + <field Type="RO" name="LOCK_B" offset="31" width="1">0x0</field> + </register> + <register address="0x00000008" description="PLL reference and feedback registers" name="PLL_REF_FB"> + <field Type="RW" name="FSE_B" offset="0" width="1">0x0</field> + <field Type="RW" name="FBCK_SEL" offset="1" width="2">0x0</field> + <field Type="RW" name="FOUTFB_SELMUX_EN" offset="3" width="1">0x0</field> + <field Type="RSVD" name="RESERVE12" offset="4" width="4">0x0</field> + <field Type="RW" name="RFDIV" offset="8" width="6">0x5</field> + <field Type="RSVD" name="RESERVE13" offset="14" width="2">0x0</field> + <field Type="RSVD" name="RESERVE14" offset="16" width="12">0x0</field> + <field Type="RSVD" name="RESERVE15" offset="28" width="4">0x0</field> + </register> + <register address="0x0000000C" description="PLL fractional register" name="PLL_FRACN"> + <field Type="RW" name="FRACN_EN" offset="0" width="1">0x0</field> + <field Type="RW" name="FRACN_DAC_EN" offset="1" width="1">0x0</field> + <field Type="RSVD" name="RESERVE16" offset="2" width="6">0x0</field> + <field Type="RSVD" name="RESERVE17" offset="8" width="24">0x0</field> + </register> + <register address="0x00000010" description="PLL 0/1 division registers" name="PLL_DIV_0_1"> + <field Type="RO" name="VCO0PH_SEL" offset="0" width="3">0x0</field> + <field Type="RW" name="DIV0_START" offset="3" width="3">0x0</field> + <field Type="RSVD" name="RESERVE18" offset="6" width="2">0x0</field> + <field Type="RW" name="POST0DIV" offset="8" width="7">0x2</field> + <field Type="RSVD" name="RESERVE19" offset="15" width="1">0x0</field> + <field Type="RO" name="VCO1PH_SEL" offset="16" width="3">0x0</field> + <field Type="RW" name="DIV1_START" offset="19" width="3">0x0</field> + <field Type="RSVD" name="RESERVE20" offset="22" width="2">0x0</field> + <field Type="RW" name="POST1DIV" offset="24" width="7">0x1</field> + <field Type="RSVD" name="RESERVE21" offset="31" width="1">0x0</field> + </register> + <register address="0x00000014" description="PLL 2/3 division registers" name="PLL_DIV_2_3"> + <field Type="RO" name="VCO2PH_SEL" offset="0" width="3">0x0</field> + <field Type="RW" name="DIV2_START" offset="3" width="3">0x0</field> + <field Type="RSVD" name="RESERVE22" offset="6" width="2">0x0</field> + <field Type="RW" name="POST2DIV" offset="8" width="7">0x6</field> + <field Type="RSVD" name="RESERVE23" offset="15" width="1">0x0</field> + <field Type="RO" name="VCO3PH_SEL" offset="16" width="3">0x0</field> + <field Type="RW" name="DIV3_START" offset="19" width="3">0x0</field> + <field Type="RSVD" name="RESERVE24" offset="22" width="2">0x0</field> + <field Type="RW" name="POST3DIV" offset="24" width="7">0xF</field> + <field Type="RW" name="CKPOST3_SEL" offset="31" width="1">0x0</field> + </register> + <register address="0x00000018" description="PLL control register" name="PLL_CTRL2"> + <field Type="RW" name="BWI" offset="0" width="2">0x0</field> + <field Type="RW" name="BWP" offset="2" width="2">0x0</field> + <field Type="RW" name="IREF_EN" offset="4" width="1">0x0</field> + <field Type="RW" name="IREF_TOGGLE" offset="5" width="1">0x1</field> + <field Type="RSVD" name="RESERVE25" offset="6" width="3">0x0</field> + <field Type="RW" name="LOCKCNT" offset="9" width="4">0x8</field> + <field Type="RSVD" name="RESERVE26" offset="13" width="4">0x0</field> + <field Type="RW" name="ATEST_EN" offset="17" width="1">0x0</field> + <field Type="RW" name="ATEST_SEL" offset="18" width="3">0x0</field> + <field Type="RSVD" name="RESERVE27" offset="21" width="11">0x0</field> + </register> + <register address="0x0000001C" description="PLL calibration register" name="PLL_CAL"> + <field Type="RW" name="DSKEWCALCNT" offset="0" width="3">0x6</field> + <field Type="RW" name="DSKEWCAL_EN" offset="3" width="1">0x0</field> + <field Type="RW" name="DSKEWCALBYP" offset="4" width="1">0x0</field> + <field Type="RSVD" name="RESERVE28" offset="5" width="3">0x0</field> + <field Type="RW" name="DSKEWCALIN" offset="8" width="7">0xd</field> + <field Type="RSVD" name="RESERVE29" offset="15" width="1">0x0</field> + <field Type="RO" name="DSKEWCALOUT" offset="16" width="7">0x0</field> + <field Type="RSVD" name="RESERVE30" offset="23" width="9">0x0</field> + </register> + <register address="0x00000020" description="PLL phase registers" name="PLL_PHADJ"> + <field Type="RW" name="PLL_REG_SYNCREFDIV_EN" offset="0" width="1">0x1</field> + <field Type="RW" name="PLL_REG_ENABLE_SYNCREFDIV" offset="1" width="1">0x1</field> + <field Type="RW" name="REG_OUT0_PHSINIT" offset="2" width="3">0x0</field> + <field Type="RW" name="REG_OUT1_PHSINIT" offset="5" width="3">0x0</field> + <field Type="RW" name="REG_OUT2_PHSINIT" offset="8" width="3">0x0</field> + <field Type="RW" name="REG_OUT3_PHSINIT" offset="11" width="3">0x8</field> + <field Type="RW" name="REG_LOADPHS_B" offset="14" width="1">0x0</field> + <field Type="RSVD" name="RESERVE31" offset="15" width="17">0x0</field> + </register> + <register address="0x00000024" description="SSCG registers 0" name="SSCG_REG_0"> + <field Type="RW" name="DIVVAL" offset="0" width="6">0x0</field> + <field Type="RW" name="FRACIN" offset="6" width="24">0x0</field> + <field Type="RSVD" name="RESERVE00" offset="30" width="2">0x0</field> + </register> + <register address="0x00000028" description="SSCG registers 1" name="SSCG_REG_1"> + <field Type="RW" name="DOWNSPREAD" offset="0" width="1">0x0</field> + <field Type="RW" name="SSMD" offset="1" width="5">0x0</field> + <field Type="RO" name="FRACMOD" offset="6" width="24">0x0</field> + <field Type="RSVD" name="RESERVE01" offset="30" width="2">0x0</field> + </register> + <register address="0x0000002C" description="SSCG registers 2" name="SSCG_REG_2"> + <field Type="RW" name="INTIN" offset="0" width="12">0xC0</field> + <field Type="RO" name="INTMOD" offset="12" width="12">0x0</field> + <field Type="RSVD" name="RESERVE02" offset="24" width="8">0x0</field> + </register> + <register address="0x00000030" description="SSCG registers 3" name="SSCG_REG_3"> + <field Type="RW" name="SSE_B" offset="0" width="1">0x1</field> + <field Type="RW" name="SEL_EXTWAVE" offset="1" width="2">0x0</field> + <field Type="RW" name="EXT_MAXADDR" offset="3" width="8">0x0</field> + <field Type="RO" name="TBLADDR" offset="11" width="8">0x0</field> + <field Type="RW" name="RANDOM_FILTER" offset="19" width="1">0x0</field> + <field Type="RW" name="RANDOM_SEL" offset="20" width="2">0x0</field> + <field Type="RSVD" name="RESERVE03" offset="22" width="1">0x0</field> + <field Type="RSVD" name="RESERVE04" offset="23" width="9">0x0</field> + </register> + </registers> + </mss_pll> + <sgmii_pll> + <registers> + <register address="0x00000000" description="This is a compulsory register for all SCB slaves and must be at the same offset in all slaves to facilitate global soft reset of all SCB registers with a single broadcast write from the SCB master." name="SOFT_RESET"> + <field Type="RST" name="NV_MAP" offset="0" width="1">0x0</field> + <field Type="RST" name="V_MAP" offset="1" width="1">0x0</field> + <field Type="RST" name="PERIPH" offset="8" width="1">0x0</field> + <field Type="ID" name="BLOCKID" offset="16" width="16">0x0</field> + </register> + <register address="0x00000004" description="PLL control register" name="PLL_CTRL"> + <field Type="RW" name="REG_POWERDOWN_B" offset="0" width="1">0x1</field> + <field Type="RW" name="REG_RFDIV_EN" offset="1" width="1">0x1</field> + <field Type="RW" name="REG_DIVQ0_EN" offset="2" width="1">0x1</field> + <field Type="RW" name="REG_DIVQ1_EN" offset="3" width="1">0x1</field> + <field Type="RW" name="REG_DIVQ2_EN" offset="4" width="1">0x1</field> + <field Type="RW" name="REG_DIVQ3_EN" offset="5" width="1">0x1</field> + <field Type="RW" name="REG_RFCLK_SEL" offset="6" width="1">0x0</field> + <field Type="RW" name="RESETONLOCK" offset="7" width="1">0x0</field> + <field Type="RW" name="BYPCK_SEL" offset="8" width="4">0x0</field> + <field Type="RW" name="REG_BYPASS_GO_B" offset="12" width="1">0x0</field> + <field Type="RSVD" name="RESERVE10" offset="13" width="3">0x0</field> + <field Type="RW" name="REG_BYPASSPRE" offset="16" width="4">0x0</field> + <field Type="RW" name="REG_BYPASSPOST" offset="20" width="4">0x0</field> + <field Type="RW" name="LP_REQUIRES_LOCK" offset="24" width="1">0x1</field> + <field Type="RO" name="LOCK" offset="25" width="1">0x0</field> + <field Type="RW" name="LOCK_INT_EN" offset="26" width="1">0x0</field> + <field Type="RW" name="UNLOCK_INT_EN" offset="27" width="1">0x0</field> + <field Type="SW1C" name="LOCK_INT" offset="28" width="1">0x0</field> + <field Type="SW1C" name="UNLOCK_INT" offset="29" width="1">0x0</field> + <field Type="RSVD" name="RESERVE11" offset="30" width="1">0x0</field> + <field Type="RO" name="LOCK_B" offset="31" width="1">0x0</field> + </register> + <register address="0x00000008" description="PLL reference and feedback registers" name="PLL_REF_FB"> + <field Type="RW" name="FSE_B" offset="0" width="1">0x0</field> + <field Type="RW" name="FBCK_SEL" offset="1" width="2">0x0</field> + <field Type="RW" name="FOUTFB_SELMUX_EN" offset="3" width="1">0x0</field> + <field Type="RSVD" name="RESERVE12" offset="4" width="4">0x0</field> + <field Type="RW" name="RFDIV" offset="8" width="6">0x1</field> + <field Type="RSVD" name="RESERVE13" offset="14" width="2">0x0</field> + <field Type="RSVD" name="RESERVE14" offset="16" width="12">0x0</field> + <field Type="RSVD" name="RESERVE15" offset="28" width="4">0x0</field> + </register> + <register address="0x0000000C" description="PLL fractional register" name="PLL_FRACN"> + <field Type="RW" name="FRACN_EN" offset="0" width="1">0x0</field> + <field Type="RW" name="FRACN_DAC_EN" offset="1" width="1">0x0</field> + <field Type="RSVD" name="RESERVE16" offset="2" width="6">0x0</field> + <field Type="RSVD" name="RESERVE17" offset="8" width="24">0x0</field> + </register> + <register address="0x00000010" description="PLL 0/1 division registers" name="PLL_DIV_0_1"> + <field Type="RO" name="VCO0PH_SEL" offset="0" width="3">0x0</field> + <field Type="RW" name="DIV0_START" offset="3" width="3">0x0</field> + <field Type="RSVD" name="RESERVE18" offset="6" width="2">0x0</field> + <field Type="RW" name="POST0DIV" offset="8" width="7">0x1</field> + <field Type="RSVD" name="RESERVE19" offset="15" width="1">0x0</field> + <field Type="RO" name="VCO1PH_SEL" offset="16" width="3">0x0</field> + <field Type="RW" name="DIV1_START" offset="19" width="3">0x0</field> + <field Type="RSVD" name="RESERVE20" offset="22" width="2">0x0</field> + <field Type="RW" name="POST1DIV" offset="24" width="7">0x1</field> + <field Type="RSVD" name="RESERVE21" offset="31" width="1">0x0</field> + </register> + <register address="0x00000014" description="PLL 2/3 division registers" name="PLL_DIV_2_3"> + <field Type="RO" name="VCO2PH_SEL" offset="0" width="3">0x0</field> + <field Type="RW" name="DIV2_START" offset="3" width="3">0x0</field> + <field Type="RSVD" name="RESERVE22" offset="6" width="2">0x0</field> + <field Type="RW" name="POST2DIV" offset="8" width="7">0x1</field> + <field Type="RSVD" name="RESERVE23" offset="15" width="1">0x0</field> + <field Type="RO" name="VCO3PH_SEL" offset="16" width="3">0x0</field> + <field Type="RW" name="DIV3_START" offset="19" width="3">0x0</field> + <field Type="RSVD" name="RESERVE24" offset="22" width="2">0x0</field> + <field Type="RW" name="POST3DIV" offset="24" width="7">0x1</field> + <field Type="RW" name="CKPOST3_SEL" offset="31" width="1">0x0</field> + </register> + <register address="0x00000018" description="PLL control register" name="PLL_CTRL2"> + <field Type="RW" name="BWI" offset="0" width="2">0x0</field> + <field Type="RW" name="BWP" offset="2" width="2">0x0</field> + <field Type="RW" name="IREF_EN" offset="4" width="1">0x0</field> + <field Type="RW" name="IREF_TOGGLE" offset="5" width="1">0x1</field> + <field Type="RSVD" name="RESERVE25" offset="6" width="3">0x0</field> + <field Type="RW" name="LOCKCNT" offset="9" width="4">0x8</field> + <field Type="RSVD" name="RESERVE26" offset="13" width="4">0x0</field> + <field Type="RW" name="ATEST_EN" offset="17" width="1">0x0</field> + <field Type="RW" name="ATEST_SEL" offset="18" width="3">0x0</field> + <field Type="RSVD" name="RESERVE27" offset="21" width="11">0x0</field> + </register> + <register address="0x0000001C" description="PLL calibration register" name="PLL_CAL"> + <field Type="RW" name="DSKEWCALCNT" offset="0" width="3">0x6</field> + <field Type="RW" name="DSKEWCAL_EN" offset="3" width="1">0x0</field> + <field Type="RW" name="DSKEWCALBYP" offset="4" width="1">0x0</field> + <field Type="RSVD" name="RESERVE28" offset="5" width="3">0x0</field> + <field Type="RW" name="DSKEWCALIN" offset="8" width="7">0xd</field> + <field Type="RSVD" name="RESERVE29" offset="15" width="1">0x0</field> + <field Type="RO" name="DSKEWCALOUT" offset="16" width="7">0x0</field> + <field Type="RSVD" name="RESERVE30" offset="23" width="9">0x0</field> + </register> + <register address="0x00000020" description="PLL phase registers" name="PLL_PHADJ"> + <field Type="RW" name="PLL_REG_SYNCREFDIV_EN" offset="0" width="1">0x1</field> + <field Type="RW" name="PLL_REG_ENABLE_SYNCREFDIV" offset="1" width="1">0x1</field> + <field Type="RW" name="REG_OUT0_PHSINIT" offset="2" width="3">0x0</field> + <field Type="RW" name="REG_OUT1_PHSINIT" offset="5" width="3">0x2</field> + <field Type="RW" name="REG_OUT2_PHSINIT" offset="8" width="3">0x4</field> + <field Type="RW" name="REG_OUT3_PHSINIT" offset="11" width="3">0x6</field> + <field Type="RW" name="REG_LOADPHS_B" offset="14" width="1">0x1</field> + <field Type="RSVD" name="RESERVE31" offset="15" width="17">0x0</field> + </register> + <register address="0x00000024" description="SSCG registers 0" name="SSCG_REG_0"> + <field Type="RW" name="DIVVAL" offset="0" width="6">0x0</field> + <field Type="RW" name="FRACIN" offset="6" width="24">0x0</field> + <field Type="RSVD" name="RESERVE00" offset="30" width="2">0x0</field> + </register> + <register address="0x00000028" description="SSCG registers 1" name="SSCG_REG_1"> + <field Type="RW" name="DOWNSPREAD" offset="0" width="1">0x0</field> + <field Type="RW" name="SSMD" offset="1" width="5">0x0</field> + <field Type="RO" name="FRACMOD" offset="6" width="24">0x0</field> + <field Type="RSVD" name="RESERVE01" offset="30" width="2">0x0</field> + </register> + <register address="0x0000002C" description="SSCG registers 2" name="SSCG_REG_2"> + <field Type="RW" name="INTIN" offset="0" width="12">0x14</field> + <field Type="RO" name="INTMOD" offset="12" width="12">0x0</field> + <field Type="RSVD" name="RESERVE02" offset="24" width="8">0x0</field> + </register> + <register address="0x00000030" description="SSCG registers 3" name="SSCG_REG_3"> + <field Type="RW" name="SSE_B" offset="0" width="1">0x1</field> + <field Type="RW" name="SEL_EXTWAVE" offset="1" width="2">0x0</field> + <field Type="RW" name="EXT_MAXADDR" offset="3" width="8">0x0</field> + <field Type="RO" name="TBLADDR" offset="11" width="8">0x0</field> + <field Type="RW" name="RANDOM_FILTER" offset="19" width="1">0x0</field> + <field Type="RW" name="RANDOM_SEL" offset="20" width="2">0x0</field> + <field Type="RSVD" name="RESERVE03" offset="22" width="1">0x0</field> + <field Type="RSVD" name="RESERVE04" offset="23" width="9">0x0</field> + </register> + </registers> + </sgmii_pll> + <ddr_pll> + <registers> + <register address="0x00000000" description="This is a compulsory register for all SCB slaves and must be at the same offset in all slaves to facilitate global soft reset of all SCB registers with a single broadcast write from the SCB master." name="SOFT_RESET"> + <field Type="RST" name="NV_MAP" offset="0" width="1">DDR3</field> + <field Type="RST" name="V_MAP" offset="1" width="1">0x0</field> + <field Type="RST" name="PERIPH" offset="8" width="1">0x0</field> + <field Type="ID" name="BLOCKID" offset="16" width="16">0x0</field> + </register> + <register address="0x00000004" description="PLL control register" name="PLL_CTRL"> + <field Type="RW" name="REG_POWERDOWN_B" offset="0" width="1">0x1</field> + <field Type="RW" name="REG_RFDIV_EN" offset="1" width="1">0x1</field> + <field Type="RW" name="REG_DIVQ0_EN" offset="2" width="1">0x1</field> + <field Type="RW" name="REG_DIVQ1_EN" offset="3" width="1">0x1</field> + <field Type="RW" name="REG_DIVQ2_EN" offset="4" width="1">0x1</field> + <field Type="RW" name="REG_DIVQ3_EN" offset="5" width="1">0x1</field> + <field Type="RW" name="REG_RFCLK_SEL" offset="6" width="1">0x0</field> + <field Type="RW" name="RESETONLOCK" offset="7" width="1">0x0</field> + <field Type="RW" name="BYPCK_SEL" offset="8" width="4">0x0</field> + <field Type="RW" name="REG_BYPASS_GO_B" offset="12" width="1">0x0</field> + <field Type="RSVD" name="RESERVE10" offset="13" width="3">0x0</field> + <field Type="RW" name="REG_BYPASSPRE" offset="16" width="4">0x0</field> + <field Type="RW" name="REG_BYPASSPOST" offset="20" width="4">0x0</field> + <field Type="RW" name="LP_REQUIRES_LOCK" offset="24" width="1">0x1</field> + <field Type="RO" name="LOCK" offset="25" width="1">0x0</field> + <field Type="RW" name="LOCK_INT_EN" offset="26" width="1">0x0</field> + <field Type="RW" name="UNLOCK_INT_EN" offset="27" width="1">0x0</field> + <field Type="SW1C" name="LOCK_INT" offset="28" width="1">0x0</field> + <field Type="SW1C" name="UNLOCK_INT" offset="29" width="1">0x0</field> + <field Type="RSVD" name="RESERVE11" offset="30" width="1">0x0</field> + <field Type="RO" name="LOCK_B" offset="31" width="1">0x0</field> + </register> + <register address="0x00000008" description="PLL reference and feedback registers" name="PLL_REF_FB"> + <field Type="RW" name="FSE_B" offset="0" width="1">0x0</field> + <field Type="RW" name="FBCK_SEL" offset="1" width="2">0x0</field> + <field Type="RW" name="FOUTFB_SELMUX_EN" offset="3" width="1">0x0</field> + <field Type="RSVD" name="RESERVE12" offset="4" width="4">0x0</field> + <field Type="RW" name="RFDIV" offset="8" width="6">0x5</field> + <field Type="RSVD" name="RESERVE13" offset="14" width="2">0x0</field> + <field Type="RSVD" name="RESERVE14" offset="16" width="12">0x0</field> + <field Type="RSVD" name="RESERVE15" offset="28" width="4">0x0</field> + </register> + <register address="0x0000000C" description="PLL fractional register" name="PLL_FRACN"> + <field Type="RW" name="FRACN_EN" offset="0" width="1">0x0</field> + <field Type="RW" name="FRACN_DAC_EN" offset="1" width="1">0x0</field> + <field Type="RSVD" name="RESERVE16" offset="2" width="6">0x0</field> + <field Type="RSVD" name="RESERVE17" offset="8" width="24">0x0</field> + </register> + <register address="0x00000010" description="PLL 0/1 division registers" name="PLL_DIV_0_1"> + <field Type="RO" name="VCO0PH_SEL" offset="0" width="3">0x0</field> + <field Type="RW" name="DIV0_START" offset="3" width="3">0x0</field> + <field Type="RSVD" name="RESERVE18" offset="6" width="2">0x0</field> + <field Type="RW" name="POST0DIV" offset="8" width="7">0x1</field> + <field Type="RSVD" name="RESERVE19" offset="15" width="1">0x0</field> + <field Type="RO" name="VCO1PH_SEL" offset="16" width="3">0x0</field> + <field Type="RW" name="DIV1_START" offset="19" width="3">0x0</field> + <field Type="RSVD" name="RESERVE20" offset="22" width="2">0x0</field> + <field Type="RW" name="POST1DIV" offset="24" width="7">0x2</field> + <field Type="RSVD" name="RESERVE21" offset="31" width="1">0x0</field> + </register> + <register address="0x00000014" description="PLL 2/3 division registers" name="PLL_DIV_2_3"> + <field Type="RO" name="VCO2PH_SEL" offset="0" width="3">0x0</field> + <field Type="RW" name="DIV2_START" offset="3" width="3">0x0</field> + <field Type="RSVD" name="RESERVE22" offset="6" width="2">0x0</field> + <field Type="RW" name="POST2DIV" offset="8" width="7">0x1</field> + <field Type="RSVD" name="RESERVE23" offset="15" width="1">0x0</field> + <field Type="RO" name="VCO3PH_SEL" offset="16" width="3">0x0</field> + <field Type="RW" name="DIV3_START" offset="19" width="3">0x0</field> + <field Type="RSVD" name="RESERVE24" offset="22" width="2">0x0</field> + <field Type="RW" name="POST3DIV" offset="24" width="7">0x1</field> + <field Type="RW" name="CKPOST3_SEL" offset="31" width="1">0x0</field> + </register> + <register address="0x00000018" description="PLL control register" name="PLL_CTRL2"> + <field Type="RW" name="BWI" offset="0" width="2">0x0</field> + <field Type="RW" name="BWP" offset="2" width="2">0x0</field> + <field Type="RW" name="IREF_EN" offset="4" width="1">0x0</field> + <field Type="RW" name="IREF_TOGGLE" offset="5" width="1">0x1</field> + <field Type="RSVD" name="RESERVE25" offset="6" width="3">0x0</field> + <field Type="RW" name="LOCKCNT" offset="9" width="4">0x8</field> + <field Type="RSVD" name="RESERVE26" offset="13" width="4">0x0</field> + <field Type="RW" name="ATEST_EN" offset="17" width="1">0x0</field> + <field Type="RW" name="ATEST_SEL" offset="18" width="3">0x0</field> + <field Type="RSVD" name="RESERVE27" offset="21" width="11">0x0</field> + </register> + <register address="0x0000001C" description="PLL calibration register" name="PLL_CAL"> + <field Type="RW" name="DSKEWCALCNT" offset="0" width="3">0x6</field> + <field Type="RW" name="DSKEWCAL_EN" offset="3" width="1">0x0</field> + <field Type="RW" name="DSKEWCALBYP" offset="4" width="1">0x0</field> + <field Type="RSVD" name="RESERVE28" offset="5" width="3">0x0</field> + <field Type="RW" name="DSKEWCALIN" offset="8" width="7">0xd</field> + <field Type="RSVD" name="RESERVE29" offset="15" width="1">0x0</field> + <field Type="RO" name="DSKEWCALOUT" offset="16" width="7">0x0</field> + <field Type="RSVD" name="RESERVE30" offset="23" width="9">0x0</field> + </register> + <register address="0x00000020" description="PLL phase registers" name="PLL_PHADJ"> + <field Type="RW" name="PLL_REG_SYNCREFDIV_EN" offset="0" width="1">0x1</field> + <field Type="RW" name="PLL_REG_ENABLE_SYNCREFDIV" offset="1" width="1">0x1</field> + <field Type="RW" name="REG_OUT0_PHSINIT" offset="2" width="3">0x0</field> + <field Type="RW" name="REG_OUT1_PHSINIT" offset="5" width="3">0x0</field> + <field Type="RW" name="REG_OUT2_PHSINIT" offset="8" width="3">0x0</field> + <field Type="RW" name="REG_OUT3_PHSINIT" offset="11" width="3">0x2</field> + <field Type="RW" name="REG_LOADPHS_B" offset="14" width="1">0x1</field> + <field Type="RSVD" name="RESERVE31" offset="15" width="17">0x0</field> + </register> + <register address="0x00000024" description="SSCG registers 0" name="SSCG_REG_0"> + <field Type="RW" name="DIVVAL" offset="0" width="6">0x0</field> + <field Type="RW" name="FRACIN" offset="6" width="24">0x0</field> + <field Type="RSVD" name="RESERVE00" offset="30" width="2">0x0</field> + </register> + <register address="0x00000028" description="SSCG registers 1" name="SSCG_REG_1"> + <field Type="RW" name="DOWNSPREAD" offset="0" width="1">0x0</field> + <field Type="RW" name="SSMD" offset="1" width="5">0x0</field> + <field Type="RO" name="FRACMOD" offset="6" width="24">0x0</field> + <field Type="RSVD" name="RESERVE01" offset="30" width="2">0x0</field> + </register> + <register address="0x0000002C" description="SSCG registers 2" name="SSCG_REG_2"> + <field Type="RW" name="INTIN" offset="0" width="12">0x80</field> + <field Type="RO" name="INTMOD" offset="12" width="12">0x0</field> + <field Type="RSVD" name="RESERVE02" offset="24" width="8">0x0</field> + </register> + <register address="0x00000030" description="SSCG registers 3" name="SSCG_REG_3"> + <field Type="RW" name="SSE_B" offset="0" width="1">0x1</field> + <field Type="RW" name="SEL_EXTWAVE" offset="1" width="2">0x0</field> + <field Type="RW" name="EXT_MAXADDR" offset="3" width="8">0x0</field> + <field Type="RO" name="TBLADDR" offset="11" width="8">0x0</field> + <field Type="RW" name="RANDOM_FILTER" offset="19" width="1">0x0</field> + <field Type="RW" name="RANDOM_SEL" offset="20" width="2">0x0</field> + <field Type="RSVD" name="RESERVE03" offset="22" width="1">0x0</field> + <field Type="RSVD" name="RESERVE04" offset="23" width="9">0x0</field> + </register> + </registers> + </ddr_pll> + <mss_cfm> + <registers> + <register address="0x00000004" description="Input mux selections" name="BCLKMUX"> + <field Type="RW" name="BCLK0_SEL" offset="0" width="5">0x8</field> + <field Type="RW" name="BCLK1_SEL" offset="5" width="5">0x10</field> + <field Type="RW" name="BCLK2_SEL" offset="10" width="5">0x0</field> + <field Type="RW" name="BCLK3_SEL" offset="15" width="5">0x0</field> + <field Type="RW" name="BCLK4_SEL" offset="20" width="5">0x0</field> + <field Type="RW" name="BCLK5_SEL" offset="25" width="5">0x0</field> + <field Type="RW" name="RESERVED" offset="30" width="2">0x0</field> + </register> + <register address="0x00000008" description="Input mux selections" name="PLL_CKMUX"> + <field Type="RW" name="CLK_IN_MAC_TSU_SEL" offset="0" width="2">0x1</field> + <field Type="RW" name="PLL0_RFCLK0_SEL" offset="2" width="2">0x1</field> + <field Type="RW" name="PLL0_RFCLK1_SEL" offset="4" width="2">0x1</field> + <field Type="RW" name="PLL1_RFCLK0_SEL" offset="6" width="2">0x1</field> + <field Type="RW" name="PLL1_RFCLK1_SEL" offset="8" width="2">0x1</field> + <field Type="RW" name="PLL1_FDR_SEL" offset="10" width="5">0x0</field> + <field Type="RW" name="RESERVED" offset="15" width="17">0x0</field> + </register> + <register address="0x0000000C" description="MSS Clock mux selections" name="MSSCLKMUX"> + <field Type="RW" name="MSSCLK_MUX_SEL" offset="0" width="2">0x3</field> + <field Type="RW" name="MSSCLK_MUX_MD" offset="2" width="2">0x0</field> + <field Type="RW" name="CLK_STANDBY_SEL" offset="4" width="1">0x0</field> + <field Type="RW" name="RESERVED" offset="5" width="27">0x0</field> + </register> + <register address="0x00000010" description="spare logic " name="SPARE0"> + <field Type="RW" name="SPARE0" offset="0" width="32">0x0</field> + </register> + <register address="0x00000014" description="Frequency_meter_address_selections" name="FMETER_ADDR"> + <field Type="RSVD" name="ADDR10" offset="0" width="2">0x0</field> + <field Type="RW" name="ADDR" offset="2" width="4">0x0</field> + <field Type="RSVD" name="RESERVE18" offset="6" width="26">0x0</field> + </register> + <register address="0x00000018" description="Frequency_meter_data_write" name="FMETER_DATAW"> + <field Type="RW" name="DATA" offset="0" width="24">0x0</field> + <field Type="W1P" name="STROBE" offset="24" width="1">0x0</field> + <field Type="RSVD" name="RESERVE19" offset="25" width="7">0x0</field> + </register> + <register address="0x0000001C" description="Frequency_meter_data_read" name="FMETER_DATAR"> + <field Type="RO" name="DATA" offset="0" width="24">0x0</field> + <field Type="RSVD" name="RESERVE20" offset="24" width="8">0x0</field> + </register> + <register address="0x0000001E" description="Imirror TRIM Bits" name="IMIRROR_TRIM"> + <field Type="RW" name="BG_CODE" offset="0" width="3">0x0</field> + <field Type="RW" name="CC_CODE" offset="3" width="8">0x0</field> + <field Type="RSVD" name="RESERVE21" offset="11" width="21">0x0</field> + </register> + <register address="0x00000020" description="Test MUX Controls" name="TEST_CTRL"> + <field Type="RW" name="OSC_ENABLE" offset="0" width="4">0x0</field> + <field Type="RW" name="ATEST_EN" offset="4" width="1">0x0</field> + <field Type="RW" name="ATEST_SEL" offset="5" width="5">0x0</field> + <field Type="RW" name="DTEST_EN" offset="10" width="1">0x0</field> + <field Type="RW" name="DTEST_SEL" offset="11" width="5">0x0</field> + <field Type="RSVD" name="RESERVE22" offset="16" width="16">0x0</field> + </register> + </registers> + </mss_cfm> + <sgmii_cfm> + <registers> + <register address="0x00000004" description="Input mux selections" name="REFCLKMUX"> + <field Type="RW" name="PLL0_RFCLK0_SEL" offset="0" width="2">0x1</field> + <field Type="RW" name="PLL0_RFCLK1_SEL" offset="2" width="2">0x1</field> + <field Type="RW" name="RESERVED" offset="4" width="28">0x0</field> + </register> + <register address="0x00000008" description="sgmii clk mux" name="SGMII_CLKMUX"> + <field Type="RW" name="SGMII_CLKMUX" offset="0" width="32">0x5</field> + </register> + <register address="0x0000000C" description="spare logic" name="SPARE0"> + <field Type="RW" name="RESERVED" offset="0" width="32">0x0</field> + </register> + <register address="0x00000010" description="Clock_Receiver " name="CLK_XCVR"> + <field Type="RW" name="EN_UDRIVE_P" offset="0" width="1">0x0</field> + <field Type="RW" name="EN_INS_HYST_P" offset="1" width="1">0x0</field> + <field Type="RW" name="EN_TERM_P" offset="2" width="2">0x0</field> + <field Type="RW" name="EN_RXMODE_P" offset="4" width="2">0x3</field> + <field Type="RW" name="EN_UDRIVE_N" offset="6" width="1">0x0</field> + <field Type="RW" name="EN_INS_HYST_N" offset="7" width="1">0x0</field> + <field Type="RW" name="EN_TERM_N" offset="8" width="2">0x0</field> + <field Type="RW" name="EN_RXMODE_N" offset="10" width="2">0x3</field> + <field Type="RW" name="CLKBUF_EN_PULLUP" offset="12" width="1">0x0</field> + <field Type="RW" name="EN_RDIFF" offset="13" width="1">0x1</field> + <field Type="RW" name="RESERVED" offset="14" width="18">0x0</field> + </register> + <register address="0x00000014" description="Test MUX Controls" name="TEST_CTRL"> + <field Type="RW" name="OSC_ENABLE" offset="0" width="4">0x0</field> + <field Type="RW" name="ATEST_EN" offset="4" width="1">0x0</field> + <field Type="RW" name="ATEST_SEL" offset="5" width="5">0x0</field> + <field Type="RW" name="DTEST_EN" offset="10" width="1">0x0</field> + <field Type="RW" name="DTEST_SEL" offset="11" width="5">0x0</field> + <field Type="RSVD" name="RESERVE22" offset="16" width="16">0x0</field> + </register> + </registers> + </sgmii_cfm> + </mss_clocks> + <mss_general> + <mss_peripherals> + <registers> + <register address="0x0000009C" description="GPIO Blocks reset control- (soft_reset options chossen in Libero confgurator)" name="GPIO_CR"> + <field Type="RW" name="GPIO0_SOFT_RESET_SELECT" offset="0" width="2">0x3</field> + <field Type="RW" name="GPIO0_DEFAULT" offset="4" width="2">0x0</field> + <field Type="RW" name="GPIO1_SOFT_RESET_SELECT" offset="8" width="3">0x7</field> + <field Type="RW" name="GPIO1_DEFAULT" offset="12" width="3">0x0</field> + <field Type="RW" name="GPIO2_SOFT_RESET_SELECT" offset="16" width="4">0xF</field> + <field Type="RW" name="GPIO2_DEFAULT" offset="20" width="4">0x0</field> + </register> + <register address="0x00000000" description="Information on how Crypto setup on this MPFS " name="CRYPTO_CR_INFO"> + <field Type="RO" name="MSS_MODE" offset="0" width="2">0x0</field> + <field Type="RO" name="RESERVED" offset="2" width="1">0x0</field> + <field Type="RO" name="STREAM_ENABLE" offset="3" width="1">0x0</field> + <field Type="RO" name="RESERVED1" offset="4" width="28">0x0</field> + </register> + </registers> + </mss_peripherals> + </mss_general> + </mss> |