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diff --git a/FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/platform/mpfs_hal/common/atomic.h b/FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/platform/mpfs_hal/common/atomic.h
new file mode 100644
index 000000000..48110f007
--- /dev/null
+++ b/FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/platform/mpfs_hal/common/atomic.h
@@ -0,0 +1,62 @@
+/*
+    Copyright (c) 2013, The Regents of the University of California (Regents).
+    All Rights Reserved.
+
+    Redistribution and use in source and binary forms, with or without
+    modification, are permitted provided that the following conditions are met:
+    1. Redistributions of source code must retain the above copyright
+       notice, this list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright
+       notice, this list of conditions and the following disclaimer in the
+       documentation and/or other materials provided with the distribution.
+    3. Neither the name of the Regents nor the
+       names of its contributors may be used to endorse or promote products
+       derived from this software without specific prior written permission.
+
+    IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
+    SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
+    OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS
+    BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+    REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+    THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+    PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
+    HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
+    MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
+*/
+
+/***********************************************************************************
+ * Record of Microchip changes
+ */
+
+#ifndef RISCV_ATOMIC_H
+#define RISCV_ATOMIC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define mb() asm volatile ("fence" ::: "memory")
+#define atomic_set(ptr, val) (*(volatile typeof(*(ptr)) *)(ptr) = val)
+#define atomic_read(ptr) (*(volatile typeof(*(ptr)) *)(ptr))
+
+#ifdef __riscv_atomic
+# define atomic_swap(ptr, swp) __sync_lock_test_and_set(ptr, swp)
+# define atomic_or(ptr, inc) __sync_fetch_and_or(ptr, inc)
+#else
+#define atomic_binop(ptr, inc, op) ({ \
+  long flags = disable_irqsave(); \
+  typeof(*(ptr)) res = atomic_read(ptr); \
+  atomic_set(ptr, op); \
+  enable_irqrestore(flags); \
+  res; })
+#define atomic_or(ptr, inc) atomic_binop(ptr, inc, res | (inc))
+#define atomic_swap(ptr, swp) atomic_binop(ptr, swp, (swp))
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  //RISCV_ATOMIC_H
+