From 3fcb9a5ad001bb6558e17e82fec7936ad249b6cb Mon Sep 17 00:00:00 2001 From: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com> Date: Fri, 28 Apr 2023 13:01:57 +0530 Subject: Add IAR projects for LPC55S69 (#1007) * Add IAR projects for LPC55S69 * IAR Project for trustzone * MCUXpresso and IAR projects for non-trustzone (NTZ) ports Signed-off-by: Gaurav Aggarwal * Fix build issues and warnings Signed-off-by: Gaurav Aggarwal * Fix formatting check Signed-off-by: Gaurav Aggarwal --------- Signed-off-by: Gaurav Aggarwal --- .../.gitignore | 5 +- .../NSC_Functions/nsc_printf.c | 78 + .../NSC_Functions/nsc_printf.h | 37 + .../NXP_Code/CMSIS/cmsis_iccarm.h | 1002 ++ .../NXP_Code/startup/startup_LPC55S69_cm33_core0.s | 635 + .../NXP_Code/trustzone/tzm_config.c | 272 + .../NXP_Code/trustzone/tzm_config.h | 18 + .../Projects/IAR/Config/FreeRTOSConfig.h | 169 + .../Projects/IAR/FreeRTOSDemo.eww | 22 + .../IAR/NonSecure/FreeRTOSDemo_flash_ns.icf | 144 + .../Projects/IAR/NonSecure/FreeRTOSDemo_ns.ewd | 12342 +++++++++++++++++++ .../Projects/IAR/NonSecure/FreeRTOSDemo_ns.ewp | 1422 +++ .../Projects/IAR/NonSecure/fault_handler.s | 42 + .../Projects/IAR/Secure/FreeRTOSDemo_flash_s.icf | 122 + .../Projects/IAR/Secure/FreeRTOSDemo_s.ewd | 1554 +++ .../Projects/IAR/Secure/FreeRTOSDemo_s.ewp | 1340 ++ .../Projects/MCUXpresso/Config/FreeRTOSConfig.h | 128 +- .../Projects/MCUXpresso/NonSecure/.cproject | 2 + .../Projects/MCUXpresso/NonSecure/.project | 33 +- .../.settings/org.eclipse.core.resources.prefs | 2 + .../Projects/MCUXpresso/NonSecure/fault_handler.c | 50 + .../Projects/MCUXpresso/NonSecure/main_ns.c | 198 - .../Projects/MCUXpresso/NonSecure/reg_tests.c | 446 - .../Projects/MCUXpresso/NonSecure/reg_tests.h | 35 - .../Projects/MCUXpresso/Secure/.cproject | 11 +- .../Projects/MCUXpresso/Secure/.project | 25 +- .../.settings/org.eclipse.core.resources.prefs | 2 + .../Projects/MCUXpresso/Secure/main_s.c | 131 - .../Projects/MCUXpresso/Secure/nsc_printf.c | 78 - .../Projects/MCUXpresso/Secure/nsc_printf.h | 37 - .../Projects/MCUXpresso/Secure/tzm_config.c | 272 - .../Projects/MCUXpresso/Secure/tzm_config.h | 18 - .../Projects_NTZ/IAR/Config/FreeRTOSConfig.h | 170 + .../Projects_NTZ/IAR/FreeRTOSDemo.ewd | 1554 +++ .../Projects_NTZ/IAR/FreeRTOSDemo.ewp | 1355 ++ .../Projects_NTZ/IAR/FreeRTOSDemo.eww | 15 + .../Projects_NTZ/IAR/FreeRTOSDemo_flash.icf | 144 + .../Projects_NTZ/IAR/fault_handler.s | 42 + .../Projects_NTZ/MCUXpresso/.cproject | 398 + .../Projects_NTZ/MCUXpresso/.project | 221 + .../.settings/org.eclipse.core.resources.prefs | 2 + .../MCUXpresso/Config/FreeRTOSConfig.h | 168 + .../MCUXpresso/FaultHandler/fault_handler.c | 50 + .../Projects_NTZ/MCUXpresso/FreeRTOSDemo.ld | 213 + .../RegTests/reg_tests.c | 486 + .../RegTests/reg_tests.h | 35 + .../User/NTZ/main.c | 161 + .../User/NonSecure/main_ns.c | 173 + .../User/Secure/main_s.c | 131 + FreeRTOS/Demo/Common/ARMv8M/mpu_demo/mpu_demo.c | 46 +- .../IAR/ARM_CM33/non_secure/reg_test_asm.h | 48 + .../IAR/ARM_CM33/non_secure/reg_test_asm.s | 1194 ++ .../IAR/ARM_CM33/secure/secure_reg_test.c | 61 + .../IAR/ARM_CM33/secure/secure_reg_test_asm.h | 49 + .../IAR/ARM_CM33/secure/secure_reg_test_asm.s | 265 + 55 files changed, 26322 insertions(+), 1331 deletions(-) create mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NSC_Functions/nsc_printf.c create mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NSC_Functions/nsc_printf.h create mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_iccarm.h create mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/startup/startup_LPC55S69_cm33_core0.s create mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/trustzone/tzm_config.c create mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/trustzone/tzm_config.h create mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/Config/FreeRTOSConfig.h create mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/FreeRTOSDemo.eww create mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/NonSecure/FreeRTOSDemo_flash_ns.icf create mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/NonSecure/FreeRTOSDemo_ns.ewd create mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/NonSecure/FreeRTOSDemo_ns.ewp create mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/NonSecure/fault_handler.s create mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/Secure/FreeRTOSDemo_flash_s.icf create mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/Secure/FreeRTOSDemo_s.ewd create mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/Secure/FreeRTOSDemo_s.ewp create mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/.settings/org.eclipse.core.resources.prefs create mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/fault_handler.c delete mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/main_ns.c delete mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/reg_tests.c delete mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/reg_tests.h create mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/.settings/org.eclipse.core.resources.prefs delete mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/main_s.c delete mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/nsc_printf.c delete mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/nsc_printf.h delete mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/tzm_config.c delete mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Secure/tzm_config.h create mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/IAR/Config/FreeRTOSConfig.h create mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/IAR/FreeRTOSDemo.ewd create mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/IAR/FreeRTOSDemo.ewp create mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/IAR/FreeRTOSDemo.eww create mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/IAR/FreeRTOSDemo_flash.icf create mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/IAR/fault_handler.s create mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/MCUXpresso/.cproject create mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/MCUXpresso/.project create mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/MCUXpresso/.settings/org.eclipse.core.resources.prefs create mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/MCUXpresso/Config/FreeRTOSConfig.h create mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/MCUXpresso/FaultHandler/fault_handler.c create mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects_NTZ/MCUXpresso/FreeRTOSDemo.ld create mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/RegTests/reg_tests.c create mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/RegTests/reg_tests.h create mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/User/NTZ/main.c create mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/User/NonSecure/main_ns.c create mode 100644 FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/User/Secure/main_s.c create mode 100644 FreeRTOS/Demo/Common/ARMv8M/reg_tests/IAR/ARM_CM33/non_secure/reg_test_asm.h create mode 100644 FreeRTOS/Demo/Common/ARMv8M/reg_tests/IAR/ARM_CM33/non_secure/reg_test_asm.s create mode 100644 FreeRTOS/Demo/Common/ARMv8M/reg_tests/IAR/ARM_CM33/secure/secure_reg_test.c create mode 100644 FreeRTOS/Demo/Common/ARMv8M/reg_tests/IAR/ARM_CM33/secure/secure_reg_test_asm.h create mode 100644 FreeRTOS/Demo/Common/ARMv8M/reg_tests/IAR/ARM_CM33/secure/secure_reg_test_asm.s diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/.gitignore b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/.gitignore index 242758392..38a973882 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/.gitignore +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/.gitignore @@ -1,6 +1,9 @@ # IDE autogenerated files. -.settings/ +*.settings.xml *.launch +settings/ +*.ewt +*.dep # Build Artifacts Debug/ \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NSC_Functions/nsc_printf.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NSC_Functions/nsc_printf.c new file mode 100644 index 000000000..d3d04719f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NSC_Functions/nsc_printf.c @@ -0,0 +1,78 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* ARM includes. */ +#include + +/* Interface includes. */ +#include "nsc_printf.h" + +/* FreeRTOS includes. */ +#include "secure_port_macros.h" + +/* Device includes. */ +#include "fsl_debug_console.h" +/*-----------------------------------------------------------*/ + +/* Maximum length of the string that the non-secure code + * can print. */ +#define MAX_ALLOWED_STRING_LENGTH 0x400 +/*-----------------------------------------------------------*/ + +secureportNON_SECURE_CALLABLE void NSC_Printf( char const *str ) +{ + uint32_t isInvalidSting = 0; + size_t stringLength; + + /* Check whether the string is null terminated. */ + stringLength = strnlen( str, MAX_ALLOWED_STRING_LENGTH ); + + if( ( stringLength == MAX_ALLOWED_STRING_LENGTH ) && + ( str[ stringLength ] != '\0') ) + { + PRINTF( "[ERROR] [NSC_Printf] String too long or not null terminated!\r\n" ); + isInvalidSting = 1; + } + + if( isInvalidSting == 0 ) + { + /* Check whether the string is located in non-secure memory. */ + if( cmse_check_address_range( ( void * ) str, + stringLength, + ( CMSE_NONSECURE | CMSE_MPU_READ ) ) == NULL ) + { + PRINTF( "[ERROR] [NSC_Printf] String is not located in non-secure memory!\r\n" ); + isInvalidSting = 1; + } + } + + /* Print the string if it is a valid string. */ + if( isInvalidSting == 0 ) + { + PRINTF( str ); + } +} +/*-----------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NSC_Functions/nsc_printf.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NSC_Functions/nsc_printf.h new file mode 100644 index 000000000..1362b4556 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NSC_Functions/nsc_printf.h @@ -0,0 +1,37 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef NSC_PRINTF_H +#define NSC_PRINTF_H + +/** + * @brief Non-Secure callable printf function. + * + * @param str The string to print. + */ +void NSC_Printf( char const *str ); + +#endif /* NSC_PRINTF_H */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_iccarm.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_iccarm.h new file mode 100644 index 000000000..65b824b00 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/CMSIS/cmsis_iccarm.h @@ -0,0 +1,1002 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.3.0 + * @date 14. April 2021 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2021 IAR Systems +// Copyright (c) 2017-2021 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#undef __WEAK /* undo the definition from DLib_Defaults.h */ +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL STACKSEAL$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __arm_wsr("CONTROL", control); + __iar_builtin_ISB(); +} + + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __arm_wsr("CONTROL_NS", control); + __iar_builtin_ISB(); +} + + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + __iar_builtin_ISB(); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/startup/startup_LPC55S69_cm33_core0.s b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/startup/startup_LPC55S69_cm33_core0.s new file mode 100644 index 000000000..e83185c1b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/startup/startup_LPC55S69_cm33_core0.s @@ -0,0 +1,635 @@ +;/***************************************************************************** +; * @file: startup_LPC55S69_cm33_core0.s +; * @purpose: CMSIS Cortex-M33 Core Device Startup File +; * LPC55S69_cm33_core0 +; * @version: 1.1 +; * @date: 2019-5-16 +; *---------------------------------------------------------------------------- +; * +; Copyright 1997-2016 Freescale Semiconductor, Inc. +; Copyright 2016-2021 NXP +; All rights reserved. +; +; SPDX-License-Identifier: BSD-3-Clause +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__iar_init$$done: ; The vector table is not needed + ; until after copy initialization is done + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD SecureFault_Handler + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect, Flash interrupt + DCD DMA0_IRQHandler ; DMA0 controller + DCD GINT0_IRQHandler ; GPIO group 0 + DCD GINT1_IRQHandler ; GPIO group 1 + DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0 + DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1 + DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2 + DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3 + DCD UTICK0_IRQHandler ; Micro-tick Timer + DCD MRT0_IRQHandler ; Multi-rate timer + DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0 + DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1 + DCD SCT0_IRQHandler ; SCTimer/PWM + DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3 + DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) + DCD ADC0_IRQHandler ; ADC0 + DCD Reserved39_IRQHandler ; Reserved interrupt + DCD ACMP_IRQHandler ; ACMP interrupts + DCD Reserved41_IRQHandler ; Reserved interrupt + DCD Reserved42_IRQHandler ; Reserved interrupt + DCD USB0_NEEDCLK_IRQHandler ; USB Activity Wake-up Interrupt + DCD USB0_IRQHandler ; USB device + DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts + DCD Reserved46_IRQHandler ; Reserved interrupt + DCD MAILBOX_IRQHandler ; WAKEUP,Mailbox interrupt (present on selected devices) + DCD PIN_INT4_IRQHandler ; Pin interrupt 4 or pattern match engine slice 4 int + DCD PIN_INT5_IRQHandler ; Pin interrupt 5 or pattern match engine slice 5 int + DCD PIN_INT6_IRQHandler ; Pin interrupt 6 or pattern match engine slice 6 int + DCD PIN_INT7_IRQHandler ; Pin interrupt 7 or pattern match engine slice 7 int + DCD CTIMER2_IRQHandler ; Standard counter/timer CTIMER2 + DCD CTIMER4_IRQHandler ; Standard counter/timer CTIMER4 + DCD OS_EVENT_IRQHandler ; OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts + DCD Reserved55_IRQHandler ; Reserved interrupt + DCD Reserved56_IRQHandler ; Reserved interrupt + DCD Reserved57_IRQHandler ; Reserved interrupt + DCD SDIO_IRQHandler ; SD/MMC + DCD Reserved59_IRQHandler ; Reserved interrupt + DCD Reserved60_IRQHandler ; Reserved interrupt + DCD Reserved61_IRQHandler ; Reserved interrupt + DCD USB1_PHY_IRQHandler ; USB1_PHY + DCD USB1_IRQHandler ; USB1 interrupt + DCD USB1_NEEDCLK_IRQHandler ; USB1 activity + DCD SEC_HYPERVISOR_CALL_IRQHandler ; SEC_HYPERVISOR_CALL interrupt + DCD SEC_GPIO_INT0_IRQ0_IRQHandler ; SEC_GPIO_INT0_IRQ0 interrupt + DCD SEC_GPIO_INT0_IRQ1_IRQHandler ; SEC_GPIO_INT0_IRQ1 interrupt + DCD PLU_IRQHandler ; PLU interrupt + DCD SEC_VIO_IRQHandler ; SEC_VIO interrupt + DCD HASHCRYPT_IRQHandler ; HASHCRYPT interrupt + DCD CASER_IRQHandler ; CASPER interrupt + DCD PUF_IRQHandler ; PUF interrupt + DCD PQ_IRQHandler ; PQ interrupt + DCD DMA1_IRQHandler ; DMA1 interrupt + DCD FLEXCOMM8_IRQHandler ; Flexcomm Interface 8 (SPI, , FLEXCOMM) +__Vectors_End + + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + CPSID I ; Mask interrupts + LDR R0, =0xE000ED08 + LDR R1, =__vector_table + STR R1, [R0] + LDR R2, [R1] + MSR MSP, R2 + LDR R0, =sfb(CSTACK) + MSR MSPLIM, R0 + CPSIE I ; Unmask interrupts + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B . + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B . + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B . + + PUBWEAK SecureFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SecureFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + PUBWEAK WDT_BOD_IRQHandler + PUBWEAK WDT_BOD_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +WDT_BOD_IRQHandler + LDR R0, =WDT_BOD_DriverIRQHandler + BX R0 + PUBWEAK DMA0_IRQHandler + PUBWEAK DMA0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA0_IRQHandler + LDR R0, =DMA0_DriverIRQHandler + BX R0 + PUBWEAK GINT0_IRQHandler + PUBWEAK GINT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GINT0_IRQHandler + LDR R0, =GINT0_DriverIRQHandler + BX R0 + PUBWEAK GINT1_IRQHandler + PUBWEAK GINT1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GINT1_IRQHandler + LDR R0, =GINT1_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT0_IRQHandler + PUBWEAK PIN_INT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT0_IRQHandler + LDR R0, =PIN_INT0_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT1_IRQHandler + PUBWEAK PIN_INT1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT1_IRQHandler + LDR R0, =PIN_INT1_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT2_IRQHandler + PUBWEAK PIN_INT2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT2_IRQHandler + LDR R0, =PIN_INT2_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT3_IRQHandler + PUBWEAK PIN_INT3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT3_IRQHandler + LDR R0, =PIN_INT3_DriverIRQHandler + BX R0 + PUBWEAK UTICK0_IRQHandler + PUBWEAK UTICK0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UTICK0_IRQHandler + LDR R0, =UTICK0_DriverIRQHandler + BX R0 + PUBWEAK MRT0_IRQHandler + PUBWEAK MRT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +MRT0_IRQHandler + LDR R0, =MRT0_DriverIRQHandler + BX R0 + PUBWEAK CTIMER0_IRQHandler + PUBWEAK CTIMER0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER0_IRQHandler + LDR R0, =CTIMER0_DriverIRQHandler + BX R0 + PUBWEAK CTIMER1_IRQHandler + PUBWEAK CTIMER1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER1_IRQHandler + LDR R0, =CTIMER1_DriverIRQHandler + BX R0 + PUBWEAK SCT0_IRQHandler + PUBWEAK SCT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SCT0_IRQHandler + LDR R0, =SCT0_DriverIRQHandler + BX R0 + PUBWEAK CTIMER3_IRQHandler + PUBWEAK CTIMER3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER3_IRQHandler + LDR R0, =CTIMER3_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM0_IRQHandler + PUBWEAK FLEXCOMM0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM0_IRQHandler + LDR R0, =FLEXCOMM0_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM1_IRQHandler + PUBWEAK FLEXCOMM1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM1_IRQHandler + LDR R0, =FLEXCOMM1_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM2_IRQHandler + PUBWEAK FLEXCOMM2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM2_IRQHandler + LDR R0, =FLEXCOMM2_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM3_IRQHandler + PUBWEAK FLEXCOMM3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM3_IRQHandler + LDR R0, =FLEXCOMM3_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM4_IRQHandler + PUBWEAK FLEXCOMM4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM4_IRQHandler + LDR R0, =FLEXCOMM4_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM5_IRQHandler + PUBWEAK FLEXCOMM5_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM5_IRQHandler + LDR R0, =FLEXCOMM5_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM6_IRQHandler + PUBWEAK FLEXCOMM6_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM6_IRQHandler + LDR R0, =FLEXCOMM6_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM7_IRQHandler + PUBWEAK FLEXCOMM7_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM7_IRQHandler + LDR R0, =FLEXCOMM7_DriverIRQHandler + BX R0 + PUBWEAK ADC0_IRQHandler + PUBWEAK ADC0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ADC0_IRQHandler + LDR R0, =ADC0_DriverIRQHandler + BX R0 + PUBWEAK Reserved39_IRQHandler + PUBWEAK Reserved39_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved39_IRQHandler + LDR R0, =Reserved39_DriverIRQHandler + BX R0 + PUBWEAK ACMP_IRQHandler + PUBWEAK ACMP_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ACMP_IRQHandler + LDR R0, =ACMP_DriverIRQHandler + BX R0 + PUBWEAK Reserved41_IRQHandler + PUBWEAK Reserved41_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved41_IRQHandler + LDR R0, =Reserved41_DriverIRQHandler + BX R0 + PUBWEAK Reserved42_IRQHandler + PUBWEAK Reserved42_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved42_IRQHandler + LDR R0, =Reserved42_DriverIRQHandler + BX R0 + PUBWEAK USB0_NEEDCLK_IRQHandler + PUBWEAK USB0_NEEDCLK_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB0_NEEDCLK_IRQHandler + LDR R0, =USB0_NEEDCLK_DriverIRQHandler + BX R0 + PUBWEAK USB0_IRQHandler + PUBWEAK USB0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB0_IRQHandler + LDR R0, =USB0_DriverIRQHandler + BX R0 + PUBWEAK RTC_IRQHandler + PUBWEAK RTC_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +RTC_IRQHandler + LDR R0, =RTC_DriverIRQHandler + BX R0 + PUBWEAK Reserved46_IRQHandler + PUBWEAK Reserved46_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved46_IRQHandler + LDR R0, =Reserved46_DriverIRQHandler + BX R0 + PUBWEAK MAILBOX_IRQHandler + PUBWEAK MAILBOX_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +MAILBOX_IRQHandler + LDR R0, =MAILBOX_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT4_IRQHandler + PUBWEAK PIN_INT4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT4_IRQHandler + LDR R0, =PIN_INT4_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT5_IRQHandler + PUBWEAK PIN_INT5_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT5_IRQHandler + LDR R0, =PIN_INT5_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT6_IRQHandler + PUBWEAK PIN_INT6_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT6_IRQHandler + LDR R0, =PIN_INT6_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT7_IRQHandler + PUBWEAK PIN_INT7_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT7_IRQHandler + LDR R0, =PIN_INT7_DriverIRQHandler + BX R0 + PUBWEAK CTIMER2_IRQHandler + PUBWEAK CTIMER2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER2_IRQHandler + LDR R0, =CTIMER2_DriverIRQHandler + BX R0 + PUBWEAK CTIMER4_IRQHandler + PUBWEAK CTIMER4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER4_IRQHandler + LDR R0, =CTIMER4_DriverIRQHandler + BX R0 + PUBWEAK OS_EVENT_IRQHandler + PUBWEAK OS_EVENT_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +OS_EVENT_IRQHandler + LDR R0, =OS_EVENT_DriverIRQHandler + BX R0 + PUBWEAK Reserved55_IRQHandler + PUBWEAK Reserved55_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved55_IRQHandler + LDR R0, =Reserved55_DriverIRQHandler + BX R0 + PUBWEAK Reserved56_IRQHandler + PUBWEAK Reserved56_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved56_IRQHandler + LDR R0, =Reserved56_DriverIRQHandler + BX R0 + PUBWEAK Reserved57_IRQHandler + PUBWEAK Reserved57_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved57_IRQHandler + LDR R0, =Reserved57_DriverIRQHandler + BX R0 + PUBWEAK SDIO_IRQHandler + PUBWEAK SDIO_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SDIO_IRQHandler + LDR R0, =SDIO_DriverIRQHandler + BX R0 + PUBWEAK Reserved59_IRQHandler + PUBWEAK Reserved59_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved59_IRQHandler + LDR R0, =Reserved59_DriverIRQHandler + BX R0 + PUBWEAK Reserved60_IRQHandler + PUBWEAK Reserved60_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved60_IRQHandler + LDR R0, =Reserved60_DriverIRQHandler + BX R0 + PUBWEAK Reserved61_IRQHandler + PUBWEAK Reserved61_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved61_IRQHandler + LDR R0, =Reserved61_DriverIRQHandler + BX R0 + PUBWEAK USB1_PHY_IRQHandler + PUBWEAK USB1_PHY_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB1_PHY_IRQHandler + LDR R0, =USB1_PHY_DriverIRQHandler + BX R0 + PUBWEAK USB1_IRQHandler + PUBWEAK USB1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB1_IRQHandler + LDR R0, =USB1_DriverIRQHandler + BX R0 + PUBWEAK USB1_NEEDCLK_IRQHandler + PUBWEAK USB1_NEEDCLK_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB1_NEEDCLK_IRQHandler + LDR R0, =USB1_NEEDCLK_DriverIRQHandler + BX R0 + PUBWEAK SEC_HYPERVISOR_CALL_IRQHandler + PUBWEAK SEC_HYPERVISOR_CALL_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SEC_HYPERVISOR_CALL_IRQHandler + LDR R0, =SEC_HYPERVISOR_CALL_DriverIRQHandler + BX R0 + PUBWEAK SEC_GPIO_INT0_IRQ0_IRQHandler + PUBWEAK SEC_GPIO_INT0_IRQ0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SEC_GPIO_INT0_IRQ0_IRQHandler + LDR R0, =SEC_GPIO_INT0_IRQ0_DriverIRQHandler + BX R0 + PUBWEAK SEC_GPIO_INT0_IRQ1_IRQHandler + PUBWEAK SEC_GPIO_INT0_IRQ1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SEC_GPIO_INT0_IRQ1_IRQHandler + LDR R0, =SEC_GPIO_INT0_IRQ1_DriverIRQHandler + BX R0 + PUBWEAK PLU_IRQHandler + PUBWEAK PLU_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PLU_IRQHandler + LDR R0, =PLU_DriverIRQHandler + BX R0 + PUBWEAK SEC_VIO_IRQHandler + PUBWEAK SEC_VIO_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SEC_VIO_IRQHandler + LDR R0, =SEC_VIO_DriverIRQHandler + BX R0 + PUBWEAK HASHCRYPT_IRQHandler + PUBWEAK HASHCRYPT_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +HASHCRYPT_IRQHandler + LDR R0, =HASHCRYPT_DriverIRQHandler + BX R0 + PUBWEAK CASER_IRQHandler + PUBWEAK CASER_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CASER_IRQHandler + LDR R0, =CASER_DriverIRQHandler + BX R0 + PUBWEAK PUF_IRQHandler + PUBWEAK PUF_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PUF_IRQHandler + LDR R0, =PUF_DriverIRQHandler + BX R0 + PUBWEAK PQ_IRQHandler + PUBWEAK PQ_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PQ_IRQHandler + LDR R0, =PQ_DriverIRQHandler + BX R0 + PUBWEAK DMA1_IRQHandler + PUBWEAK DMA1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA1_IRQHandler + LDR R0, =DMA1_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM8_IRQHandler + PUBWEAK FLEXCOMM8_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM8_IRQHandler + LDR R0, =FLEXCOMM8_DriverIRQHandler + BX R0 +WDT_BOD_DriverIRQHandler +DMA0_DriverIRQHandler +GINT0_DriverIRQHandler +GINT1_DriverIRQHandler +PIN_INT0_DriverIRQHandler +PIN_INT1_DriverIRQHandler +PIN_INT2_DriverIRQHandler +PIN_INT3_DriverIRQHandler +UTICK0_DriverIRQHandler +MRT0_DriverIRQHandler +CTIMER0_DriverIRQHandler +CTIMER1_DriverIRQHandler +SCT0_DriverIRQHandler +CTIMER3_DriverIRQHandler +FLEXCOMM0_DriverIRQHandler +FLEXCOMM1_DriverIRQHandler +FLEXCOMM2_DriverIRQHandler +FLEXCOMM3_DriverIRQHandler +FLEXCOMM4_DriverIRQHandler +FLEXCOMM5_DriverIRQHandler +FLEXCOMM6_DriverIRQHandler +FLEXCOMM7_DriverIRQHandler +ADC0_DriverIRQHandler +Reserved39_DriverIRQHandler +ACMP_DriverIRQHandler +Reserved41_DriverIRQHandler +Reserved42_DriverIRQHandler +USB0_NEEDCLK_DriverIRQHandler +USB0_DriverIRQHandler +RTC_DriverIRQHandler +Reserved46_DriverIRQHandler +MAILBOX_DriverIRQHandler +PIN_INT4_DriverIRQHandler +PIN_INT5_DriverIRQHandler +PIN_INT6_DriverIRQHandler +PIN_INT7_DriverIRQHandler +CTIMER2_DriverIRQHandler +CTIMER4_DriverIRQHandler +OS_EVENT_DriverIRQHandler +Reserved55_DriverIRQHandler +Reserved56_DriverIRQHandler +Reserved57_DriverIRQHandler +SDIO_DriverIRQHandler +Reserved59_DriverIRQHandler +Reserved60_DriverIRQHandler +Reserved61_DriverIRQHandler +USB1_PHY_DriverIRQHandler +USB1_DriverIRQHandler +USB1_NEEDCLK_DriverIRQHandler +SEC_HYPERVISOR_CALL_DriverIRQHandler +SEC_GPIO_INT0_IRQ0_DriverIRQHandler +SEC_GPIO_INT0_IRQ1_DriverIRQHandler +PLU_DriverIRQHandler +SEC_VIO_DriverIRQHandler +HASHCRYPT_DriverIRQHandler +CASER_DriverIRQHandler +PUF_DriverIRQHandler +PQ_DriverIRQHandler +DMA1_DriverIRQHandler +FLEXCOMM8_DriverIRQHandler +DefaultISR + B . + + END diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/trustzone/tzm_config.c b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/trustzone/tzm_config.c new file mode 100644 index 000000000..ee665709a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/trustzone/tzm_config.c @@ -0,0 +1,272 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: TEE v3.0 +processor: LPC55S69 +package_id: LPC55S69JBD100 +mcu_data: ksdk2_0 +processor_version: 0.10.1 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/*********************************************************************************************************************** + * Included files + **********************************************************************************************************************/ +#include "fsl_common.h" +#include "tzm_config.h" + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ +/* SAU region boundaries */ +#define SAU_REGION_0_BASE 0 +#define SAU_REGION_0_END 0x0FFFFFFFU +#define SAU_REGION_1_BASE 0x20000000U +#define SAU_REGION_1_END 0xDFFFFFFFU +#define SAU_REGION_2_BASE 0x1000FE00U +#define SAU_REGION_2_END 0x1000FFFFU + + + +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +functional_group: +- called_from_default_init: 'true' +- id_prefix: '' +- prefix_user_defined: 'true' +- name: 'BOARD_InitTEE' +- description: '' +- ahb: + - regions: [{memory: PROGRAM_FLASH, security: s_priv, start: '0x00000000', size: '0x00010000'}, {memory: PROGRAM_FLASH, security: ns_user, start: '0x00010000', + size: '0x00090000'}, {memory: BootROM, security: ns_user, start: '0x00000000', size: '0x00020000'}, {memory: SRAMX, security: ns_user, start: '0x00000000', + size: '0x00008000'}, {memory: SRAM0, security: s_priv, start: '0x00000000', size: '0x00008000'}, {memory: SRAM0, security: ns_user, start: '0x00008000', size: '0x00008000'}, + {memory: SRAM1, security: ns_user, start: '0x00000000', size: '0x00010000'}, {memory: SRAM2, security: ns_user, start: '0x00000000', size: '0x00010000'}, {memory: SRAM3, + security: ns_user, start: '0x00000000', size: '0x00010000'}, {memory: SRAM4, security: ns_user, start: '0x00000000', size: '0x00004000'}, {memory: USB_RAM, + security: ns_user, start: '0x00000000', size: '0x00004000'}] + - masters: {ns_user: {id: [HASH, MCM33C, MCM33S, PQ, SDIO, SDMA0, SDMA1, USBFSD, USBFSH]}} + - peripherals: {ns_user: {id: [ADC0, AHB_SECURE_CTRL, ANACTRL, CASPER, CRC_ENGINE, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DBGMAILBOX, DMA0, DMA1, FLASH, + FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, GINT0, GINT1, GPIO, HASHCRYPT, INPUTMUX, MAILBOX, MRT0, OSTIMER, PINT, PLU, PMC, + POWERQUAD, PRINCE, PUF, RNG, RTC, SCT0, SDIF, SECGPIO, SECPINT, SPI8, SYSCTL, USB0, USBFSH, USBHSD, USBHSH, USBPHY, UTICK0, WWDT]}, s_priv: {id: [FLEXCOMM0, + IOCON, SYSCON]}} + - interrupts: + - masking: {Non-masked: {id: [acmp_capt_irq, adc_irq, casper_irq, ctimer0_irq, ctimer1_irq, ctimer2_irq, ctimer3_irq, ctimer4_irq, flexcomm0_irq, flexcomm1_irq, + flexcomm2_irq, flexcomm3_irq, flexcomm4_irq, flexcomm5_irq, flexcomm6_irq, flexcomm7_irq, global_irq0, global_irq1, lspi_hs_irq, mailbox_irq, mrt_irq, os_event_irq, + pin_int4, pin_int5, pin_int6, pin_int7, pin_irq0, pin_irq1, pin_irq2, pin_irq3, plu_irq, pq_irq, qddkey_irq, rtc_irq, sct_irq, sdio_irq, sdma0_irq, sdma1_irq, + sec_hypervisor_call_irq, sec_int0, sec_int1, sec_vio_irq, sha_irq, sys_irq, usb0_irq, usb0_needclk_irq, usb1_irq, usb1_needclk_irq, usb1_utmi_irq, utick_irq]}} + - security: {Secure: {id: [acmp_capt_irq, adc_irq, casper_irq, ctimer0_irq, ctimer1_irq, ctimer2_irq, ctimer3_irq, ctimer4_irq, flexcomm0_irq, flexcomm1_irq, + flexcomm2_irq, flexcomm3_irq, flexcomm4_irq, flexcomm5_irq, flexcomm6_irq, flexcomm7_irq, global_irq0, global_irq1, lspi_hs_irq, mailbox_irq, mrt_irq, os_event_irq, + pin_int4, pin_int5, pin_int6, pin_int7, pin_irq0, pin_irq1, pin_irq2, pin_irq3, plu_irq, pq_irq, qddkey_irq, rtc_irq, sct_irq, sdio_irq, sdma0_irq, sdma1_irq, + sec_hypervisor_call_irq, sec_int0, sec_int1, sec_vio_irq, sha_irq, sys_irq, usb0_irq, usb0_needclk_irq, usb1_irq, usb1_needclk_irq, usb1_utmi_irq, utick_irq]}} + - pins_masks: + - pio0: {Non-masked: {id: ['0', '1', '10', '11', '12', '13', '14', '15', '16', '17', '18', '19', '2', '20', '21', '22', '23', '24', '25', '26', '27', '28', + '3', '31', '4', '5', '6', '7', '8', '9']}, Masked: {id: ['29', '30']}} + - pio1: {Non-masked: {id: ['0', '1', '10', '11', '12', '13', '14', '15', '16', '17', '18', '19', '2', '20', '21', '22', '23', '24', '25', '26', '27', '28', + '29', '3', '30', '31', '4', '5', '6', '7', '8', '9']}} +- sau: + - enabled: 'true' + - all_non_secure: 'false' + - generate_code_for_disabled_regions: 'false' + - regions: [{index: '0', enabled: 'true', security: ns, start: '0x00000000', size: '0x10000000'}, {index: '1', enabled: 'true', security: ns, start: '0x20000000', + size: '0xC0000000'}, {index: '2', enabled: 'true', security: nsc, start: '0x1000FE00', size: '0x00000200'}, {index: '3', enabled: 'false', security: ns, start: '0x00000000', + size: '0x00000020'}, {index: '4', enabled: 'false', security: ns, start: '0x00000000', size: '0x00000020'}, {index: '5', enabled: 'false', security: ns, start: '0x00000000', + size: '0x00000020'}, {index: '6', enabled: 'false', security: ns, start: '0x00000000', size: '0x00000020'}, {index: '7', enabled: 'false', security: ns, start: '0x00000000', + size: '0x00000020'}] +- global_options: + - no: + - id: [AIRCR_PRIS, AIRCR_BFHFNMINS, AIRCR_SYSRESETREQS, SCR_SLEEPDEEPS, SHCSR_SECUREFAULTENA, NSACR_CP2, NSACR_CP3, NSACR_CP4, NSACR_CP5, NSACR_CP6, NSACR_CP7, + CPPWR_SU0, CPPWR_SUS0, CPPWR_SU1, CPPWR_SUS1, CPPWR_SU2, CPPWR_SUS2, CPPWR_SU3, CPPWR_SUS3, CPPWR_SU4, CPPWR_SUS4, CPPWR_SU5, CPPWR_SUS5, CPPWR_SU6, CPPWR_SUS6, + CPPWR_SU7, CPPWR_SUS7, CPPWR_SU10, CPPWR_SUS10, CPPWR_SU11, CPPWR_SUS11, SEC_GPIO_MASK0_LOCK, SEC_GPIO_MASK1_LOCK, SEC_CPU1_INT_MASK0_LOCK, SEC_CPU1_INT_MASK1_LOCK, + MASTER_SEC_LEVEL_LOCK, CPU0_LOCK_NS_VTOR, CPU0_LOCK_NS_MPU, CPU0_LOCK_S_VTAIRCR, CPU0_LOCK_S_MPU, CPU0_LOCK_SAU, CPU0_LOCK_REG_LOCK, CPU1_LOCK_NS_VTOR, CPU1_LOCK_NS_MPU, + CPU1_LOCK_REG_LOCK, AHB_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK, AHB_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK, AHB_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT, AHB_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE, + AHB_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE, AHB_MISC_CTRL_REG_IDAU_ALL_NS] + - yes: + - id: [NSACR_CP0, NSACR_CP1, NSACR_CP10, NSACR_CP11, AHB_MISC_CTRL_REG_ENABLE_SECURE_CHECKING, AHB_MISC_CTRL_REG_WRITE_LOCK, _legacy_source_names_] + - c_code: + - id: [_output_type_] +- user_memory_regions: [{id: Region_1, security: s_priv, name: Secure Code, start: '0x10000000', size: '0x0000FE00'}, {id: Region_2, security: nsc_priv, name: Veneer + Table, start: '0x1000FE00', size: '0x00000200'}, {id: Region_3, security: s_priv, name: Secure Stack and Data, start: '0x30000000', size: '0x00008000'}, {id: Region_4, + security: ns_user, name: Non-secure Code, description: Privilege check is disabled so reset value (NS-User) can be used, start: '0x00010000', size: '0x00068000'}, + {id: Region_5, security: ns_user, name: Non-secure Stack and Data, description: 'Privilege check is disabled so reset value (NS-User) can be used. ', start: '0x20008000', + size: '0x0002B000'}] +- mpus: + - mpu: + - enabled: 'false' + - id: 's' + - priv_default_map: 'false' + - handler_enabled: 'false' + - generate_code_for_disabled_regions: 'false' + - attributes: [{index: '0', id: '0', memory_type: device, device: nGnRE}, {index: '1', id: '1', memory_type: device, device: nGnRE}, {index: '2', id: '2', memory_type: device, + device: nGnRE}, {index: '3', id: '3', memory_type: device, device: nGnRE}, {index: '4', id: '4', memory_type: device, device: nGnRE}, {index: '5', id: '5', + memory_type: device, device: nGnRE}, {index: '6', id: '6', memory_type: device, device: nGnRE}, {index: '7', id: '7', memory_type: device, device: nGnRE}] + - regions: [{executable: 'false', read_only: 'false', attributes_index: '0', index: '0', enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, + {executable: 'false', read_only: 'false', attributes_index: '0', index: '1', enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', + read_only: 'false', attributes_index: '0', index: '2', enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', read_only: 'false', + attributes_index: '0', index: '3', enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', read_only: 'false', attributes_index: '0', + index: '4', enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', read_only: 'false', attributes_index: '0', index: '5', + enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', read_only: 'false', attributes_index: '0', index: '6', enabled: 'false', + security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', read_only: 'false', attributes_index: '0', index: '7', enabled: 'false', security: priv, + start: '0x00000000', size: '0x00000020'}] + - mpu: + - enabled: 'false' + - id: 'ns' + - priv_default_map: 'false' + - handler_enabled: 'false' + - generate_code_for_disabled_regions: 'false' + - attributes: [{index: '0', id: '0', memory_type: device, device: nGnRE}, {index: '1', id: '1', memory_type: device, device: nGnRE}, {index: '2', id: '2', memory_type: device, + device: nGnRE}, {index: '3', id: '3', memory_type: device, device: nGnRE}, {index: '4', id: '4', memory_type: device, device: nGnRE}, {index: '5', id: '5', + memory_type: device, device: nGnRE}, {index: '6', id: '6', memory_type: device, device: nGnRE}, {index: '7', id: '7', memory_type: device, device: nGnRE}] + - regions: [{executable: 'false', read_only: 'false', attributes_index: '0', index: '0', enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, + {executable: 'false', read_only: 'false', attributes_index: '0', index: '1', enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', + read_only: 'false', attributes_index: '0', index: '2', enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', read_only: 'false', + attributes_index: '0', index: '3', enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', read_only: 'false', attributes_index: '0', + index: '4', enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', read_only: 'false', attributes_index: '0', index: '5', + enabled: 'false', security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', read_only: 'false', attributes_index: '0', index: '6', enabled: 'false', + security: priv, start: '0x00000000', size: '0x00000020'}, {executable: 'false', read_only: 'false', attributes_index: '0', index: '7', enabled: 'false', security: priv, + start: '0x00000000', size: '0x00000020'}] + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/*********************************************************************************************************************** + * BOARD_InitTrustZone function + **********************************************************************************************************************/ +void BOARD_InitTrustZone() +{ + /* SAU configuration */ + + /* Set SAU Control register: Disable SAU and All Secure */ + SAU->CTRL = 0; + + /* Set SAU region number */ + SAU->RNR = 0; + /* Region base address */ + SAU->RBAR = SAU_REGION_0_BASE & SAU_RBAR_BADDR_Msk; + /* Region end address */ + SAU->RLAR = (SAU_REGION_0_END & SAU_RLAR_LADDR_Msk) + | ((0U << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) + | ((1U << SAU_RLAR_ENABLE_Pos) & SAU_RLAR_ENABLE_Msk); + + /* Set SAU region number */ + SAU->RNR = 1; + /* Region base address */ + SAU->RBAR = SAU_REGION_1_BASE & SAU_RBAR_BADDR_Msk; + /* Region end address */ + SAU->RLAR = (SAU_REGION_1_END & SAU_RLAR_LADDR_Msk) + | ((0U << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) + | ((1U << SAU_RLAR_ENABLE_Pos) & SAU_RLAR_ENABLE_Msk); + + /* Set SAU region number */ + SAU->RNR = 2; + /* Region base address */ + SAU->RBAR = SAU_REGION_2_BASE & SAU_RBAR_BADDR_Msk; + /* Region end address */ + SAU->RLAR = (SAU_REGION_2_END & SAU_RLAR_LADDR_Msk) + | ((1U << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) + | ((1U << SAU_RLAR_ENABLE_Pos) & SAU_RLAR_ENABLE_Msk); + + /* Force memory writes before continuing */ + __DSB(); + /* Flush and refill pipeline with updated permissions */ + __ISB(); + + /* Set SAU Control register: Enable SAU and All Secure (applied only if disabled) */ + SAU->CTRL = ((0U << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) + | ((1U << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk); + + /* AHB configuration */ + + /*-------------------------------------------------------------------- + - AHB Security Level Configurations + -------------------------------------------------------------------*/ + /* Configuration of AHB Secure Controller + Possible values for every memory sector or peripheral rule: + 0 Non-secure, User access allowed. + 1 Non-secure, Privileged access allowed. + 2 Secure, User access allowed. + 3 Secure, Privileged access allowed. + */ + + /* Security level configuration of MPC checker */ + AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_FLASH_MEM_RULE[0] = 0x00000033U; + AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_FLASH_MEM_RULE[1] = 0; + AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_FLASH_MEM_RULE[2] = 0; + AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_ROM_MEM_RULE[0] = 0; + AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_ROM_MEM_RULE[1] = 0; + AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_ROM_MEM_RULE[2] = 0; + AHB_SECURE_CTRL->SEC_CTRL_FLASH_ROM[0].SEC_CTRL_ROM_MEM_RULE[3] = 0; + AHB_SECURE_CTRL->SEC_CTRL_RAMX[0].MEM_RULE[0] = 0; + AHB_SECURE_CTRL->SEC_CTRL_RAM0[0].MEM_RULE[0] = 0x33333333U; + AHB_SECURE_CTRL->SEC_CTRL_RAM0[0].MEM_RULE[1] = 0; + AHB_SECURE_CTRL->SEC_CTRL_RAM1[0].MEM_RULE[0] = 0; + AHB_SECURE_CTRL->SEC_CTRL_RAM1[0].MEM_RULE[1] = 0; + AHB_SECURE_CTRL->SEC_CTRL_RAM2[0].MEM_RULE[0] = 0; + AHB_SECURE_CTRL->SEC_CTRL_RAM2[0].MEM_RULE[1] = 0; + AHB_SECURE_CTRL->SEC_CTRL_RAM3[0].MEM_RULE[0] = 0; + AHB_SECURE_CTRL->SEC_CTRL_RAM3[0].MEM_RULE[1] = 0; + AHB_SECURE_CTRL->SEC_CTRL_RAM4[0].MEM_RULE[0] = 0; + AHB_SECURE_CTRL->SEC_CTRL_USB_HS[0].MEM_RULE[0] = 0; + + /* Security level configuration of PPC checker */ + AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 = 0xFCCCCCFFU; + AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 = 0xFCCCFFCCU; + AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 = 0xFFFFCFFFU; + AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 = 0xFFFFCFFCU; + AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 = 0xFFCCFCCCU; + AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 = 0xFFCCFFFFU; + AHB_SECURE_CTRL->SEC_CTRL_APB_BRIDGE[0].SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 = 0xFFCFCCFCU; + AHB_SECURE_CTRL->SEC_CTRL_AHB_PORT8_SLAVE0_RULE = 0xCFCCFCFFU; + AHB_SECURE_CTRL->SEC_CTRL_AHB_PORT8_SLAVE1_RULE = 0xFFFCCCCCU; + AHB_SECURE_CTRL->SEC_CTRL_AHB_PORT9_SLAVE0_RULE = 0xCCCCFFFFU; + AHB_SECURE_CTRL->SEC_CTRL_AHB_PORT9_SLAVE1_RULE = 0xCFFCCFFCU; + AHB_SECURE_CTRL->SEC_CTRL_AHB_PORT10[0].SLAVE0_RULE = 0xCCCCCCFCU; + AHB_SECURE_CTRL->SEC_CTRL_AHB_PORT10[0].SLAVE1_RULE = 0xFFFFFFCCU; + + /* Security level configuration of masters */ + AHB_SECURE_CTRL->MASTER_SEC_LEVEL = 0x80000000U; + AHB_SECURE_CTRL->MASTER_SEC_ANTI_POL_REG = 0xBFFFFFFFU; + + /*-------------------------------------------------------------------- + - Pins: Reading GPIO state + -------------------------------------------------------------------*/ + /* Possible values for every pin: + * 0b0 Deny + * 0b1 Allow */ + AHB_SECURE_CTRL->SEC_GPIO_MASK0 = 0x9FFFFFFFU; + AHB_SECURE_CTRL->SEC_GPIO_MASK1 = 0xFFFFFFFFU; + + /*-------------------------------------------------------------------- + - Interrupts: Interrupt handling by Core1 + -------------------------------------------------------------------*/ + /* Possible values for every interrupt: + * 0b0 Deny + * 0b1 Allow */ + AHB_SECURE_CTRL->SEC_CPU_INT_MASK0 = 0xFFFFFFFFU; + AHB_SECURE_CTRL->SEC_CPU_INT_MASK1 = 0xFFFFFFFFU; + + /*-------------------------------------------------------------------- + - Interrupts: Interrupt security configuration + -------------------------------------------------------------------*/ + /* Possible values for every interrupt: + * 0b0 Secure + * 0b1 Non-secure */ + NVIC->ITNS[0] = 0; + NVIC->ITNS[1] = 0; + + /* Global Options */ + SCB->AIRCR = (SCB->AIRCR & 0x000009FF7U) | 0x005FA0000U; + SCB->SCR &= 0x0FFFFFFF7U; + SCB->SHCSR &= 0x0FFF7FFFFU; + SCB->NSACR = 0x00000C03U; + SCnSCB->CPPWR = 0; + AHB_SECURE_CTRL->SEC_MASK_LOCK = 0x00000AAAU; + AHB_SECURE_CTRL->MASTER_SEC_LEVEL = (AHB_SECURE_CTRL->MASTER_SEC_LEVEL & 0x03FFFFFFFU) | 0x080000000U; + AHB_SECURE_CTRL->MASTER_SEC_ANTI_POL_REG = (AHB_SECURE_CTRL->MASTER_SEC_ANTI_POL_REG & 0x03FFFFFFFU) | 0x080000000U; + AHB_SECURE_CTRL->CPU0_LOCK_REG = 0x800002AAU; + AHB_SECURE_CTRL->CPU1_LOCK_REG = 0x8000000AU; + AHB_SECURE_CTRL->MISC_CTRL_REG = (AHB_SECURE_CTRL->MISC_CTRL_REG & 0x0FFFF0003U) | 0x00000AAA4U; + AHB_SECURE_CTRL->MISC_CTRL_DP_REG = 0x0000AAA5U; +} diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/trustzone/tzm_config.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/trustzone/tzm_config.h new file mode 100644 index 000000000..9cc45d1a0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/trustzone/tzm_config.h @@ -0,0 +1,18 @@ +#ifndef _TZM_CONFIG_H_ +#define _TZM_CONFIG_H_ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + + +/*********************************************************************************************************************** + * Initialize TrustZone + **********************************************************************************************************************/ +void BOARD_InitTrustZone(void); + +#if defined(__cplusplus) +} +#endif + +#endif /* _TZM_CONFIG_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/Config/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/Config/FreeRTOSConfig.h new file mode 100644 index 000000000..681d846a7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/Config/FreeRTOSConfig.h @@ -0,0 +1,169 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/****************************************************************************** + See http://www.freertos.org/a00110.html for an explanation of the + definitions contained in this file. +******************************************************************************/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * https://www.FreeRTOS.org/a00110.html + *----------------------------------------------------------*/ + +#ifndef __IASMARM__ + #include "clock_config.h" +#endif + +/* Cortex M33 port configuration. */ +#define configENABLE_MPU 1 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 1 + +/* Constants related to the behaviour or the scheduler. */ +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configUSE_PREEMPTION 1 +#define configUSE_TIME_SLICING 1 +#define configMAX_PRIORITIES ( 5 ) +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_16_BIT_TICKS 0 /* Only for 8 and 16-bit hardware. */ + +/* Constants that describe the hardware and memory usage. */ +#define configCPU_CLOCK_HZ BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK +#define configMINIMAL_STACK_SIZE ( ( uint16_t ) 128 ) +#define configMINIMAL_SECURE_STACK_SIZE ( 1024 ) +#define configMAX_TASK_NAME_LEN ( 12 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 50 * 1024 ) ) + +/* Constants that build features in or out. */ +#define configUSE_MUTEXES 1 +#define configUSE_TICKLESS_IDLE 1 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_TRACE_FACILITY 1 + +/* Constants that define which hook (callback) functions should be used. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 + +/* Constants provided for debugging and optimisation assistance. */ +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } +#define configQUEUE_REGISTRY_SIZE 0 + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( 3 ) +#define configTIMER_QUEUE_LENGTH 5 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE ) + +/* Set the following definitions to 1 to include the API function, or zero + * to exclude the API function. NOTE: Setting an INCLUDE_ parameter to 0 is + * only necessary if the linker does not automatically remove functions that are + * not referenced anyway. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xTaskResumeFromISR 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xSemaphoreGetMutexHolder 0 +#define INCLUDE_xTimerPendFunctionCall 1 + +/* This demo makes use of one or more example stats formatting functions. These + * format the raw data provided by the uxTaskGetSystemState() function in to + * human readable ASCII form. See the notes in the implementation of vTaskList() + * within FreeRTOS/Source/tasks.c for limitations. */ +#define configUSE_STATS_FORMATTING_FUNCTIONS 1 + +/* Dimensions a buffer that can be used by the FreeRTOS+CLI command interpreter. + * See the FreeRTOS+CLI documentation for more information: + * https://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_CLI/ */ +#define configCOMMAND_INT_MAX_OUTPUT_SIZE 2048 + +/* Interrupt priority configuration follows...................... */ + +/* Use the system definition, if there is one. */ +#ifdef __NVIC_PRIO_BITS + #define configPRIO_BITS __NVIC_PRIO_BITS +#else + #define configPRIO_BITS 3 /* 8 priority levels. */ +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" + * function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x07 + +/* The highest interrupt priority that can be used by any interrupt service + * routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT + * CALL INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A + * HIGHER PRIORITY THAN THIS! (higher priorities are lower numeric values). */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5 + +/* Interrupt priorities used by the kernel port layer itself. These are generic + * to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << ( 8 - configPRIO_BITS ) ) + +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! + * See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << ( 8 - configPRIO_BITS ) ) + +/* The #ifdef guards against the file being included from IAR assembly files. */ +#ifndef __IASMARM__ + + /* Constants related to the generation of run time stats. */ + #define configGENERATE_RUN_TIME_STATS 0 + #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() + #define portGET_RUN_TIME_COUNTER_VALUE() 0 + #define configTICK_RATE_HZ ( ( TickType_t ) 100 ) + +#endif /* __IASMARM__ */ + +/* Enable static allocation. */ +#define configSUPPORT_STATIC_ALLOCATION 1 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/FreeRTOSDemo.eww b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/FreeRTOSDemo.eww new file mode 100644 index 000000000..f1093c989 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/FreeRTOSDemo.eww @@ -0,0 +1,22 @@ + + + + + all + + FreeRTOSDemo_s + debug + + + FreeRTOSDemo_ns + debug + + + + + $WS_DIR$/Secure/FreeRTOSDemo_s.ewp + + + $WS_DIR$/NonSecure/FreeRTOSDemo_ns.ewp + + diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/NonSecure/FreeRTOSDemo_flash_ns.icf b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/NonSecure/FreeRTOSDemo_flash_ns.icf new file mode 100644 index 000000000..5345cea5c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/NonSecure/FreeRTOSDemo_flash_ns.icf @@ -0,0 +1,144 @@ +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core0 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JEV98_cm33_core0 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 1.1, 2019-05-16 +** Build: b190926 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* USB BDT size */ +define symbol usb_bdt_size = 0x0; +/* Stack and Heap Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define symbol m_privileged_text_start = 0x00010000; +define symbol m_privileged_text_end = 0x00017FFF; + +define symbol m_syscalls_text_start = 0x00018000; +define symbol m_syscalls_text_end = 0x0001FFFF; + +define symbol m_unprivileged_text_start = 0x00020000; +define symbol m_unprivileged_text_end = 0x00071FFF; + +define exported symbol core1_image_start = 0x00072000; +define exported symbol core1_image_end = 0x0009D7FF; + +if (isdefinedsymbol(__use_shmem__)) { + define symbol m_privileged_data_start = 0x20008000; + define symbol m_privileged_data_end = 0x20017FFF; + + define symbol m_unprivileged_data_start = 0x20018000; + define symbol m_unprivileged_data_end = 0x20030FFF; + + define exported symbol rpmsg_sh_mem_start = 0x20031800; + define exported symbol rpmsg_sh_mem_end = 0x20032FFF; +} else { + define symbol m_privileged_data_start = 0x20008000; + define symbol m_privileged_data_end = 0x20017FFF; + + define symbol m_unprivileged_data_start = 0x20018000; + define symbol m_unprivileged_data_end = 0x20032FFF; +} + +define symbol m_usb_sram_start = 0x40100000; +define symbol m_usb_sram_end = 0x40103FFF; + +define memory mem with size = 4G; + +define region TEXT_privileged_region = mem:[from m_privileged_text_start to m_privileged_text_end]; +define region TEXT_syscalls_region = mem:[from m_syscalls_text_start to m_syscalls_text_end]; +define region TEXT_unprivileged_region = mem:[from m_unprivileged_text_start to m_unprivileged_text_end]; + + +define region DATA_privileged_region = mem:[from m_privileged_data_start to m_privileged_data_end]; +define region DATA_unprivileged_region = mem:[from m_unprivileged_data_start to m_unprivileged_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_unprivileged_data_end-__size_cstack__+1 to m_unprivileged_data_end]; + +if (isdefinedsymbol(__use_shmem__)) { + define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; +} + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + +define region core1_region = mem:[from core1_image_start to core1_image_end]; +define block CORE1_IMAGE_WBLOCK { section __core1_image }; + +/* regions for USB */ +define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1]; +define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end]; +place in USB_BDT_region { section m_usb_bdt }; +place in USB_SRAM_region { section m_usb_global }; + +initialize by copy { readwrite, section .textrw }; + +if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) +{ + /* Required in a multi-threaded application */ + initialize by copy with packing = none { section __DLIB_PERTHREAD }; +} + +do not initialize { section .noinit, section m_usb_bdt, section m_usb_global }; +if (isdefinedsymbol(__use_shmem__)) { + do not initialize { section rpmsg_sh_mem_section }; +} + +/* Exported symbols. */ +define exported symbol __privileged_functions_start__ = m_privileged_text_start; +define exported symbol __privileged_functions_end__ = m_privileged_text_end; +define exported symbol __syscalls_flash_start__ = m_syscalls_text_start; +define exported symbol __syscalls_flash_end__ = m_syscalls_text_end; +define exported symbol __unprivileged_flash_start__ = m_unprivileged_text_start; +define exported symbol __unprivileged_flash_end__ = m_unprivileged_text_end; +define exported symbol __privileged_sram_start__ = m_privileged_data_start; +define exported symbol __privileged_sram_end__ = m_privileged_data_end; + +/* Placements. */ +place at address mem: m_privileged_text_start { readonly section .intvec }; + +place in TEXT_privileged_region { readonly section privileged_functions }; +place in TEXT_syscalls_region { readonly section freertos_system_calls }; +place in TEXT_unprivileged_region { readonly }; + +place in DATA_privileged_region { readwrite section privileged_data }; +place in DATA_unprivileged_region { block RW }; +place in DATA_unprivileged_region { block ZI }; +place in DATA_unprivileged_region { last block HEAP }; + +place in CSTACK_region { block CSTACK }; +if (isdefinedsymbol(__use_shmem__)) { + place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; +} +place in core1_region { block CORE1_IMAGE_WBLOCK }; + diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/NonSecure/FreeRTOSDemo_ns.ewd b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/NonSecure/FreeRTOSDemo_ns.ewd new file mode 100644 index 000000000..5f2320290 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/NonSecure/FreeRTOSDemo_ns.ewd @@ -0,0 +1,12342 @@ + + + + 3 + + + + debug + + + + ARM + + + + 1 + + + + C-SPY + + 2 + + + + 32 + + 1 + + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\NXP_Code\board\pin_mux.c + + + $PROJ_DIR$\..\..\..\NXP_Code\board\pin_mux.h + + + + CMSIS + + $PROJ_DIR$\..\..\..\NXP_Code\CMSIS\cmsis_compiler.h + + + $PROJ_DIR$\..\..\..\NXP_Code\CMSIS\cmsis_gcc.h + + + $PROJ_DIR$\..\..\..\NXP_Code\CMSIS\cmsis_iccarm.h + + + $PROJ_DIR$\..\..\..\NXP_Code\CMSIS\cmsis_version.h + + + $PROJ_DIR$\..\..\..\NXP_Code\CMSIS\core_cm33.h + + + $PROJ_DIR$\..\..\..\NXP_Code\CMSIS\mpu_armv8.h + + + $PROJ_DIR$\..\..\..\NXP_Code\CMSIS\tz_context.h + + + + component + + lists + + $PROJ_DIR$\..\..\..\NXP_Code\component\lists\fsl_component_generic_list.c + + + $PROJ_DIR$\..\..\..\NXP_Code\component\lists\fsl_component_generic_list.h + + + + uart + + $PROJ_DIR$\..\..\..\NXP_Code\component\uart\fsl_adapter_uart.h + + + $PROJ_DIR$\..\..\..\NXP_Code\component\uart\fsl_adapter_usart.c + + + + + device + + $PROJ_DIR$\..\..\..\NXP_Code\device\fsl_device_registers.h + + + $PROJ_DIR$\..\..\..\NXP_Code\device\LPC55S69_cm33_core0.h + + + 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$PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_reset.c + + + $PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_reset.h + + + $PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_usart.c + + + $PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_usart.h + + + + startup + + $PROJ_DIR$\..\..\..\NXP_Code\startup\startup_LPC55S69_cm33_core0.s + + + + utilities + + $PROJ_DIR$\..\..\..\NXP_Code\utilities\fsl_assert.c + + + $PROJ_DIR$\..\..\..\NXP_Code\utilities\fsl_debug_console.c + + + $PROJ_DIR$\..\..\..\NXP_Code\utilities\fsl_debug_console.h + + + $PROJ_DIR$\..\..\..\NXP_Code\utilities\fsl_str.c + + + $PROJ_DIR$\..\..\..\NXP_Code\utilities\fsl_str.h + + + + + User + + $PROJ_DIR$\fault_handler.s + + + $PROJ_DIR$\..\..\..\User\NonSecure\main_ns.c + + + $PROJ_DIR$\..\..\..\RegTests\reg_tests.c + + + $PROJ_DIR$\..\..\..\RegTests\reg_tests.h + + + diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/NonSecure/fault_handler.s b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/NonSecure/fault_handler.s new file mode 100644 index 000000000..70cba7358 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/NonSecure/fault_handler.s @@ -0,0 +1,42 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + EXTERN vHandleMemoryFault + PUBLIC MemManage_Handler + + SECTION .text:CODE:NOROOT(2) + THUMB +/*-----------------------------------------------------------*/ + +MemManage_Handler: + tst lr, #4 + ite eq + mrseq r0, msp + mrsne r0, psp + b vHandleMemoryFault +/*-----------------------------------------------------------*/ + + END diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/Secure/FreeRTOSDemo_flash_s.icf b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/Secure/FreeRTOSDemo_flash_s.icf new file mode 100644 index 000000000..fbccbfc44 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/Secure/FreeRTOSDemo_flash_s.icf @@ -0,0 +1,122 @@ +/* +** ################################################################### +** Processors: LPC55S69JBD100_cm33_core0 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JEV98_cm33_core0 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 1.1, 2019-05-16 +** Build: b190926 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* USB BDT size */ +define symbol usb_bdt_size = 0x0; +/* Stack and Heap Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +/* Only the first 64kB of flash is used as secure memory. */ +define symbol m_interrupts_start = 0x10000000; +define symbol m_interrupts_end = 0x100001FF; + +define symbol m_text_start = 0x10000200; +define symbol m_text_end = 0x1000FDFF; + +define exported symbol core1_image_start = 0x10072000; +define exported symbol core1_image_end = 0x1009D7FF; + +/* Only first 32kB of data RAM is used as secure memory. */ +if (isdefinedsymbol(__use_shmem__)) { + define symbol m_data_start = 0x30000000; + define symbol m_data_end = 0x30007FFF; + define exported symbol rpmsg_sh_mem_start = 0x30031800; + define exported symbol rpmsg_sh_mem_end = 0x30032FFF; +} else { + define symbol m_data_start = 0x30000000; + define symbol m_data_end = 0x30007FFF; +} + +/* 512B - memory for veneer table (NSC - secure, non-secure callable memory) */ +define symbol m_veneer_table_start = 0x1000FE00; +define symbol m_veneer_table_size = 0x200; + +define symbol m_usb_sram_start = 0x50100000; +define symbol m_usb_sram_end = 0x50103FFF; + +define memory mem with size = 4G; + +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; +if (isdefinedsymbol(__use_shmem__)) { + define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; +} + +define region VENEER_TABLE_region = mem:[from m_veneer_table_start to m_veneer_table_start + m_veneer_table_size - 1]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + +define region core1_region = mem:[from core1_image_start to core1_image_end]; +define block CORE1_IMAGE_WBLOCK { section __core1_image }; + +/* regions for USB */ +define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1]; +define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end]; +place in USB_BDT_region { section m_usb_bdt }; +place in USB_SRAM_region { section m_usb_global }; + +initialize by copy { readwrite, section .textrw }; + +if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) +{ + /* Required in a multi-threaded application */ + initialize by copy with packing = none { section __DLIB_PERTHREAD }; +} + +do not initialize { section .noinit, section m_usb_bdt, section m_usb_global }; +if (isdefinedsymbol(__use_shmem__)) { + do not initialize { section rpmsg_sh_mem_section }; +} + +place at address mem: m_interrupts_start { readonly section .intvec }; +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; +place in VENEER_TABLE_region { section Veneer$$CMSE }; + +if (isdefinedsymbol(__use_shmem__)) { + place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; +} +place in core1_region { block CORE1_IMAGE_WBLOCK }; + diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/Secure/FreeRTOSDemo_s.ewd b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/Secure/FreeRTOSDemo_s.ewd new file mode 100644 index 000000000..b23ea7ac4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/Secure/FreeRTOSDemo_s.ewd @@ -0,0 +1,1554 @@ + + + 3 + + debug + + ARM + + 1 + + C-SPY + 2 + + 32 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 3 + 1 + 1 + + + + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 1 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 1 + + + + + + + + STLINK_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/Secure/FreeRTOSDemo_s.ewp b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/Secure/FreeRTOSDemo_s.ewp new file mode 100644 index 000000000..0ab1d3272 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/IAR/Secure/FreeRTOSDemo_s.ewp @@ -0,0 +1,1340 @@ + + + 3 + + debug + + ARM + + 1 + + General + 3 + + 35 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 1 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 27 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + + Config + + $PROJ_DIR$\..\Config\FreeRTOSConfig.h + + + + Demos + + reg_tests + + $PROJ_DIR$\..\..\..\..\Common\ARMv8M\reg_tests\IAR\ARM_CM33\secure\secure_reg_test.c + + + $PROJ_DIR$\..\..\..\..\Common\ARMv8M\reg_tests\IAR\ARM_CM33\secure\secure_reg_test_asm.h + + + $PROJ_DIR$\..\..\..\..\Common\ARMv8M\reg_tests\IAR\ARM_CM33\secure\secure_reg_test_asm.s + + + + + FreeRTOS + + portable + + IAR + + ARM_CM33 + + secure + + $PROJ_DIR$\..\..\..\..\..\Source\portable\IAR\ARM_CM33\secure\secure_context.c + + + $PROJ_DIR$\..\..\..\..\..\Source\portable\IAR\ARM_CM33\secure\secure_context.h + + + $PROJ_DIR$\..\..\..\..\..\Source\portable\IAR\ARM_CM33\secure\secure_context_port_asm.s + + + $PROJ_DIR$\..\..\..\..\..\Source\portable\IAR\ARM_CM33\secure\secure_heap.c + + + $PROJ_DIR$\..\..\..\..\..\Source\portable\IAR\ARM_CM33\secure\secure_heap.h + + + $PROJ_DIR$\..\..\..\..\..\Source\portable\IAR\ARM_CM33\secure\secure_init.c + + + $PROJ_DIR$\..\..\..\..\..\Source\portable\IAR\ARM_CM33\secure\secure_init.h + + + $PROJ_DIR$\..\..\..\..\..\Source\portable\IAR\ARM_CM33\secure\secure_port_macros.h + + + + + + + + NSC_Functions + + $PROJ_DIR$\..\..\..\..\Common\ARMv8M\tz_demo\nsc_functions.c + + + $PROJ_DIR$\..\..\..\..\Common\ARMv8M\tz_demo\nsc_functions.h + + + $PROJ_DIR$\..\..\..\NSC_Functions\nsc_printf.c + + + $PROJ_DIR$\..\..\..\NSC_Functions\nsc_printf.h + + + + NXP_Code + + board + + $PROJ_DIR$\..\..\..\NXP_Code\board\board.c + + + $PROJ_DIR$\..\..\..\NXP_Code\board\board.h + + + $PROJ_DIR$\..\..\..\NXP_Code\board\clock_config.c + + + $PROJ_DIR$\..\..\..\NXP_Code\board\clock_config.h + + + $PROJ_DIR$\..\..\..\NXP_Code\board\pin_mux.c + + + $PROJ_DIR$\..\..\..\NXP_Code\board\pin_mux.h + + + + CMSIS + + $PROJ_DIR$\..\..\..\NXP_Code\CMSIS\cmsis_compiler.h + + + $PROJ_DIR$\..\..\..\NXP_Code\CMSIS\cmsis_gcc.h + + + $PROJ_DIR$\..\..\..\NXP_Code\CMSIS\cmsis_iccarm.h + + + $PROJ_DIR$\..\..\..\NXP_Code\CMSIS\cmsis_version.h + + + $PROJ_DIR$\..\..\..\NXP_Code\CMSIS\core_cm33.h + + + $PROJ_DIR$\..\..\..\NXP_Code\CMSIS\mpu_armv8.h + + + $PROJ_DIR$\..\..\..\NXP_Code\CMSIS\tz_context.h + + + + component + + lists + + $PROJ_DIR$\..\..\..\NXP_Code\component\lists\fsl_component_generic_list.c + + + $PROJ_DIR$\..\..\..\NXP_Code\component\lists\fsl_component_generic_list.h + + + + uart + + $PROJ_DIR$\..\..\..\NXP_Code\component\uart\fsl_adapter_uart.h + + + $PROJ_DIR$\..\..\..\NXP_Code\component\uart\fsl_adapter_usart.c + + + + + device + + $PROJ_DIR$\..\..\..\NXP_Code\device\fsl_device_registers.h + + + $PROJ_DIR$\..\..\..\NXP_Code\device\LPC55S69_cm33_core0.h + + + $PROJ_DIR$\..\..\..\NXP_Code\device\LPC55S69_cm33_core0_features.h + + + $PROJ_DIR$\..\..\..\NXP_Code\device\system_LPC55S69_cm33_core0.c + + + $PROJ_DIR$\..\..\..\NXP_Code\device\system_LPC55S69_cm33_core0.h + + + + drivers + + $PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_clock.c + + + $PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_clock.h + + + $PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_common.c + + + $PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_common.h + + + $PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_common_arm.c + + + $PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_common_arm.h + + + $PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_flexcomm.c + + + $PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_flexcomm.h + + + $PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_gpio.c + + + $PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_gpio.h + + + $PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_iocon.h + + + $PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_power.c + + + $PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_power.h + + + $PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_reset.c + + + $PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_reset.h + + + $PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_usart.c + + + $PROJ_DIR$\..\..\..\NXP_Code\drivers\fsl_usart.h + + + + startup + + $PROJ_DIR$\..\..\..\NXP_Code\startup\startup_LPC55S69_cm33_core0.s + + + + trustzone + + $PROJ_DIR$\..\..\..\NXP_Code\trustzone\tzm_config.c + + + $PROJ_DIR$\..\..\..\NXP_Code\trustzone\tzm_config.h + + + + utilities + + $PROJ_DIR$\..\..\..\NXP_Code\utilities\fsl_assert.c + + + $PROJ_DIR$\..\..\..\NXP_Code\utilities\fsl_debug_console.c + + + $PROJ_DIR$\..\..\..\NXP_Code\utilities\fsl_debug_console.h + + + $PROJ_DIR$\..\..\..\NXP_Code\utilities\fsl_str.c + + + $PROJ_DIR$\..\..\..\NXP_Code\utilities\fsl_str.h + + + + + User + + $PROJ_DIR$\..\..\..\User\Secure\main_s.c + + + diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Config/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Config/FreeRTOSConfig.h index a1348de26..7d56eee98 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Config/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/Config/FreeRTOSConfig.h @@ -25,8 +25,8 @@ */ /****************************************************************************** - See http://www.freertos.org/a00110.html for an explanation of the - definitions contained in this file. + See http://www.freertos.org/a00110.html for an explanation of the + definitions contained in this file. ******************************************************************************/ #ifndef FREERTOS_CONFIG_H @@ -46,122 +46,122 @@ #include "clock_config.h" /* Cortex M33 port configuration. */ -#define configENABLE_MPU 1 -#define configENABLE_FPU 1 -#define configENABLE_TRUSTZONE 1 +#define configENABLE_MPU 1 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 1 /* Constants related to the behaviour or the scheduler. */ -#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 -#define configUSE_PREEMPTION 1 -#define configUSE_TIME_SLICING 1 -#define configMAX_PRIORITIES ( 5 ) -#define configIDLE_SHOULD_YIELD 1 -#define configUSE_16_BIT_TICKS 0 /* Only for 8 and 16-bit hardware. */ +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configUSE_PREEMPTION 1 +#define configUSE_TIME_SLICING 1 +#define configMAX_PRIORITIES ( 5 ) +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_16_BIT_TICKS 0 /* Only for 8 and 16-bit hardware. */ /* Constants that describe the hardware and memory usage. */ -#define configCPU_CLOCK_HZ BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK -#define configMINIMAL_STACK_SIZE ( ( uint16_t ) 128 ) -#define configMINIMAL_SECURE_STACK_SIZE ( 1024 ) -#define configMAX_TASK_NAME_LEN ( 12 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 50 * 1024 ) ) +#define configCPU_CLOCK_HZ BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK +#define configMINIMAL_STACK_SIZE ( ( uint16_t ) 128 ) +#define configMINIMAL_SECURE_STACK_SIZE ( 1024 ) +#define configMAX_TASK_NAME_LEN ( 12 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 50 * 1024 ) ) /* Constants that build features in or out. */ -#define configUSE_MUTEXES 1 -#define configUSE_TICKLESS_IDLE 1 -#define configUSE_APPLICATION_TASK_TAG 0 -#define configUSE_NEWLIB_REENTRANT 0 -#define configUSE_COUNTING_SEMAPHORES 1 -#define configUSE_RECURSIVE_MUTEXES 1 -#define configUSE_QUEUE_SETS 0 -#define configUSE_TASK_NOTIFICATIONS 1 -#define configUSE_TRACE_FACILITY 1 +#define configUSE_MUTEXES 1 +#define configUSE_TICKLESS_IDLE 1 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_TRACE_FACILITY 1 /* Constants that define which hook (callback) functions should be used. */ -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configUSE_MALLOC_FAILED_HOOK 0 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 /* Constants provided for debugging and optimisation assistance. */ -#define configCHECK_FOR_STACK_OVERFLOW 2 -#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } -#define configQUEUE_REGISTRY_SIZE 0 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } +#define configQUEUE_REGISTRY_SIZE 0 /* Software timer definitions. */ -#define configUSE_TIMERS 1 -#define configTIMER_TASK_PRIORITY ( 3 ) -#define configTIMER_QUEUE_LENGTH 5 -#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE ) +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( 3 ) +#define configTIMER_QUEUE_LENGTH 5 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE ) /* Set the following definitions to 1 to include the API function, or zero * to exclude the API function. NOTE: Setting an INCLUDE_ parameter to 0 is * only necessary if the linker does not automatically remove functions that are * not referenced anyway. */ -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 0 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 -#define INCLUDE_uxTaskGetStackHighWaterMark 0 -#define INCLUDE_xTaskGetIdleTaskHandle 0 -#define INCLUDE_eTaskGetState 1 -#define INCLUDE_xTaskResumeFromISR 0 -#define INCLUDE_xTaskGetCurrentTaskHandle 1 -#define INCLUDE_xTaskGetSchedulerState 0 -#define INCLUDE_xSemaphoreGetMutexHolder 0 -#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xTaskResumeFromISR 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xSemaphoreGetMutexHolder 0 +#define INCLUDE_xTimerPendFunctionCall 1 /* This demo makes use of one or more example stats formatting functions. These * format the raw data provided by the uxTaskGetSystemState() function in to * human readable ASCII form. See the notes in the implementation of vTaskList() * within FreeRTOS/Source/tasks.c for limitations. */ -#define configUSE_STATS_FORMATTING_FUNCTIONS 1 +#define configUSE_STATS_FORMATTING_FUNCTIONS 1 /* Dimensions a buffer that can be used by the FreeRTOS+CLI command interpreter. * See the FreeRTOS+CLI documentation for more information: * https://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_CLI/ */ -#define configCOMMAND_INT_MAX_OUTPUT_SIZE 2048 +#define configCOMMAND_INT_MAX_OUTPUT_SIZE 2048 /* Interrupt priority configuration follows...................... */ /* Use the system definition, if there is one. */ #ifdef __NVIC_PRIO_BITS - #define configPRIO_BITS __NVIC_PRIO_BITS + #define configPRIO_BITS __NVIC_PRIO_BITS #else - #define configPRIO_BITS 3 /* 8 priority levels. */ + #define configPRIO_BITS 3 /* 8 priority levels. */ #endif /* The lowest interrupt priority that can be used in a call to a "set priority" * function. */ -#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x07 +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x07 /* The highest interrupt priority that can be used by any interrupt service * routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT * CALL INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A * HIGHER PRIORITY THAN THIS! (higher priorities are lower numeric values). */ -#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5 +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5 /* Interrupt priorities used by the kernel port layer itself. These are generic * to all Cortex-M ports, and do not rely on any particular library functions. */ -#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << ( 8 - configPRIO_BITS ) ) +#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << ( 8 - configPRIO_BITS ) ) /* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! * See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ -#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << ( 8 - configPRIO_BITS ) ) +#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << ( 8 - configPRIO_BITS ) ) /* The #ifdef guards against the file being included from IAR assembly files. */ #ifndef __IASMARM__ - /* Constants related to the generation of run time stats. */ - #define configGENERATE_RUN_TIME_STATS 0 - #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() - #define portGET_RUN_TIME_COUNTER_VALUE() 0 - #define configTICK_RATE_HZ ( ( TickType_t ) 100 ) + /* Constants related to the generation of run time stats. */ + #define configGENERATE_RUN_TIME_STATS 0 + #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() + #define portGET_RUN_TIME_COUNTER_VALUE() 0 + #define configTICK_RATE_HZ ( ( TickType_t ) 100 ) #endif /* __IASMARM__ */ /* Enable static allocation. */ -#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_STATIC_ALLOCATION 1 #endif /* FREERTOS_CONFIG_H */ diff --git a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/.cproject b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/.cproject index e5ea92f11..9d63c2c65 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/.cproject +++ b/FreeRTOS/Demo/CORTEX_MPU_M33F_NXP_LPC55S69_MCUXpresso/Projects/MCUXpresso/NonSecure/.cproject @@ -115,6 +115,8 @@