1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
|
/* Copyright 2020 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
#include <metal/drivers/riscv_cpu.h>
#include <metal/hpm.h>
#include <stdint.h>
/* Macro to generate code within a switch case */
#define METAL_HPM_HANDLE_SWITCH(m) \
m(3) m(4) m(5) m(6) m(7) m(8) m(9) m(10) m(11) m(12) m(13) m(14) m(15) \
m(16) m(17) m(18) m(19) m(20) m(21) m(22) m(23) m(24) m(25) m(26) \
m(27) m(28) m(29) m(30) m(31)
/* Macro to set values into event selector register */
#define METAL_HPM_SET_EVENT_REG(x) \
case METAL_HPM_COUNTER_##x: \
__asm__ __volatile__("csrr %0, mhpmevent" #x : "=r"(val)); \
val &= ~bitmask; \
val |= bitmask; \
__asm__ __volatile__("csrw mhpmevent" #x ", %0" : : "r"(val)); \
break;
/* Macro to set values into event selector register */
#define METAL_HPM_CLR_EVENT_REG(x) \
case METAL_HPM_COUNTER_##x: \
__asm__ __volatile__("csrr %0, mhpmevent" #x : "=r"(val)); \
val &= ~bitmask; \
__asm__ __volatile__("csrw mhpmevent" #x ", %0" : : "r"(val)); \
break;
/* Macro to get values from event selector register */
#define METAL_HPM_GET_EVENT_REG(x) \
case METAL_HPM_COUNTER_##x: \
__asm__ __volatile__("csrr %0, mhpmevent" #x : "=r"(val)); \
break;
/* Macro to read HW performance monitor counter values */
#if __riscv_xlen == 32
#define METAL_HPM_GET_COUNT_REG(x) \
case METAL_HPM_COUNTER_##x: \
do { \
__asm__ __volatile__("csrr %0, mhpmcounter" #x "h" : "=r"(vh)); \
__asm__ __volatile__("csrr %0, mhpmcounter" #x : "=r"(vl)); \
__asm__ __volatile__("csrr %0, mhpmcounter" #x "h" : "=r"(vh1)); \
} while (vh != vh1); \
break;
#else
#define METAL_HPM_GET_COUNT_REG(x) \
case METAL_HPM_COUNTER_##x: \
__asm__ __volatile__("csrr %0, mhpmcounter" #x : "=r"(vl)); \
break;
#endif
/* Macro to clear HW performance monitor counter values */
#if __riscv_xlen == 32
#define METAL_HPM_CLR_COUNT_REG(x) \
case METAL_HPM_COUNTER_##x: \
__asm__ __volatile__("csrw mhpmcounter" #x "h, zero"); \
__asm__ __volatile__("csrw mhpmcounter" #x ", zero"); \
__asm__ __volatile__("csrw mhpmcounter" #x "h, zero"); \
break;
#else
#define METAL_HPM_CLR_COUNT_REG(x) \
case METAL_HPM_COUNTER_##x: \
__asm__ __volatile__("csrw mhpmcounter" #x ", zero"); \
break;
#endif
/* Max available counters */
#define METAL_HPM_COUNT_MAX 32
/* Macro to check for instruction trap */
#define MCAUSE_ILLEGAL_INST 0x02
/* Return codes */
#define METAL_HPM_RET_OK 0
#define METAL_HPM_RET_NOK 1
int metal_hpm_init(struct metal_cpu *gcpu) {
struct __metal_driver_cpu *cpu = (void *)gcpu;
/* Check if counters are initialized or pointer is NULL */
if ((gcpu) && (cpu->hpm_count == 0)) {
metal_hpm_counter n;
/* Count number of available hardware performance counters */
cpu->hpm_count = METAL_HPM_COUNT_MAX;
/* mcycle, mtime and minstret counters are always available */
for (n = METAL_HPM_COUNTER_3; n < METAL_HPM_COUNTER_31; n++) {
metal_hpm_set_event(gcpu, n, 0xFFFFFFFF);
if (metal_hpm_get_event(gcpu, n) == 0) {
break;
}
}
cpu->hpm_count = n;
/* TODO: mcountinhibit csr is not yet accessible.
* As per latest RiscV privileged spec v1.11,
* mcountinhibit controls which of the counters increment.
* Unused counters can be disabled to reduce power consumption. */
/* Keep all counters disabled, enable them later on as needed. */
/* __asm__ __volatile__("csrw mcountinhibit, zero"); */
/* Clear all counters */
for (unsigned int i = 0; i < cpu->hpm_count; i++) {
metal_hpm_clr_event(gcpu, i, 0xFFFFFFFF);
metal_hpm_clear_counter(gcpu, i);
}
} else {
return METAL_HPM_RET_NOK;
}
return METAL_HPM_RET_OK;
}
int metal_hpm_disable(struct metal_cpu *gcpu) {
struct __metal_driver_cpu *cpu = (void *)gcpu;
uintptr_t temp = 0, val = 0;
/* Check if pointer is NULL */
if (gcpu) {
/* Disable counter access */
__asm__ __volatile__("la %0, 1f \n\t"
"csrr %1, mtvec \n\t"
"csrw mtvec, %0 \n\t"
"csrw mcounteren, zero \n\t"
".align 4 \n\t"
"1: \n\t"
"csrw mtvec, %1 \n\t"
: "+r"(val), "+r"(temp));
/* TODO: Disable all counters */
/* __asm__ __volatile__("csrw mcountinhibit, zero"); */
cpu->hpm_count = 0;
} else {
return METAL_HPM_RET_NOK;
}
return METAL_HPM_RET_OK;
}
int metal_hpm_set_event(struct metal_cpu *gcpu, metal_hpm_counter counter,
unsigned int bitmask) {
struct __metal_driver_cpu *cpu = (void *)gcpu;
unsigned int val;
/* Return error if counter is out of range or pointer is NULL */
if ((gcpu) && (counter >= cpu->hpm_count))
return METAL_HPM_RET_NOK;
switch (counter) {
/* Set event register bit mask as requested */
METAL_HPM_HANDLE_SWITCH(METAL_HPM_SET_EVENT_REG)
default:
break;
}
return METAL_HPM_RET_OK;
}
unsigned int metal_hpm_get_event(struct metal_cpu *gcpu,
metal_hpm_counter counter) {
struct __metal_driver_cpu *cpu = (void *)gcpu;
unsigned int val = 0;
/* Return error if counter is out of range or pointer is NULL */
if ((gcpu) && (counter >= cpu->hpm_count))
return METAL_HPM_RET_NOK;
switch (counter) {
/* Read event registers */
METAL_HPM_HANDLE_SWITCH(METAL_HPM_GET_EVENT_REG)
default:
break;
}
return val;
}
int metal_hpm_clr_event(struct metal_cpu *gcpu, metal_hpm_counter counter,
unsigned int bitmask) {
struct __metal_driver_cpu *cpu = (void *)gcpu;
unsigned int val;
/* Return error if counter is out of range or pointer is NULL */
if ((gcpu) && (counter >= cpu->hpm_count))
return METAL_HPM_RET_NOK;
switch (counter) {
/* Clear event registers as requested */
METAL_HPM_HANDLE_SWITCH(METAL_HPM_CLR_EVENT_REG)
default:
break;
}
return METAL_HPM_RET_OK;
}
int metal_hpm_enable_access(struct metal_cpu *gcpu, metal_hpm_counter counter) {
struct __metal_driver_cpu *cpu = (void *)gcpu;
uintptr_t temp = 0, val = 0;
/* Return error if counter is out of range or pointer is NULL */
if ((gcpu) && (counter >= cpu->hpm_count))
return METAL_HPM_RET_NOK;
/* Set trap exit, to handle illegal instruction trap. */
__asm__ __volatile__("la %0, 1f \n\t"
"csrr %1, mtvec \n\t"
"csrw mtvec, %0 \n\t"
"csrr %0, mcounteren \n\t"
"or %0, %0, %2 \n\t"
"csrw mcounteren, %0 \n\t"
".align 4 \n\t"
"1: \n\t"
"csrw mtvec, %1 \n\t"
: "+r"(val), "+r"(temp)
: "r"(1 << counter));
return METAL_HPM_RET_OK;
}
int metal_hpm_disable_access(struct metal_cpu *gcpu,
metal_hpm_counter counter) {
struct __metal_driver_cpu *cpu = (void *)gcpu;
uintptr_t temp = 0, val = 0;
/* Return error if counter is out of range or pointer is NULL */
if ((gcpu) && (counter >= cpu->hpm_count))
return METAL_HPM_RET_NOK;
/* Set trap exit, to handle illegal instruction trap. */
__asm__ __volatile__("la %0, 1f \n\t"
"csrr %1, mtvec \n\t"
"csrw mtvec, %0 \n\t"
"csrr %0, mcounteren \n\t"
"and %0, %0, %2 \n\t"
"csrw mcounteren, %0 \n\t"
".align 4 \n\t"
"1: \n\t"
"csrw mtvec, %1 \n\t"
: "+r"(val), "+r"(temp)
: "r"(~(1 << counter)));
return METAL_HPM_RET_OK;
}
unsigned long long metal_hpm_read_counter(struct metal_cpu *gcpu,
metal_hpm_counter counter) {
struct __metal_driver_cpu *cpu = (void *)gcpu;
#if __riscv_xlen == 32
unsigned int vh = 0, vh1 = 0, vl = 0;
#else
unsigned long long vl = 0;
#endif
/* Return error if counter is out of range or pointer is NULL */
if ((gcpu) && (counter >= cpu->hpm_count))
return METAL_HPM_RET_NOK;
switch (counter) {
case METAL_HPM_CYCLE:
#if __riscv_xlen == 32
do {
__asm__ __volatile__("csrr %0, mcycleh" : "=r"(vh));
__asm__ __volatile__("csrr %0, mcycle" : "=r"(vl));
__asm__ __volatile__("csrr %0, mcycleh" : "=r"(vh1));
} while (vh != vh1);
#else
__asm__ __volatile__("csrr %0, mcycle" : "=r"(vl));
#endif
break;
case METAL_HPM_TIME:
/* mtime is memory mapped within CLINT block,
* Use CLINT APIs to access this register. */
return METAL_HPM_RET_NOK;
break;
case METAL_HPM_INSTRET:
#if __riscv_xlen == 32
do {
__asm__ __volatile__("csrr %0, minstreth" : "=r"(vh));
__asm__ __volatile__("csrr %0, minstret" : "=r"(vl));
__asm__ __volatile__("csrr %0, minstreth" : "=r"(vh1));
} while (vh != vh1);
#else
__asm__ __volatile__("csrr %0, minstret" : "=r"(vl));
#endif
break;
METAL_HPM_HANDLE_SWITCH(METAL_HPM_GET_COUNT_REG)
default:
break;
}
#if __riscv_xlen == 32
return ((((unsigned long long)vh) << 32) | vl);
#else
return vl;
#endif
}
int metal_hpm_clear_counter(struct metal_cpu *gcpu, metal_hpm_counter counter) {
struct __metal_driver_cpu *cpu = (void *)gcpu;
/* Return error if counter is out of range or pointer is NULL */
if ((gcpu) && (counter >= cpu->hpm_count))
return METAL_HPM_RET_NOK;
switch (counter) {
case METAL_HPM_CYCLE:
#if __riscv_xlen == 32
__asm__ __volatile__("csrw mcycleh, zero");
__asm__ __volatile__("csrw mcycle, zero");
__asm__ __volatile__("csrw mcycleh, zero");
#else
__asm__ __volatile__("csrw mcycle, zero");
#endif
break;
case METAL_HPM_TIME:
/* mtime is memory mapped within CLINT block */
return METAL_HPM_RET_NOK;
break;
case METAL_HPM_INSTRET:
#if __riscv_xlen == 32
__asm__ __volatile__("csrw minstreth, zero");
__asm__ __volatile__("csrw minstret, zero");
__asm__ __volatile__("csrw minstreth, zero");
#else
__asm__ __volatile__("csrw minstret, zero");
#endif
break;
METAL_HPM_HANDLE_SWITCH(METAL_HPM_CLR_COUNT_REG)
default:
break;
}
return METAL_HPM_RET_OK;
}
|
