Update BSP source files for UltraScale Cortex-A53 and Cortex-R5 and Microblaze to the 2016.4 versions.

Correct alignment issue in GCC Cortex-R port that was preventing full floating point usage in interrupts (other ports will be updated likewise). Update the UltraScale R5 demo to test the GCC Cortex-A9 port layer modification mentioned on the line above. git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2480 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
author: rtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2> 2017-01-19 04:11:21 +0000
committer: rtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2> 2017-01-19 04:11:21 +0000
commit: 4e30ef7c7f124be2098e1547438d5fd7cb067830 (patch)
tree: 8195f00ea5a59be9acbc668a0422ee252a8456c0
parent: 64addb5a73e5f925fec27252c63a290f8ba4cc3b (diff)
download: freertos-4e30ef7c7f124be2098e1547438d5fd7cb067830.tar.gz
267 files changed, 8326 insertions, 2156 deletions
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/.cproject b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/.cproject
index 6e3a6cb23..f0c9f2a32 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/.cproject
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/.cproject
@@ -20,7 +20,7 @@
 							<targetPlatform binaryParser="com.xilinx.sdk.managedbuilder.XELF.arm.a53" id="xilinx.arm.a53.target.gnu.base.debug.565045804" isAbstract="false" name="Debug Platform" superClass="xilinx.arm.a53.target.gnu.base.debug"/>
 							<builder buildPath="${workspace_loc:/RTOSDemo_A53}/Debug" enableAutoBuild="true" id="xilinx.gnu.arm.a53.toolchain.builder.debug.1503003921" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="GNU make" superClass="xilinx.gnu.arm.a53.toolchain.builder.debug"/>
 							<tool id="xilinx.gnu.arm.a53.c.toolchain.assembler.debug.1142300561" name="ARM A53 gcc assembler" superClass="xilinx.gnu.arm.a53.c.toolchain.assembler.debug">
-								<option id="xilinx.gnu.both.assembler.option.flags.139020974" superClass="xilinx.gnu.both.assembler.option.flags" value="-Wa, --gdwarf2" valueType="string"/>
+								<option id="xilinx.gnu.both.assembler.option.flags.139020974" name="Assembler Flags" superClass="xilinx.gnu.both.assembler.option.flags" value="-Wa, --gdwarf2" valueType="string"/>
 								<inputType id="xilinx.gnu.assembler.input.478741574" superClass="xilinx.gnu.assembler.input"/>
 							</tool>
 							<tool id="xilinx.gnu.arm.a53.c.toolchain.compiler.debug.587400676" name="ARM A53 gcc compiler" superClass="xilinx.gnu.arm.a53.c.toolchain.compiler.debug">
@@ -29,14 +29,15 @@
 								<option id="xilinx.gnu.compiler.inferred.swplatform.includes.1218722002" name="Software Platform Include Path" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
 									<listOptionValue builtIn="false" value="../../RTOSDemo_A53_bsp/psu_cortexa53_0/include"/>
 								</option>
-								<option id="xilinx.gnu.compiler.dircategory.includes.959905810" superClass="xilinx.gnu.compiler.dircategory.includes" valueType="includePath">
+								<option id="xilinx.gnu.compiler.dircategory.includes.959905810" name="Include Paths" superClass="xilinx.gnu.compiler.dircategory.includes" valueType="includePath">
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/src/FreeRTOS_Source/include}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/src/FreeRTOS_Source/portable/GCC/ARM_CA53_64_BIT}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/src/Full_Demo}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/src/Full_Demo/Standard_Demo_Tasks/include}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/src}&quot;"/>
 								</option>
-								<option id="xilinx.gnu.compiler.misc.other.1651312713" superClass="xilinx.gnu.compiler.misc.other" value="-c -fmessage-length=0 -MT&quot;$@&quot; -fno-builtin" valueType="string"/>
+								<option id="xilinx.gnu.compiler.misc.other.1651312713" name="Other flags" superClass="xilinx.gnu.compiler.misc.other" value="-c -fmessage-length=0 -MT&quot;$@&quot; -fno-builtin" valueType="string"/>
+								<option id="xilinx.gnu.compiler.symbols.defined.890730491" name="Defined symbols (-D)" superClass="xilinx.gnu.compiler.symbols.defined" valueType="definedSymbols"/>
 								<inputType id="xilinx.gnu.arm.a53.c.compiler.input.1725216366" name="C source files" superClass="xilinx.gnu.arm.a53.c.compiler.input"/>
 							</tool>
 							<tool id="xilinx.gnu.arm.a53.cxx.toolchain.compiler.debug.986847379" name="ARM A53 g++ compiler" superClass="xilinx.gnu.arm.a53.cxx.toolchain.compiler.debug">
@@ -55,6 +56,7 @@
 									<listOptionValue builtIn="false" value="-Wl,--start-group,-lxil,-lgcc,-lc,--end-group"/>
 								</option>
 								<option id="xilinx.gnu.c.linker.option.lscript.210457854" name="Linker Script" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
+								<option id="xilinx.gnu.c.link.option.other.791632065" name="Other options (-XLinker [option])" superClass="xilinx.gnu.c.link.option.other" valueType="stringList"/>
 								<inputType id="xilinx.gnu.linker.input.294386883" superClass="xilinx.gnu.linker.input">
 									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
 									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
@@ -164,4 +166,5 @@
 			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMA53GCCManagedMakePerProjectProfileC"/>
 		</scannerConfigBuildInfo>
 	</storageModule>
+	<storageModule moduleId="refreshScope"/>
 </cproject>
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/main.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/main.c
index 853527563..887e9688e 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/main.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/main.c
@@ -288,64 +288,6 @@ static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ];
 }
 /*-----------------------------------------------------------*/
 
-void *memcpy( void *pvDest, const void *pvSource, size_t xBytes )
-{
-/* The compiler used during development seems to err unless these volatiles are
-included at -O3 optimisation.  */
-volatile unsigned char *pcDest = ( volatile unsigned char * ) pvDest, *pcSource = ( volatile unsigned char * ) pvSource;
-size_t x;
-
-	/* Extremely crude standard library implementations in lieu of having a C
-	library. */
-	if( pvDest != pvSource )
-	{
-		for( x = 0; x < xBytes; x++ )
-		{
-			pcDest[ x ] = pcSource[ x ];
-		}
-	}
-
-	return pvDest;
-}
-/*-----------------------------------------------------------*/
-
-void *memset( void *pvDest, int iValue, size_t xBytes )
-{
-/* The compiler used during development seems to err unless these volatiles are
-included at -O3 optimisation.  */
-volatile unsigned char * volatile pcDest = ( volatile unsigned char * volatile ) pvDest;
-volatile size_t x;
-
-	/* Extremely crude standard library implementations in lieu of having a C
-	library. */
-	for( x = 0; x < xBytes; x++ )
-	{
-		pcDest[ x ] = ( unsigned char ) iValue;
-	}
-
-	return pvDest;
-}
-/*-----------------------------------------------------------*/
-
-int memcmp( const void *pvMem1, const void *pvMem2, size_t xBytes )
-{
-const volatile unsigned char *pucMem1 = pvMem1, *pucMem2 = pvMem2;
-volatile size_t x;
-
-	/* Extremely crude standard library implementations in lieu of having a C
-	library. */
-    for( x = 0; x < xBytes; x++ )
-    {
-        if( pucMem1[ x ] != pucMem2[ x ] )
-        {
-            break;
-        }
-    }
-
-    return xBytes - x;
-}
-/*-----------------------------------------------------------*/
-
 void vMainAssertCalled( const char *pcFileName, uint32_t ulLineNumber )
 {
 	xil_printf( "ASSERT!  Line %lu of file %s\r\n", ulLineNumber, pcFileName );
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xparameters.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xparameters.h
index 7d8be3152..f9fa7224b 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xparameters.h
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xparameters.h
@@ -260,12 +260,12 @@
 #define XPAR_PSU_ETHERNET_3_BASEADDR 0xFF0E0000
 #define XPAR_PSU_ETHERNET_3_HIGHADDR 0xFF0EFFFF
 #define XPAR_PSU_ETHERNET_3_ENET_CLK_FREQ_HZ 124998749
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0 50000000
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV1 50000000
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV0 50000000
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV1 50000000
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV0 50000000
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV1 50000000
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0 12
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV1 1
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV0 60
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV1 1
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV0 60
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV1 10
 
 
 /******************************************************************/
@@ -275,12 +275,12 @@
 #define XPAR_XEMACPS_0_BASEADDR 0xFF0E0000
 #define XPAR_XEMACPS_0_HIGHADDR 0xFF0EFFFF
 #define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 124998749
-#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 50000000
-#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 50000000
-#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 50000000
-#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 50000000
-#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 50000000
-#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50000000
+#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 12
+#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1
+#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 60
+#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 1
+#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 60
+#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 10
 
 
 /******************************************************************/
@@ -452,8 +452,6 @@
 
 
 /* Definitions for peripheral PSU_IOU_S */
-#define XPAR_PSU_IOU_S_S_AXI_BASEADDR 0xFF000000
-#define XPAR_PSU_IOU_S_S_AXI_HIGHADDR 0xFF2AFFFF
 
 
 /* Definitions for peripheral PSU_IOU_SCNTR */
@@ -512,8 +510,6 @@
 
 
 /* Definitions for peripheral PSU_OCM_RAM_1 */
-#define XPAR_PSU_OCM_RAM_1_S_AXI_BASEADDR 0xFFFF0000
-#define XPAR_PSU_OCM_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF
 
 
 /* Definitions for peripheral PSU_OCM_XMPU_CFG */
@@ -651,7 +647,7 @@
 
 /******************************************************************/
 
-#define  XPAR_XIPIPSU_NUM_INSTANCES  1
+#define  XPAR_XIPIPSU_NUM_INSTANCES  3
 
 /* Parameter definitions for peripheral psu_ipi_0 */
 #define  XPAR_PSU_IPI_0_DEVICE_ID  0
@@ -660,6 +656,20 @@
 #define  XPAR_PSU_IPI_0_BUFFER_INDEX  2
 #define  XPAR_PSU_IPI_0_INT_ID  67
 
+/* Parameter definitions for peripheral psu_ipi_1 */
+#define  XPAR_PSU_IPI_1_DEVICE_ID  1
+#define  XPAR_PSU_IPI_1_BASE_ADDRESS  0xFF310000
+#define  XPAR_PSU_IPI_1_BIT_MASK  0x00000100
+#define  XPAR_PSU_IPI_1_BUFFER_INDEX  0
+#define  XPAR_PSU_IPI_1_INT_ID  65
+
+/* Parameter definitions for peripheral psu_ipi_2 */
+#define  XPAR_PSU_IPI_2_DEVICE_ID  2
+#define  XPAR_PSU_IPI_2_BASE_ADDRESS  0xFF320000
+#define  XPAR_PSU_IPI_2_BIT_MASK  0x00000200
+#define  XPAR_PSU_IPI_2_BUFFER_INDEX  1
+#define  XPAR_PSU_IPI_2_INT_ID  66
+
 /* Canonical definitions for peripheral psu_ipi_0 */
 #define  XPAR_XIPIPSU_0_DEVICE_ID	XPAR_PSU_IPI_0_DEVICE_ID
 #define  XPAR_XIPIPSU_0_BASE_ADDRESS	XPAR_PSU_IPI_0_BASE_ADDRESS
@@ -667,6 +677,20 @@
 #define  XPAR_XIPIPSU_0_BUFFER_INDEX	XPAR_PSU_IPI_0_BUFFER_INDEX
 #define  XPAR_XIPIPSU_0_INT_ID	XPAR_PSU_IPI_0_INT_ID
 
+/* Canonical definitions for peripheral psu_ipi_1 */
+#define  XPAR_XIPIPSU_1_DEVICE_ID	XPAR_PSU_IPI_1_DEVICE_ID
+#define  XPAR_XIPIPSU_1_BASE_ADDRESS	XPAR_PSU_IPI_1_BASE_ADDRESS
+#define  XPAR_XIPIPSU_1_BIT_MASK	XPAR_PSU_IPI_1_BIT_MASK
+#define  XPAR_XIPIPSU_1_BUFFER_INDEX	XPAR_PSU_IPI_1_BUFFER_INDEX
+#define  XPAR_XIPIPSU_1_INT_ID	XPAR_PSU_IPI_1_INT_ID
+
+/* Canonical definitions for peripheral psu_ipi_2 */
+#define  XPAR_XIPIPSU_2_DEVICE_ID	XPAR_PSU_IPI_2_DEVICE_ID
+#define  XPAR_XIPIPSU_2_BASE_ADDRESS	XPAR_PSU_IPI_2_BASE_ADDRESS
+#define  XPAR_XIPIPSU_2_BIT_MASK	XPAR_PSU_IPI_2_BIT_MASK
+#define  XPAR_XIPIPSU_2_BUFFER_INDEX	XPAR_PSU_IPI_2_BUFFER_INDEX
+#define  XPAR_XIPIPSU_2_INT_ID	XPAR_PSU_IPI_2_INT_ID
+
 #define  XPAR_XIPIPSU_NUM_TARGETS  11
 
 #define  XPAR_PSU_IPI_0_BIT_MASK  0x00000001
@@ -695,15 +719,31 @@
 
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_MASK  XPAR_PSU_IPI_0_BIT_MASK
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_INDEX  0
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH1_MASK  XPAR_PSU_IPI_1_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH1_INDEX  1
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH2_MASK  XPAR_PSU_IPI_2_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH2_INDEX  2
 
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_MASK  XPAR_PSU_IPI_0_BIT_MASK
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_INDEX  0
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH1_MASK  XPAR_PSU_IPI_1_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH1_INDEX  1
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH2_MASK  XPAR_PSU_IPI_2_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH2_INDEX  2
 
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_MASK  XPAR_PSU_IPI_0_BIT_MASK
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_INDEX  0
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH1_MASK  XPAR_PSU_IPI_1_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH1_INDEX  1
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH2_MASK  XPAR_PSU_IPI_2_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH2_INDEX  2
 
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_MASK  XPAR_PSU_IPI_0_BIT_MASK
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_INDEX  0
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH1_MASK  XPAR_PSU_IPI_1_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH1_INDEX  1
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH2_MASK  XPAR_PSU_IPI_2_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH2_INDEX  2
 
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_MASK  XPAR_PSU_IPI_1_BIT_MASK
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_INDEX  1
@@ -715,14 +755,18 @@
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH1_MASK  XPAR_PSU_IPI_2_BIT_MASK
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH1_INDEX  2
 
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_MASK  XPAR_PSU_IPI_3_BIT_MASK
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_INDEX  3
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_MASK  XPAR_PSU_IPI_4_BIT_MASK
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_INDEX  4
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_MASK  XPAR_PSU_IPI_5_BIT_MASK
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_INDEX  5
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_MASK  XPAR_PSU_IPI_6_BIT_MASK
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_INDEX  6
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_MASK  XPAR_PSU_IPI_1_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_INDEX  1
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_MASK  XPAR_PSU_IPI_2_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_INDEX  2
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_MASK  XPAR_PSU_IPI_3_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_INDEX  3
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_MASK  XPAR_PSU_IPI_4_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_INDEX  4
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH4_MASK  XPAR_PSU_IPI_5_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH4_INDEX  5
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH5_MASK  XPAR_PSU_IPI_6_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH5_INDEX  6
 
 /* Definitions for driver QSPIPSU */
 #define XPAR_XQSPIPSU_NUM_INSTANCES 1
@@ -1010,14 +1054,14 @@
 #define XPAR_PSU_WDT_0_DEVICE_ID 0
 #define XPAR_PSU_WDT_0_BASEADDR 0xFF150000
 #define XPAR_PSU_WDT_0_HIGHADDR 0xFF15FFFF
-#define XPAR_PSU_WDT_0_WDT_CLK_FREQ_HZ 25000000
+#define XPAR_PSU_WDT_0_WDT_CLK_FREQ_HZ 99999001
 
 
 /* Definitions for peripheral PSU_WDT_1 */
 #define XPAR_PSU_WDT_1_DEVICE_ID 1
 #define XPAR_PSU_WDT_1_BASEADDR 0xFD4D0000
 #define XPAR_PSU_WDT_1_HIGHADDR 0xFD4DFFFF
-#define XPAR_PSU_WDT_1_WDT_CLK_FREQ_HZ 25000000
+#define XPAR_PSU_WDT_1_WDT_CLK_FREQ_HZ 99999001
 
 
 /******************************************************************/
@@ -1026,13 +1070,13 @@
 #define XPAR_XWDTPS_0_DEVICE_ID XPAR_PSU_WDT_0_DEVICE_ID
 #define XPAR_XWDTPS_0_BASEADDR 0xFF150000
 #define XPAR_XWDTPS_0_HIGHADDR 0xFF15FFFF
-#define XPAR_XWDTPS_0_WDT_CLK_FREQ_HZ 25000000
+#define XPAR_XWDTPS_0_WDT_CLK_FREQ_HZ 99999001
 
 /* Canonical definitions for peripheral PSU_WDT_1 */
 #define XPAR_XWDTPS_1_DEVICE_ID XPAR_PSU_WDT_1_DEVICE_ID
 #define XPAR_XWDTPS_1_BASEADDR 0xFD4D0000
 #define XPAR_XWDTPS_1_HIGHADDR 0xFD4DFFFF
-#define XPAR_XWDTPS_1_WDT_CLK_FREQ_HZ 25000000
+#define XPAR_XWDTPS_1_WDT_CLK_FREQ_HZ 99999001
 
 
 /******************************************************************/
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_4/src/xaxipmon_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_4/src/xaxipmon_g.c
index a33878ef5..2bd473dd5 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_4/src/xaxipmon_g.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_4/src/xaxipmon_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_1/src/xcanps_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_1/src/xcanps_g.c
index b45c5b2d6..4063a44eb 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_1/src/xcanps_g.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_1/src/xcanps_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_0/src/xcsudma_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_0/src/xcsudma_g.c
index b3fb65f5b..09e7f739a 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_0/src/xcsudma_g.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_0/src/xcsudma_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_2/src/xemacps_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_2/src/xemacps_g.c
index 6a7cc7866..db734b924 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_2/src/xemacps_g.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_2/src/xemacps_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_1/src/xgpiops_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_1/src/xgpiops_g.c
index 597b38a12..38a5b9355 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_1/src/xgpiops_g.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_1/src/xgpiops_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_1/src/xiicps_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_1/src/xiicps_g.c
index 50f1c1413..f449e0ed6 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_1/src/xiicps_g.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_1/src/xiicps_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_0/src/xipipsu_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_0/src/xipipsu_g.c
index 6d32d1dc7..7845cb5b7 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_0/src/xipipsu_g.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_0/src/xipipsu_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
@@ -101,5 +101,117 @@ XIpiPsu_Config XIpiPsu_ConfigTable[] =
 				XPAR_PSU_IPI_10_BUFFER_INDEX
 			}
 		}
+	},
+
+	{
+		XPAR_PSU_IPI_1_DEVICE_ID,
+		XPAR_PSU_IPI_1_BASE_ADDRESS,
+		XPAR_PSU_IPI_1_BIT_MASK,
+		XPAR_PSU_IPI_1_BUFFER_INDEX,
+		XPAR_PSU_IPI_1_INT_ID,
+		XPAR_XIPIPSU_NUM_TARGETS,
+		{
+
+			{
+				XPAR_PSU_IPI_0_BIT_MASK,
+				XPAR_PSU_IPI_0_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_1_BIT_MASK,
+				XPAR_PSU_IPI_1_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_2_BIT_MASK,
+				XPAR_PSU_IPI_2_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_3_BIT_MASK,
+				XPAR_PSU_IPI_3_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_4_BIT_MASK,
+				XPAR_PSU_IPI_4_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_5_BIT_MASK,
+				XPAR_PSU_IPI_5_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_6_BIT_MASK,
+				XPAR_PSU_IPI_6_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_7_BIT_MASK,
+				XPAR_PSU_IPI_7_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_8_BIT_MASK,
+				XPAR_PSU_IPI_8_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_9_BIT_MASK,
+				XPAR_PSU_IPI_9_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_10_BIT_MASK,
+				XPAR_PSU_IPI_10_BUFFER_INDEX
+			}
+		}
+	},
+
+	{
+		XPAR_PSU_IPI_2_DEVICE_ID,
+		XPAR_PSU_IPI_2_BASE_ADDRESS,
+		XPAR_PSU_IPI_2_BIT_MASK,
+		XPAR_PSU_IPI_2_BUFFER_INDEX,
+		XPAR_PSU_IPI_2_INT_ID,
+		XPAR_XIPIPSU_NUM_TARGETS,
+		{
+
+			{
+				XPAR_PSU_IPI_0_BIT_MASK,
+				XPAR_PSU_IPI_0_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_1_BIT_MASK,
+				XPAR_PSU_IPI_1_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_2_BIT_MASK,
+				XPAR_PSU_IPI_2_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_3_BIT_MASK,
+				XPAR_PSU_IPI_3_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_4_BIT_MASK,
+				XPAR_PSU_IPI_4_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_5_BIT_MASK,
+				XPAR_PSU_IPI_5_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_6_BIT_MASK,
+				XPAR_PSU_IPI_6_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_7_BIT_MASK,
+				XPAR_PSU_IPI_7_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_8_BIT_MASK,
+				XPAR_PSU_IPI_8_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_9_BIT_MASK,
+				XPAR_PSU_IPI_9_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_10_BIT_MASK,
+				XPAR_PSU_IPI_10_BUFFER_INDEX
+			}
+		}
 	}
 };
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_0/src/xqspipsu_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_0/src/xqspipsu_g.c
index daa5bde27..969fa96b0 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_0/src/xqspipsu_g.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_0/src/xqspipsu_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_g.c
index 8dc37775a..5913cd8d4 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_g.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_2/src/xscugic_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_2/src/xscugic_g.c
index 2acea2b51..ff1955d3a 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_2/src/xscugic_g.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_2/src/xscugic_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v2_7/src/xsdps_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v2_7/src/xsdps_g.c
index b5d2e4be8..34c589039 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v2_7/src/xsdps_g.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v2_7/src/xsdps_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/bspconfig.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/bspconfig.h
index 4dd178f04..8671e3fbe 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/bspconfig.h
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v5_4/src/bspconfig.h
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_g.c
index ace39e369..b692531ad 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_g.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_1/src/xttcps_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_1/src/xttcps_g.c
index 10c16eb02..28d356092 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_1/src/xttcps_g.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_1/src/xttcps_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_1/src/xuartps_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_1/src/xuartps_g.c
index 94aaf5b2e..d4a8e5ab9 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_1/src/xuartps_g.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_1/src/xuartps_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/wdtps_v3_0/src/xwdtps_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/wdtps_v3_0/src/xwdtps_g.c
index 5147be676..6ea6b192b 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/wdtps_v3_0/src/xwdtps_g.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/wdtps_v3_0/src/xwdtps_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_1/src/xzdma_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_1/src/xzdma_g.c
index 33202264d..194aac12e 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_1/src/xzdma_g.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_1/src/xzdma_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/Full_Demo/main_full.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/Full_Demo/main_full.c
index fb6114afc..bcd6d1ada 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/Full_Demo/main_full.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/Full_Demo/main_full.c
@@ -496,6 +496,23 @@ void vFullDemoTickHook( void )
 
 	/* Call the code that 'gives' a task notification from an ISR. */
 	xNotifyTaskFromISR();
+
+	/* Test flop alignment in interrupts - calling printf from an interrupt
+	is BAD! */
+	#if( configASSERT_DEFINED == 1 )
+	{
+	char cBuf[ 20 ];
+	UBaseType_t uxSavedInterruptStatus;
+
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			sprintf( cBuf, "%1.3f", 1.234 );
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+		configASSERT( strcmp( cBuf, "1.234" ) == 0 );
+	}
+	#endif /* configASSERT_DEFINED */
 }
 
 
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.cproject b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.cproject
index 25054143d..d73fe8014 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.cproject
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.cproject
@@ -1,8 +1,8 @@
 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
 <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
 	<storageModule moduleId="org.eclipse.cdt.core.settings">
-		<cconfiguration id="org.eclipse.cdt.core.default.config.750804140">
-			<storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.750804140" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
+		<cconfiguration id="org.eclipse.cdt.core.default.config.887738538">
+			<storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.887738538" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
 				<externalSettings/>
 				<extensions/>
 			</storageModule>
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.project b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.project
index be846c648..ed0ff0ff0 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.project
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.project
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <projectDescription>
 	<name>RTOSDemo_R5_bsp</name>
-	<comment>Created by SDK v2016.1</comment>
+	<comment>Created by SDK v2016.4</comment>
 	<projects>
 	</projects>
 	<buildSpec>
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/Makefile
index 91c3fcf13..071f646d1 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/Makefile
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/Makefile
@@ -21,11 +21,11 @@ $(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a
 
 %/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,)
 	@echo "Running Make include in $(subst /make.include,,$@)"
-	$(MAKE) -C $(subst /make.include,,$@) -s include  "SHELL=$(SHELL)" "COMPILER=armr5-none-eabi-gcc" "ARCHIVER=armr5-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=cortex-r5" "EXTRA_COMPILER_FLAGS=-g -DARMR5 -mfpu=vfpv3-d16"
+	$(MAKE) -C $(subst /make.include,,$@) -s include  "SHELL=$(SHELL)" "COMPILER=armr5-none-eabi-gcc" "ARCHIVER=armr5-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=cortex-r5" "EXTRA_COMPILER_FLAGS=-g -DARMR5"
 
 %/make.libs: include
 	@echo "Running Make libs in $(subst /make.libs,,$@)"
-	$(MAKE) -C $(subst /make.libs,,$@) -s libs  "SHELL=$(SHELL)" "COMPILER=armr5-none-eabi-gcc" "ARCHIVER=armr5-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=cortex-r5" "EXTRA_COMPILER_FLAGS=-g -DARMR5 -mfpu=vfpv3-d16"
+	$(MAKE) -C $(subst /make.libs,,$@) -s libs  "SHELL=$(SHELL)" "COMPILER=armr5-none-eabi-gcc" "ARCHIVER=armr5-none-eabi-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=cortex-r5" "EXTRA_COMPILER_FLAGS=-g -DARMR5"
 
 clean:
 	rm -f ${PROCESSOR}/lib/libxil.a
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/include/xparameters.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/include/xparameters.h
index 7e9e79ff2..efc88f158 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/include/xparameters.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/include/xparameters.h
@@ -13,6 +13,9 @@
 
 /******************************************************************/
 
+ /* Definition for PSS REF CLK FREQUENCY */
+#define XPAR_PSU_PSS_REF_CLK_FREQ_HZ 33333000U
+
 #include "xparameters_ps.h"
 
 /******************************************************************/
@@ -27,6 +30,10 @@
 
 /******************************************************************/
 
+
+/* Number of Fabric Resets */
+#define XPAR_NUM_FABRIC_RESETS 1
+
 #define STDIN_BASEADDRESS 0xFF000000
 #define STDOUT_BASEADDRESS 0xFF000000
 
@@ -262,6 +269,28 @@
 
 /******************************************************************/
 
+/* Definitions for driver DDRCPSU */
+#define XPAR_XDDRCPSU_NUM_INSTANCES 1
+
+/* Definitions for peripheral PSU_DDRC_0 */
+#define XPAR_PSU_DDRC_0_DEVICE_ID 0
+#define XPAR_PSU_DDRC_0_BASEADDR 0xFD070000
+#define XPAR_PSU_DDRC_0_HIGHADDR 0xFD070FFF
+#define XPAR_PSU_DDRC_0_HAS_ECC 0
+#define XPAR_PSU_DDRC_0_DDRC_CLK_FREQ_HZ 533328002
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PSU_DDRC_0 */
+#define XPAR_DDRCPSU_0_DEVICE_ID XPAR_PSU_DDRC_0_DEVICE_ID
+#define XPAR_DDRCPSU_0_BASEADDR 0xFD070000
+#define XPAR_DDRCPSU_0_HIGHADDR 0xFD070FFF
+#define XPAR_DDRCPSU_0_DDRC_CLK_FREQ_HZ 533328002
+
+
+/******************************************************************/
+
 /* Definitions for driver EMACPS */
 #define XPAR_XEMACPS_NUM_INSTANCES 1
 
@@ -270,12 +299,12 @@
 #define XPAR_PSU_ETHERNET_3_BASEADDR 0xFF0E0000
 #define XPAR_PSU_ETHERNET_3_HIGHADDR 0xFF0EFFFF
 #define XPAR_PSU_ETHERNET_3_ENET_CLK_FREQ_HZ 124998749
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0 50000000
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV1 50000000
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV0 50000000
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV1 50000000
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV0 50000000
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV1 50000000
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0 12
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV1 1
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV0 60
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV1 1
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV0 60
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV1 10
 
 
 /******************************************************************/
@@ -285,12 +314,12 @@
 #define XPAR_XEMACPS_0_BASEADDR 0xFF0E0000
 #define XPAR_XEMACPS_0_HIGHADDR 0xFF0EFFFF
 #define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 124998749
-#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 50000000
-#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 50000000
-#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 50000000
-#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 50000000
-#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 50000000
-#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50000000
+#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 12
+#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1
+#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 60
+#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 1
+#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 60
+#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 10
 
 
 /******************************************************************/
@@ -336,11 +365,6 @@
 #define XPAR_PSU_APU_S_AXI_HIGHADDR 0xFD5CFFFF
 
 
-/* Definitions for peripheral PSU_BBRAM_0 */
-#define XPAR_PSU_BBRAM_0_S_AXI_BASEADDR 0xFFCD0000
-#define XPAR_PSU_BBRAM_0_S_AXI_HIGHADDR 0xFFCDFFFF
-
-
 /* Definitions for peripheral PSU_CCI_GPV */
 #define XPAR_PSU_CCI_GPV_S_AXI_BASEADDR 0xFD6E0000
 #define XPAR_PSU_CCI_GPV_S_AXI_HIGHADDR 0xFD6EFFFF
@@ -406,11 +430,6 @@
 #define XPAR_PSU_DDR_XMPU5_CFG_S_AXI_HIGHADDR 0xFD05FFFF
 
 
-/* Definitions for peripheral PSU_DDRC_0 */
-#define XPAR_PSU_DDRC_0_S_AXI_BASEADDR 0xFD070000
-#define XPAR_PSU_DDRC_0_S_AXI_HIGHADDR 0xFD070FFF
-
-
 /* Definitions for peripheral PSU_DP */
 #define XPAR_PSU_DP_S_AXI_BASEADDR 0xFD4A0000
 #define XPAR_PSU_DP_S_AXI_HIGHADDR 0xFD4AFFFF
@@ -456,11 +475,6 @@
 #define XPAR_PSU_GPU_S_AXI_HIGHADDR 0xFD4BFFFF
 
 
-/* Definitions for peripheral PSU_IOU_S */
-#define XPAR_PSU_IOU_S_S_AXI_BASEADDR 0xFF000000
-#define XPAR_PSU_IOU_S_S_AXI_HIGHADDR 0xFF2AFFFF
-
-
 /* Definitions for peripheral PSU_IOU_SCNTR */
 #define XPAR_PSU_IOU_SCNTR_S_AXI_BASEADDR 0xFF250000
 #define XPAR_PSU_IOU_SCNTR_S_AXI_HIGHADDR 0xFF25FFFF
@@ -516,11 +530,6 @@
 #define XPAR_PSU_OCM_RAM_0_S_AXI_HIGHADDR 0xFFFEFFFF
 
 
-/* Definitions for peripheral PSU_OCM_RAM_1 */
-#define XPAR_PSU_OCM_RAM_1_S_AXI_BASEADDR 0xFFFF0000
-#define XPAR_PSU_OCM_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF
-
-
 /* Definitions for peripheral PSU_OCM_XMPU_CFG */
 #define XPAR_PSU_OCM_XMPU_CFG_S_AXI_BASEADDR 0xFFA70000
 #define XPAR_PSU_OCM_XMPU_CFG_S_AXI_HIGHADDR 0xFFA7FFFF
@@ -541,6 +550,11 @@
 #define XPAR_PSU_PCIE_DMA_S_AXI_HIGHADDR 0xFD0FFFFF
 
 
+/* Definitions for peripheral PSU_PCIE_LOW */
+#define XPAR_PSU_PCIE_LOW_S_AXI_BASEADDR 0xE0000000
+#define XPAR_PSU_PCIE_LOW_S_AXI_HIGHADDR 0xEFFFFFFF
+
+
 /* Definitions for peripheral PSU_PMU_GLOBAL_0 */
 #define XPAR_PSU_PMU_GLOBAL_0_S_AXI_BASEADDR 0xFFD80000
 #define XPAR_PSU_PMU_GLOBAL_0_S_AXI_HIGHADDR 0xFFDBFFFF
@@ -551,44 +565,19 @@
 #define XPAR_PSU_PMU_IOMODULE_S_AXI_HIGHADDR 0xFFD5FFFF
 
 
-/* Definitions for peripheral PSU_PMU_RAM */
-#define XPAR_PSU_PMU_RAM_S_AXI_BASEADDR 0xFFDC0000
-#define XPAR_PSU_PMU_RAM_S_AXI_HIGHADDR 0xFFDDFFFF
-
-
 /* Definitions for peripheral PSU_QSPI_LINEAR_0 */
 #define XPAR_PSU_QSPI_LINEAR_0_S_AXI_BASEADDR 0xC0000000
 #define XPAR_PSU_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xDFFFFFFF
 
 
 /* Definitions for peripheral PSU_R5_0_ATCM */
-#define XPAR_PSU_R5_0_ATCM_S_AXI_BASEADDR 0xFFE00000
-#define XPAR_PSU_R5_0_ATCM_S_AXI_HIGHADDR 0xFFE0FFFF
-
-
-/* Definitions for peripheral PSU_R5_0_ATCM_LOCKSTEP */
-#define XPAR_PSU_R5_0_ATCM_LOCKSTEP_S_AXI_BASEADDR 0xFFE10000
-#define XPAR_PSU_R5_0_ATCM_LOCKSTEP_S_AXI_HIGHADDR 0xFFE1FFFF
+#define XPAR_PSU_R5_0_ATCM_S_AXI_BASEADDR 0x00000000
+#define XPAR_PSU_R5_0_ATCM_S_AXI_HIGHADDR 0x0000FFFF
 
 
 /* Definitions for peripheral PSU_R5_0_BTCM */
-#define XPAR_PSU_R5_0_BTCM_S_AXI_BASEADDR 0xFFE20000
-#define XPAR_PSU_R5_0_BTCM_S_AXI_HIGHADDR 0xFFE2FFFF
-
-
-/* Definitions for peripheral PSU_R5_0_BTCM_LOCKSTEP */
-#define XPAR_PSU_R5_0_BTCM_LOCKSTEP_S_AXI_BASEADDR 0xFFE30000
-#define XPAR_PSU_R5_0_BTCM_LOCKSTEP_S_AXI_HIGHADDR 0xFFE3FFFF
-
-
-/* Definitions for peripheral PSU_R5_1_ATCM */
-#define XPAR_PSU_R5_1_ATCM_S_AXI_BASEADDR 0xFFE90000
-#define XPAR_PSU_R5_1_ATCM_S_AXI_HIGHADDR 0xFFE9FFFF
-
-
-/* Definitions for peripheral PSU_R5_1_BTCM */
-#define XPAR_PSU_R5_1_BTCM_S_AXI_BASEADDR 0xFFEB0000
-#define XPAR_PSU_R5_1_BTCM_S_AXI_HIGHADDR 0xFFEBFFFF
+#define XPAR_PSU_R5_0_BTCM_S_AXI_BASEADDR 0x00020000
+#define XPAR_PSU_R5_0_BTCM_S_AXI_HIGHADDR 0x0002FFFF
 
 
 /* Definitions for peripheral PSU_R5_DDR_0 */
@@ -598,7 +587,7 @@
 
 /* Definitions for peripheral PSU_R5_TCM_RAM_0 */
 #define XPAR_PSU_R5_TCM_RAM_0_S_AXI_BASEADDR 0x00000000
-#define XPAR_PSU_R5_TCM_RAM_0_S_AXI_HIGHADDR 0x00020000
+#define XPAR_PSU_R5_TCM_RAM_0_S_AXI_HIGHADDR 0x0003FFFF
 
 
 /* Definitions for peripheral PSU_RPU */
@@ -636,11 +625,6 @@
 #define XPAR_PSU_SMMU_REG_S_AXI_HIGHADDR 0xFD5FFFFF
 
 
-/* Definitions for peripheral PSU_USB_0 */
-#define XPAR_PSU_USB_0_S_AXI_BASEADDR 0xFE200000
-#define XPAR_PSU_USB_0_S_AXI_HIGHADDR 0xFE20FFFF
-
-
 /******************************************************************/
 
 /* Definitions for driver GPIOPS */
@@ -754,15 +738,31 @@
 
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_MASK  XPAR_PSU_IPI_0_BIT_MASK
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_INDEX  0
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH1_MASK  XPAR_PSU_IPI_1_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH1_INDEX  1
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH2_MASK  XPAR_PSU_IPI_2_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH2_INDEX  2
 
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_MASK  XPAR_PSU_IPI_0_BIT_MASK
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_INDEX  0
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH1_MASK  XPAR_PSU_IPI_1_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH1_INDEX  1
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH2_MASK  XPAR_PSU_IPI_2_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH2_INDEX  2
 
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_MASK  XPAR_PSU_IPI_0_BIT_MASK
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_INDEX  0
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH1_MASK  XPAR_PSU_IPI_1_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH1_INDEX  1
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH2_MASK  XPAR_PSU_IPI_2_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH2_INDEX  2
 
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_MASK  XPAR_PSU_IPI_0_BIT_MASK
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_INDEX  0
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH1_MASK  XPAR_PSU_IPI_1_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH1_INDEX  1
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH2_MASK  XPAR_PSU_IPI_2_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH2_INDEX  2
 
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_MASK  XPAR_PSU_IPI_1_BIT_MASK
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_INDEX  1
@@ -774,14 +774,18 @@
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH1_MASK  XPAR_PSU_IPI_2_BIT_MASK
 #define  XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH1_INDEX  2
 
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_MASK  XPAR_PSU_IPI_3_BIT_MASK
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_INDEX  3
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_MASK  XPAR_PSU_IPI_4_BIT_MASK
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_INDEX  4
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_MASK  XPAR_PSU_IPI_5_BIT_MASK
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_INDEX  5
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_MASK  XPAR_PSU_IPI_6_BIT_MASK
-#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_INDEX  6
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_MASK  XPAR_PSU_IPI_1_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_INDEX  1
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_MASK  XPAR_PSU_IPI_2_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_INDEX  2
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_MASK  XPAR_PSU_IPI_3_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_INDEX  3
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_MASK  XPAR_PSU_IPI_4_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_INDEX  4
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH4_MASK  XPAR_PSU_IPI_5_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH4_INDEX  5
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH5_MASK  XPAR_PSU_IPI_6_BIT_MASK
+#define  XPAR_XIPIPS_TARGET_PSU_PMU_0_CH5_INDEX  6
 
 /* Definitions for driver QSPIPSU */
 #define XPAR_XQSPIPSU_NUM_INSTANCES 1
@@ -858,6 +862,9 @@
 #define XPAR_PSU_SD_1_SDIO_CLK_FREQ_HZ 199998006
 #define XPAR_PSU_SD_1_HAS_CD 1
 #define XPAR_PSU_SD_1_HAS_WP 1
+#define XPAR_PSU_SD_1_BUS_WIDTH 4
+#define XPAR_PSU_SD_1_MIO_BANK 1
+#define XPAR_PSU_SD_1_HAS_EMIO 0
 
 
 /******************************************************************/
@@ -869,6 +876,9 @@
 #define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 199998006
 #define XPAR_XSDPS_0_HAS_CD 1
 #define XPAR_XSDPS_0_HAS_WP 1
+#define XPAR_XSDPS_0_BUS_WIDTH 4
+#define XPAR_XSDPS_0_MIO_BANK 1
+#define XPAR_XSDPS_0_HAS_EMIO 0
 
 
 /******************************************************************/
@@ -1062,6 +1072,25 @@
 
 /******************************************************************/
 
+/* Definitions for driver USBPSU */
+#define XPAR_XUSBPSU_NUM_INSTANCES 1
+
+/* Definitions for peripheral PSU_USB_0 */
+#define XPAR_PSU_USB_0_DEVICE_ID 0
+#define XPAR_PSU_USB_0_BASEADDR 0xFE200000
+#define XPAR_PSU_USB_0_HIGHADDR 0xFE20FFFF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PSU_USB_0 */
+#define XPAR_XUSBPSU_0_DEVICE_ID XPAR_PSU_USB_0_DEVICE_ID
+#define XPAR_XUSBPSU_0_BASEADDR 0xFE200000
+#define XPAR_XUSBPSU_0_HIGHADDR 0xFE20FFFF
+
+
+/******************************************************************/
+
 /* Definitions for driver WDTPS */
 #define XPAR_XWDTPS_NUM_INSTANCES 2
 
@@ -1069,14 +1098,14 @@
 #define XPAR_PSU_WDT_0_DEVICE_ID 0
 #define XPAR_PSU_WDT_0_BASEADDR 0xFF150000
 #define XPAR_PSU_WDT_0_HIGHADDR 0xFF15FFFF
-#define XPAR_PSU_WDT_0_WDT_CLK_FREQ_HZ 25000000
+#define XPAR_PSU_WDT_0_WDT_CLK_FREQ_HZ 99999001
 
 
 /* Definitions for peripheral PSU_WDT_1 */
 #define XPAR_PSU_WDT_1_DEVICE_ID 1
 #define XPAR_PSU_WDT_1_BASEADDR 0xFD4D0000
 #define XPAR_PSU_WDT_1_HIGHADDR 0xFD4DFFFF
-#define XPAR_PSU_WDT_1_WDT_CLK_FREQ_HZ 25000000
+#define XPAR_PSU_WDT_1_WDT_CLK_FREQ_HZ 99999001
 
 
 /******************************************************************/
@@ -1085,13 +1114,13 @@
 #define XPAR_XWDTPS_0_DEVICE_ID XPAR_PSU_WDT_0_DEVICE_ID
 #define XPAR_XWDTPS_0_BASEADDR 0xFF150000
 #define XPAR_XWDTPS_0_HIGHADDR 0xFF15FFFF
-#define XPAR_XWDTPS_0_WDT_CLK_FREQ_HZ 25000000
+#define XPAR_XWDTPS_0_WDT_CLK_FREQ_HZ 99999001
 
 /* Canonical definitions for peripheral PSU_WDT_1 */
 #define XPAR_XWDTPS_1_DEVICE_ID XPAR_PSU_WDT_1_DEVICE_ID
 #define XPAR_XWDTPS_1_BASEADDR 0xFD4D0000
 #define XPAR_XWDTPS_1_HIGHADDR 0xFD4DFFFF
-#define XPAR_XWDTPS_1_WDT_CLK_FREQ_HZ 25000000
+#define XPAR_XWDTPS_1_WDT_CLK_FREQ_HZ 99999001
 
 
 /******************************************************************/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/Makefile
index 926b20c4e..926b20c4e 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/Makefile
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/Makefile
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon.c
index fbb867839..fbb867839 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon.h
index f8d4d6467..f8d4d6467 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_g.c
index a33878ef5..2bd473dd5 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon_g.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_hw.h
index 68ed57aaf..68ed57aaf 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon_hw.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_hw.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_selftest.c
index df2a9da66..df2a9da66 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon_selftest.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_selftest.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_sinit.c
index 737d80b48..737d80b48 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon_sinit.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_sinit.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/Makefile
index 55565709b..55565709b 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/Makefile
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/Makefile
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps.c
index 243b3a81b..243b3a81b 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps.h
index b180e37ec..b180e37ec 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_g.c
index b45c5b2d6..4063a44eb 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_g.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_hw.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_hw.c
index bbb96120a..bbb96120a 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_hw.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_hw.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_hw.h
index 9fe681aaf..9fe681aaf 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_hw.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_hw.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_intr.c
index f6721ca75..f6721ca75 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_intr.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_intr.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_selftest.c
index 8bc77d7f4..48a6f4031 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_selftest.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_selftest.c
@@ -166,7 +166,7 @@ s32 XCanPs_SelfTest(XCanPs *InstancePtr)
 	for (Index = 0U; Index < 8U; Index++) {
 		if(*FramePtr != 0U) {
 			*FramePtr = (u8)Index;
-			*FramePtr++;
+			FramePtr++;
 		}
 	}
 
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_sinit.c
index 230c429b3..230c429b3 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_sinit.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_sinit.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_2/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_3/src/Makefile
index 007162d8c..007162d8c 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_2/src/Makefile
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_3/src/Makefile
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_2/src/xcoresightpsdcc.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_3/src/xcoresightpsdcc.c
index e999f6f5d..4bad57094 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_2/src/xcoresightpsdcc.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_3/src/xcoresightpsdcc.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2015-2016 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -51,12 +51,18 @@
 * 1.1   kvn    06/12/15 Add support for Zynq Ultrascale+ MP.
 *       kvn    08/18/15 Modified Makefile according to compiler changes.
 * 1.2   kvn    10/09/15 Add support for IAR Compiler.
+* 1.3   asa    07/01/16 Made changes to ensure that the file does not compile
+*                       for MB BSPs. Instead it throws up a warning. This
+*                       fixes the CR#953056.
 *
 * </pre>
 *
 ******************************************************************************/
 
 /***************************** Include Files *********************************/
+#ifdef __MICROBLAZE__
+#warning "The driver is supported only for ARM architecture"
+#else
 
 #include <xil_types.h>
 #include <xpseudo_asm.h>
@@ -177,5 +183,6 @@ static INLINE u32 XCoresightPs_DccGetStatus(void)
 	}
 #endif
 	return Status;
+#endif
 }
 /** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_2/src/xcoresightpsdcc.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_3/src/xcoresightpsdcc.h
index 6bab7ae09..a732b235d 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_2/src/xcoresightpsdcc.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_3/src/xcoresightpsdcc.h
@@ -55,16 +55,20 @@
 * 1.00  kvn    02/14/15 First release
 * 1.1   kvn    06/12/15 Add support for Zynq Ultrascale+ MP.
 *       kvn    08/18/15 Modified Makefile according to compiler changes.
+* 1.3   asa    07/01/16 Made changes to ensure that the file does not compile
+*                       for MB BSPs. Instead it throws up a warning. This
+*                       fixes the CR#953056.
 *
 * </pre>
 *
 ******************************************************************************/
 
 /***************************** Include Files *********************************/
-
+#ifndef __MICROBLAZE__
 #include <xil_types.h>
 
 void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data);
 
 u8 XCoresightPs_DccRecvByte(u32 BaseAddress);
+#endif
 /** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/Makefile
index 778797bcf..778797bcf 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/Makefile
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/Makefile
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma.c
index 2f6a62e50..4ed4dd60b 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma.c
@@ -46,6 +46,8 @@
 * Ver   Who     Date     Changes
 * ----- ------  -------- ---------------------------------------------------
 * 1.0   vnsld   22/10/14 First release
+* 1.1   adk     10/05/16 Fixed CR#951040 race condition in the recv path when
+*                        source and destination points to the same buffer.
 * </pre>
 *
 ******************************************************************************/
@@ -152,8 +154,12 @@ void XCsuDma_Transfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel,
 	}
 	/* Invalidating cache memory */
 	else {
+#if defined(__aarch64__)
 		Xil_DCacheInvalidateRange(Addr, Size <<
 					(u32)(XCSUDMA_SIZE_SHIFT));
+#else
+		Xil_DCacheFlushRange(Addr, Size << (u32)(XCSUDMA_SIZE_SHIFT));
+#endif
 	}
 
 	XCsuDma_WriteReg(InstancePtr->Config.BaseAddress,
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma.h
index fe63530a5..03a32c1ce 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma.h
@@ -97,6 +97,8 @@
 * Ver   Who     Date     Changes
 * ----- ------  -------- -----------------------------------------------------
 * 1.0   vnsld   22/10/14 First release
+* 1.1   adk     10/05/16 Fixed CR#951040 race condition in the recv path when
+*                        source and destination points to the same buffer.
 * </pre>
 *
 ******************************************************************************/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_g.c
index b3fb65f5b..09e7f739a 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_g.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_hw.h
index 6b2c2cdb8..6b2c2cdb8 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_hw.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_hw.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_intr.c
index 9f37e4582..9f37e4582 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_intr.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_intr.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_selftest.c
index f61910fd4..f61910fd4 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_selftest.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_selftest.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_sinit.c
index 10e5c14f6..10e5c14f6 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_sinit.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_sinit.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ddrcpsu_v1_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ddrcpsu_v1_1/src/Makefile
new file mode 100644
index 000000000..198637a46
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ddrcpsu_v1_1/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xddrcpsu_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling ddrcpsu"
+
+xddrcpsu_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xddrcpsu_includes
+
+xddrcpsu_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ddrcpsu_v1_1/src/xddrcpsu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ddrcpsu_v1_1/src/xddrcpsu.h
new file mode 100644
index 000000000..2640a9462
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ddrcpsu_v1_1/src/xddrcpsu.h
@@ -0,0 +1,66 @@
+/*******************************************************************************
+ *
+ * Copyright (C) 2016 Xilinx, Inc.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * Use of the Software is limited solely to applications:
+ * (a) running on a Xilinx device, or
+ * (b) that interact with a Xilinx device through a bus or interconnect.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Except as contained in this notice, the name of the Xilinx shall not be used
+ * in advertising or otherwise to promote the sale, use or other dealings in
+ * in advertising or otherwise to promote the sale, use or other dealings in
+ * this Software without prior written authorization from Xilinx.
+ *
+*******************************************************************************/
+/******************************************************************************/
+/**
+ *
+ * @file xddcrpsu.h
+ * @addtogroup ddrcpsu_v1_0
+ * @{
+ * @details
+ *
+ * The Xilinx DdrcPsu driver. This driver supports the Xilinx ddrcpsu
+ * IP core.
+ *
+ * @note	None.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0	ssc   04/28/16 First Release.
+ * 1.1  adk   04/08/16 Export DDR freq to xparameters.h file.
+ *
+ * </pre>
+ *
+*******************************************************************************/
+
+#ifndef XDDRCPS_H_
+/* Prevent circular inclusions by using protection macros. */
+#define XDDRCPS_H_
+
+/******************************* Include Files ********************************/
+
+
+#endif /* XDDRCPS_H_ */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/Makefile
index 7002e6223..7002e6223 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/Makefile
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/Makefile
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps.c
index 26df03c3d..26df03c3d 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps.h
index f12092bec..f12092bec 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_bd.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_bd.h
index 52c5f7e7e..52c5f7e7e 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_bd.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_bd.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_bdring.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_bdring.c
index d837e1df1..d837e1df1 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_bdring.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_bdring.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_bdring.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_bdring.h
index de78cf28f..de78cf28f 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_bdring.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_bdring.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_control.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_control.c
index f52451a8c..f52451a8c 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_control.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_control.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_g.c
index 6a7cc7866..db734b924 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_g.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_hw.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_hw.c
index daba38397..daba38397 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_hw.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_hw.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_hw.h
index 953cc6265..953cc6265 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_hw.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_hw.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_intr.c
index 59636c4ef..59636c4ef 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_intr.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_intr.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_sinit.c
index 1bc5b3b19..1bc5b3b19 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_sinit.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_sinit.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_g.c
index 597b38a12..38a5b9355 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_g.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/Makefile
index 8c16c35ae..8c16c35ae 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/Makefile
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/Makefile
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps.c
index 812c2ecdc..1c6819152 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -54,6 +54,7 @@
 * 						 in XIicPs_Reset.
 *				12/06/14 Implemented Repeated start feature.
 *				01/31/15 Modified the code according to MISRAC 2012 Compliant.
+* 3.3   kvn		05/05/16 Modified latest code for MISRA-C:2012 Compliance.
 *
 * </pre>
 *
@@ -228,7 +229,7 @@ void XIicPs_Abort(XIicPs *InstancePtr)
 	 * Reset the settings in config register and clear the FIFOs.
 	 */
 	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
-			  XIICPS_CR_RESET_VALUE | XIICPS_CR_CLR_FIFO_MASK);
+			  (u32)XIICPS_CR_RESET_VALUE | (u32)XIICPS_CR_CLR_FIFO_MASK);
 
 	/*
 	 * Read, then write the interrupt status to make sure there are no
@@ -242,7 +243,7 @@ void XIicPs_Abort(XIicPs *InstancePtr)
 	/*
 	 * Restore the interrupt state.
 	 */
-	IntrMaskReg = XIICPS_IXR_ALL_INTR_MASK & (~IntrMaskReg);
+	IntrMaskReg = (u32)XIICPS_IXR_ALL_INTR_MASK & (~IntrMaskReg);
 	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
 			  XIICPS_IER_OFFSET, IntrMaskReg);
 
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps.h
index 73ad5dc64..b26193486 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps.h
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -183,6 +183,7 @@
 *			01/31/15 Modified the code according to MISRAC 2012 Compliant.
 *			02/18/15 Implemented larger data transfer using repeated start
 *					  in Zynq UltraScale MP.
+* 3.3   kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
 *
 * </pre>
 *
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_g.c
index 50f1c1413..f449e0ed6 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_g.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_hw.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_hw.c
index 8b7a58fc6..a1dba8e62 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_hw.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_hw.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2013 - 2016 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_hw.h
index cec349928..3b00cf8b1 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_hw.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_hw.h
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_intr.c
index de05b93b6..5231049c7 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_intr.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_intr.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_master.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_master.c
index d49feecdf..7824d86b6 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_master.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_master.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -62,6 +62,7 @@
 *			 01/31/15 Modified the code according to MISRAC 2012 Compliant.
 *			 02/18/15 Implemented larger data transfer using repeated start
 *					  in Zynq UltraScale MP.
+* 3.3   kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
 *
 * </pre>
 *
@@ -106,6 +107,7 @@ void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
 		 u16 SlaveAddr)
 {
 	u32 BaseAddr;
+	u32 Platform = XGetPlatform_Info();
 
 	/*
 	 * Assert validates the input arguments.
@@ -147,6 +149,16 @@ void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
 	 */
 	XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
 
+	/* Clear the Hold bit in ZYNQ if receive byte count is less than
+	 * the FIFO depth to get the completion interrupt properly.
+	 */
+	if ((ByteCount < XIICPS_FIFO_DEPTH) && (Platform == (u32)XPLAT_ZYNQ))
+	{
+		XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+				XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) &
+				(u32)(~XIICPS_CR_HOLD_MASK));
+	}
+
 }
 
 /*****************************************************************************/
@@ -182,10 +194,8 @@ void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
 	BaseAddr = InstancePtr->Config.BaseAddress;
 	InstancePtr->RecvBufferPtr = MsgPtr;
 	InstancePtr->RecvByteCount = ByteCount;
-	InstancePtr->CurrByteCount = ByteCount;
 	InstancePtr->SendBufferPtr = NULL;
 	InstancePtr->IsSend = 0;
-	InstancePtr->UpdateTxSize = 0;
 
 	if ((ByteCount > XIICPS_FIFO_DEPTH) ||
 		((InstancePtr->IsRepeatedStart) !=0))
@@ -203,14 +213,16 @@ void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
 	 * Setup the transfer size register so the slave knows how much
 	 * to send to us.
 	 */
-	if (ByteCount > XIICPS_MAX_TRANSFER_SIZE) {
+	if (ByteCount > (s32)XIICPS_MAX_TRANSFER_SIZE) {
 		XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
 				XIICPS_MAX_TRANSFER_SIZE);
 		InstancePtr->CurrByteCount = (s32)XIICPS_MAX_TRANSFER_SIZE;
 		InstancePtr->UpdateTxSize = 1;
 	}else {
+		InstancePtr->CurrByteCount = ByteCount;
 		XIicPs_WriteReg(BaseAddr, (u32)(XIICPS_TRANS_SIZE_OFFSET),
 			 (u32)ByteCount);
+		InstancePtr->UpdateTxSize = 0;
 	}
 
 	XIicPs_EnableInterrupts(BaseAddr,
@@ -251,8 +263,7 @@ s32 XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr,
 	u32 StatusReg;
 	u32 BaseAddr;
 	u32 Intrs;
-	u32 Value;
-	s32 Status;
+	_Bool Value;
 
 	/*
 	 * Assert validates the input arguments.
@@ -260,7 +271,7 @@ s32 XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr,
 	Xil_AssertNonvoid(InstancePtr != NULL);
 	Xil_AssertNonvoid(MsgPtr != NULL);
 	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
-	Xil_AssertNonvoid(XIICPS_ADDR_MASK >= SlaveAddr);
+	Xil_AssertNonvoid((u16)XIICPS_ADDR_MASK >= SlaveAddr);
 
 	BaseAddr = InstancePtr->Config.BaseAddress;
 	InstancePtr->SendBufferPtr = MsgPtr;
@@ -302,7 +313,7 @@ s32 XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr,
 	 */
 	Value = ((InstancePtr->SendByteCount > (s32)0) &&
 		((IntrStatusReg & Intrs) == (u32)0U));
-	while (Value != (u32)0x00U) {
+	while (Value != FALSE) {
 		StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
 
 		/*
@@ -374,14 +385,8 @@ s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr,
 	u32 Intrs;
 	u32 StatusReg;
 	u32 BaseAddr;
-	s32 BytesToRecv;
-	s32 BytesToRead;
-	s32 TransSize;
-	s32 Tmp = 0;
-	u32 Status_Rcv;
-	u32 Status;
 	s32 Result;
-	s32 IsHold = 0;
+	s32 IsHold;
 	s32 UpdateTxSize = 0;
 	s32 ByteCountVar = ByteCount;
 	u32 Platform;
@@ -407,6 +412,8 @@ s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr,
 				XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
 						(u32)XIICPS_CR_HOLD_MASK);
 		IsHold = 1;
+	} else {
+		IsHold = 0;
 	}
 
 	(void)XIicPs_SetupMaster(InstancePtr, RECVING_ROLE);
@@ -423,7 +430,7 @@ s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr,
 	 * Set up the transfer size register so the slave knows how much
 	 * to send to us.
 	 */
-	if (ByteCountVar > XIICPS_MAX_TRANSFER_SIZE) {
+	if (ByteCountVar > (s32)XIICPS_MAX_TRANSFER_SIZE) {
 		XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
 				XIICPS_MAX_TRANSFER_SIZE);
 		ByteCountVar = (s32)XIICPS_MAX_TRANSFER_SIZE;
@@ -460,18 +467,18 @@ s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr,
 			XIicPs_RecvByte(InstancePtr);
 		    ByteCountVar --;
 
-			if (Platform == XPLAT_ZYNQ) {
+			if (Platform == (u32)XPLAT_ZYNQ) {
 			    if ((UpdateTxSize != 0) &&
-				    ((ByteCountVar == (XIICPS_FIFO_DEPTH + 1)) != 0U)) {
+				    (ByteCountVar == (XIICPS_FIFO_DEPTH + 1))) {
 				    break;
 				}
 			}
 
 			StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
 		}
-		if (Platform == XPLAT_ZYNQ) {
+		if (Platform == (u32)XPLAT_ZYNQ) {
 			if ((UpdateTxSize != 0) &&
-				((ByteCountVar == (XIICPS_FIFO_DEPTH + 1)) != 0U)) {
+				(ByteCountVar == (XIICPS_FIFO_DEPTH + 1))) {
 			    /*  wait while fifo is full */
 			    while (XIicPs_ReadReg(BaseAddr,
 				    XIICPS_TRANS_SIZE_OFFSET) !=
@@ -479,7 +486,7 @@ s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr,
 				}
 
 				if ((InstancePtr->RecvByteCount - XIICPS_FIFO_DEPTH) >
-					XIICPS_MAX_TRANSFER_SIZE) {
+					(s32)XIICPS_MAX_TRANSFER_SIZE) {
 
 					XIicPs_WriteReg(BaseAddr,
 						XIICPS_TRANS_SIZE_OFFSET,
@@ -507,7 +514,7 @@ s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr,
 				XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
 
 				if ((InstancePtr->RecvByteCount) >
-					XIICPS_MAX_TRANSFER_SIZE) {
+					(s32)XIICPS_MAX_TRANSFER_SIZE) {
 
 					XIicPs_WriteReg(BaseAddr,
 						XIICPS_TRANS_SIZE_OFFSET,
@@ -755,17 +762,17 @@ void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr)
 			XIicPs_RecvByte(InstancePtr);
 			ByteCnt--;
 
-			if (Platform == XPLAT_ZYNQ) {
+			if (Platform == (u32)XPLAT_ZYNQ) {
 			    if ((InstancePtr->UpdateTxSize != 0) &&
-				    ((ByteCnt == (XIICPS_FIFO_DEPTH + 1)) != 0U)) {
+				    (ByteCnt == (XIICPS_FIFO_DEPTH + 1))) {
 				    break;
 				}
 			}
 		}
 
-		if (Platform == XPLAT_ZYNQ) {
+		if (Platform == (u32)XPLAT_ZYNQ) {
 			if ((InstancePtr->UpdateTxSize != 0) &&
-				((ByteCnt == (XIICPS_FIFO_DEPTH + 1))!= 0U)) {
+				(ByteCnt == (XIICPS_FIFO_DEPTH + 1))) {
 				/* wait while fifo is full */
 				while (XIicPs_ReadReg(BaseAddr,
 					XIICPS_TRANS_SIZE_OFFSET) !=
@@ -773,7 +780,7 @@ void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr)
 				}
 
 				if ((InstancePtr->RecvByteCount - XIICPS_FIFO_DEPTH) >
-					XIICPS_MAX_TRANSFER_SIZE) {
+					(s32)XIICPS_MAX_TRANSFER_SIZE) {
 
 					XIicPs_WriteReg(BaseAddr,
 						XIICPS_TRANS_SIZE_OFFSET,
@@ -798,11 +805,11 @@ void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr)
 				IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
 				XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
 
-				SlaveAddr = XIicPs_ReadReg(BaseAddr, (u32)XIICPS_ADDR_OFFSET);
+				SlaveAddr = (u16)XIicPs_ReadReg(BaseAddr, (u32)XIICPS_ADDR_OFFSET);
 				XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
 
 				if ((InstancePtr->RecvByteCount) >
-					XIICPS_MAX_TRANSFER_SIZE) {
+					(s32)XIICPS_MAX_TRANSFER_SIZE) {
 
 					XIicPs_WriteReg(BaseAddr,
 						XIICPS_TRANS_SIZE_OFFSET,
@@ -910,7 +917,6 @@ static s32 XIicPs_SetupMaster(XIicPs *InstancePtr, s32 Role)
 {
 	u32 ControlReg;
 	u32 BaseAddr;
-	u32 EnabledIntr = 0x0U;
 
 	Xil_AssertNonvoid(InstancePtr != NULL);
 
@@ -935,11 +941,9 @@ static s32 XIicPs_SetupMaster(XIicPs *InstancePtr, s32 Role)
 
 	if (Role == RECVING_ROLE) {
 		ControlReg |= (u32)XIICPS_CR_RD_WR_MASK;
-		EnabledIntr = (u32)XIICPS_IXR_DATA_MASK |(u32)XIICPS_IXR_RX_OVR_MASK;
 	}else {
 		ControlReg &= (u32)(~XIICPS_CR_RD_WR_MASK);
 	}
-	EnabledIntr |= (u32)XIICPS_IXR_COMP_MASK | (u32)XIICPS_IXR_ARB_LOST_MASK;
 
 	XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, ControlReg);
 
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_options.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_options.c
index 5d7427a48..1ebd78673 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_options.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_options.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -55,6 +55,7 @@
 * 2.3	sk	10/07/14 Repeated start feature removed.
 * 3.0	sk	12/06/14 Implemented Repeated start feature.
 *			01/31/15 Modified the code according to MISRAC 2012 Compliant.
+* 3.3   kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
 *
 * </pre>
 *
@@ -135,7 +136,7 @@ s32 XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options)
 	 * The hold bit in CR will be written by driver when the next transfer
 	 * is initiated.
 	 */
-	if ((OptionsVar & XIICPS_REP_START_OPTION) != 0U ) {
+	if ((OptionsVar & (u32)XIICPS_REP_START_OPTION) != (u32)0 ) {
 		InstancePtr->IsRepeatedStart = 1;
 		OptionsVar = OptionsVar & (~XIICPS_REP_START_OPTION);
 	}
@@ -349,8 +350,8 @@ s32 XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz)
 	u32 ControlReg;
 	u32 CalcDivA;
 	u32 CalcDivB;
-	u32 BestDivA = 0;
-	u32 BestDivB = 0;
+	u32 BestDivA;
+	u32 BestDivB;
 	u32 FsclHzVar = FsclHz;
 
 	Xil_AssertNonvoid(InstancePtr != NULL);
@@ -379,12 +380,12 @@ s32 XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz)
 	 * If frequency 100KHz is selected, 90KHz should be set.
 	 * This is due to a hardware limitation.
 	 */
-	if(FsclHzVar > 384600U) {
-		FsclHzVar = 384600U;
+	if(FsclHzVar > (u32)384600U) {
+		FsclHzVar = (u32)384600U;
 	}
 
-	if((FsclHzVar <= 100000U) && (FsclHzVar > 90000U)) {
-		FsclHzVar = 90000U;
+	if((FsclHzVar <= (u32)100000U) && (FsclHzVar > (u32)90000U)) {
+		FsclHzVar = (u32)90000U;
 	}
 
 	/*
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_selftest.c
index 2d9e0e35e..dd57a1a51 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_selftest.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_selftest.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_sinit.c
index 40ee7733e..7d7dadaa8 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_sinit.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_sinit.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_slave.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_slave.c
index 074b5ea2e..fef640b77 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_slave.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_slave.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -44,6 +44,7 @@
 * 1.00a jz  01/30/10 First release
 * 1.04a kpc 08/30/13 Avoid buffer overwrite in SlaveRecvData function
 * 3.00	sk	01/31/15 Modified the code according to MISRAC 2012 Compliant.
+* 3.3   kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
 *
 * </pre>
 *
@@ -210,7 +211,8 @@ s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
 	s32 BytesToSend;
 	s32 Error = 0;
 	s32 Status = (s32)XST_SUCCESS;
-	u32 Value;
+	_Bool Value;
+	_Bool Result;
 
 	/*
 	 * Assert validates the input arguments.
@@ -227,8 +229,9 @@ s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
 	 * Use RXRW bit in status register to wait master to start a read.
 	 */
 	StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
-	while (((StatusReg & XIICPS_SR_RXRW_MASK) == 0U) &&
-				((!Error) != 0)) {
+	Result = (((u32)(StatusReg & XIICPS_SR_RXRW_MASK) == (u32)0x0U) &&
+			(Error == 0));
+	while (Result != FALSE) {
 
 		/*
 		 * If master tries to send us data, it is an error.
@@ -238,6 +241,8 @@ s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
 		}
 
 		StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+		Result = (((u32)(StatusReg & XIICPS_SR_RXRW_MASK) == (u32)0x0U) &&
+				(Error == 0));
 	}
 
 	if (Error != 0) {
@@ -255,8 +260,8 @@ s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
 		 * there are no errors.
 		 */
 		Value = (InstancePtr->SendByteCount > (s32)0) &&
-						((!Error) != 0);
-		while (Value != (u32)0x00U) {
+						((Error == 0));
+		while (Value != FALSE) {
 
 			/*
 			 * Find out how many can be sent.
@@ -276,7 +281,7 @@ s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
 			 * Wait for master to read the data out of fifo.
 			 */
 			while (((StatusReg & XIICPS_SR_TXDV_MASK) != (u32)0x00U) &&
-							((!Error) != 0)) {
+							(Error == 0)) {
 
 				/*
 				 * If master terminates the transfer before all data is
@@ -296,12 +301,12 @@ s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
 				StatusReg = XIicPs_ReadReg(BaseAddr,
 						XIICPS_SR_OFFSET);
 			}
-			Value = (InstancePtr->SendByteCount > (s32)0U) &&
-							((!Error) != 0);
+			Value = ((InstancePtr->SendByteCount > (s32)0) &&
+							(Error == 0));
 		}
 	}
 	if (Error != 0) {
-	Status = (s32)XST_FAILURE;
+		Status = (s32)XST_FAILURE;
 	}
 
 	return Status;
@@ -551,7 +556,7 @@ void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr)
 	/*
 	 * Signal application if there are any events.
 	 */
-	if (0U != StatusEvent) {
+	if ((u32)0U != StatusEvent) {
 		InstancePtr->StatusHandler(InstancePtr->CallBackRef,
 					   StatusEvent);
 	}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/Makefile
index 3e1fc71f7..3e1fc71f7 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/Makefile
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/Makefile
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu.c
index f8f902330..7c9d98ab0 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2015 - 2016 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -47,6 +47,7 @@
 * 1.00	mjr	03/15/15	First Release
 * 2.0	mjr	01/22/16	Fixed response buffer address
 *                               calculation. CR# 932582.
+* 2.1	kvn	05/05/16	Modified code for MISRA-C:2012 Compliance
 * </pre>
 *
 *****************************************************************************/
@@ -85,7 +86,7 @@ XStatus XIpiPsu_CfgInitialize(XIpiPsu *InstancePtr, XIpiPsu_Config * CfgPtr,
 
 	InstancePtr->Config.TargetCount = CfgPtr->TargetCount;
 
-	for (Index = 0; Index < CfgPtr->TargetCount; Index++) {
+	for (Index = 0U; Index < CfgPtr->TargetCount; Index++) {
 		InstancePtr->Config.TargetList[Index].Mask =
 				CfgPtr->TargetList[Index].Mask;
 		InstancePtr->Config.TargetList[Index].BufferIndex =
@@ -167,7 +168,7 @@ XStatus XIpiPsu_PollForAck(XIpiPsu *InstancePtr, u32 DestCpuMask,
 	Xil_AssertNonvoid(InstancePtr != NULL);
 	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
-	PollCount = 0;
+	PollCount = 0U;
 	/* Poll the OBS register until the corresponding DestCpu bit is cleared */
 	do {
 		Flag = (XIpiPsu_ReadReg(InstancePtr->Config.BaseAddress,
@@ -202,10 +203,10 @@ static u32 XIpiPsu_GetBufferIndex(XIpiPsu *InstancePtr, u32 CpuMask)
 	u32 BufferIndex;
 	u32 Index;
 	/* Init Index with an invalid value */
-	BufferIndex = XIPIPSU_MAX_BUFF_INDEX + 1;
+	BufferIndex = XIPIPSU_MAX_BUFF_INDEX + 1U;
 
 	/*Search for CPU in the List */
-	for (Index = 0; Index < InstancePtr->Config.TargetCount; Index++) {
+	for (Index = 0U; Index < InstancePtr->Config.TargetCount; Index++) {
 		/*If we find the CPU , then set the Index and break the loop*/
 		if (InstancePtr->Config.TargetList[Index].Mask == CpuMask) {
 			BufferIndex = InstancePtr->Config.TargetList[Index].BufferIndex;
@@ -276,29 +277,29 @@ static u32* XIpiPsu_GetBufferAddress(XIpiPsu *InstancePtr, u32 SrcCpuMask,
  * @param 	SrcCpuMask is the Device Mask for the CPU which has sent the message
  * @param 	MsgPtr is the pointer to Buffer to which the read message needs to be stored
  * @param 	MsgLength is the length of the buffer/message
- * @param 	BufType is the type of buffer (XIPIPSU_BUF_TYPE_MSG or XIPIPSU_BUF_TYPE_RESP)
+ * @param 	BufferType is the type of buffer (XIPIPSU_BUF_TYPE_MSG or XIPIPSU_BUF_TYPE_RESP)
  *
  * @return	XST_SUCCESS if successful
  * 			XST_FAILURE if an error occurred
  */
 
-XStatus XIpiPsu_ReadMessage(XIpiPsu *InstancePtr, u32 TargetMask, u32 *MsgPtr,
+XStatus XIpiPsu_ReadMessage(XIpiPsu *InstancePtr, u32 SrcCpuMask, u32 *MsgPtr,
 		u32 MsgLength, u8 BufferType)
 {
 	u32 *BufferPtr;
 	u32 Index;
-	u32 Status;
+	XStatus Status;
 
 	Xil_AssertNonvoid(InstancePtr != NULL);
 	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 	Xil_AssertNonvoid(MsgPtr != NULL);
 	Xil_AssertNonvoid(MsgLength <= XIPIPSU_MAX_MSG_LEN);
 
-	BufferPtr = XIpiPsu_GetBufferAddress(InstancePtr, TargetMask,
+	BufferPtr = XIpiPsu_GetBufferAddress(InstancePtr, SrcCpuMask,
 			InstancePtr->Config.BitMask, BufferType);
 	if (BufferPtr != NULL) {
 		/* Copy the IPI Buffer contents into Users's Buffer*/
-		for (Index = 0; Index < MsgLength; Index++) {
+		for (Index = 0U; Index < MsgLength; Index++) {
 			MsgPtr[Index] = BufferPtr[Index];
 		}
 		Status = XST_SUCCESS;
@@ -317,18 +318,18 @@ XStatus XIpiPsu_ReadMessage(XIpiPsu *InstancePtr, u32 TargetMask, u32 *MsgPtr,
  * @param	DestCpuMask is the Device Mask for the destination CPU
  * @param	MsgPtr is the pointer to Buffer which contains the message to be sent
  * @param	MsgLength is the length of the buffer/message
- * @param	BufType is the type of buffer (XIPIPSU_BUF_TYPE_MSG or XIPIPSU_BUF_TYPE_RESP)
+ * @param	BufferType is the type of buffer (XIPIPSU_BUF_TYPE_MSG or XIPIPSU_BUF_TYPE_RESP)
  *
  * @return	XST_SUCCESS if successful
  * 			XST_FAILURE if an error occurred
  */
 
-XStatus XIpiPsu_WriteMessage(XIpiPsu *InstancePtr, u32 TargetMask, u32 *MsgPtr,
+XStatus XIpiPsu_WriteMessage(XIpiPsu *InstancePtr, u32 DestCpuMask, u32 *MsgPtr,
 		u32 MsgLength, u8 BufferType)
 {
 	u32 *BufferPtr;
 	u32 Index;
-	u32 Status;
+	XStatus Status;
 
 	Xil_AssertNonvoid(InstancePtr != NULL);
 	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
@@ -336,10 +337,10 @@ XStatus XIpiPsu_WriteMessage(XIpiPsu *InstancePtr, u32 TargetMask, u32 *MsgPtr,
 	Xil_AssertNonvoid(MsgLength <= XIPIPSU_MAX_MSG_LEN);
 
 	BufferPtr = XIpiPsu_GetBufferAddress(InstancePtr,
-			InstancePtr->Config.BitMask, TargetMask, BufferType);
+			InstancePtr->Config.BitMask, DestCpuMask, BufferType);
 	if (BufferPtr != NULL) {
 		/* Copy the Message to IPI Buffer */
-		for (Index = 0; Index < MsgLength; Index++) {
+		for (Index = 0U; Index < MsgLength; Index++) {
 			BufferPtr[Index] = MsgPtr[Index];
 		}
 		Status = XST_SUCCESS;
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu.h
index 7eb8e5469..0253b9a68 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu.h
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2015 - 2016 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -272,10 +272,10 @@ XStatus XIpiPsu_PollForAck(XIpiPsu *InstancePtr, u32 DestCpuMask,
 		u32 TimeOutCount);
 
 XStatus XIpiPsu_ReadMessage(XIpiPsu *InstancePtr, u32 SrcCpuMask, u32 *MsgPtr,
-		u32 MsgLength, u8 BufType);
+		u32 MsgLength, u8 BufferType);
 
 XStatus XIpiPsu_WriteMessage(XIpiPsu *InstancePtr, u32 DestCpuMask, u32 *MsgPtr,
-		u32 MsgLength, u8 BufType);
+		u32 MsgLength, u8 BufferType);
 
 #endif /* XIPIPSU_H_ */
 /** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu_g.c
index f5728c502..afbbc5809 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu_g.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu_hw.h
index d24a8ea0a..b4c02b6e1 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu_hw.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu_hw.h
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2015 - 2016 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -43,6 +43,7 @@
 * Ver   Who Date     Changes
 * ----- --- -------- -----------------------------------------------.
 * 1.0   mjr  03/15/15 First release
+* 2.1   kvn  05/05/16 Modified code for MISRA-C:2012 Compliance
 *
 * </pre>
 *
@@ -54,7 +55,7 @@
 /* Message RAM related params */
 #define XIPIPSU_MSG_RAM_BASE 0xFF990000U
 #define XIPIPSU_MSG_BUF_SIZE 8U	/* Size in Words */
-#define XIPIPSU_MAX_BUFF_INDEX	7
+#define XIPIPSU_MAX_BUFF_INDEX	7U
 
 /* EIGHT pairs of TWO buffers(msg+resp) of THIRTY TWO bytes each */
 #define XIPIPSU_BUFFER_OFFSET_GROUP	(8U * 2U * 32U)
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu_sinit.c
index 26495c8dd..ae0900498 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu_sinit.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu_sinit.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2015 - 2016 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -44,6 +44,7 @@
 * Ver   Who Date     Changes
 * ----- --- -------- -----------------------------------------------
 * 1.0   mjr  03/15/15 First release
+* 2.1   kvn  05/05/16 Modified code for MISRA-C:2012 Compliance
 * </pre>
 *
 ******************************************************************************/
@@ -76,9 +77,9 @@ extern XIpiPsu_Config XIpiPsu_ConfigTable[];
 XIpiPsu_Config *XIpiPsu_LookupConfig(u32 DeviceId)
 {
 	XIpiPsu_Config *CfgPtr = NULL;
-	int Index;
+	u32 Index;
 
-	for (Index = 0; Index < XPAR_XIPIPSU_NUM_INSTANCES; Index++) {
+	for (Index = 0U; Index < XPAR_XIPIPSU_NUM_INSTANCES; Index++) {
 		if (XIpiPsu_ConfigTable[Index].DeviceId == DeviceId) {
 			CfgPtr = &XIpiPsu_ConfigTable[Index];
 			break;
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/Makefile
index 88a66dd93..88a66dd93 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/Makefile
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/Makefile
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu.c
index cd415ae07..93fa53f75 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu.c
@@ -52,6 +52,14 @@
 *       sk  04/24/15 Modified the code according to MISRAC-2012.
 *       sk  06/17/15 Removed NULL checks for Rx/Tx buffers. As
 *                    writing/reading from 0x0 location is permitted.
+* 1.1   sk  04/12/16 Added debug message prints.
+* 1.2	nsk 07/01/16 Changed XQspiPsu_Select to support GQSPI and LQSPI
+*		     selection.
+*       rk  07/15/16 Added support for TapDelays at different frequencies.
+*	nsk 08/05/16 Added example support PollData and PollTimeout
+* 1.3	nsk 09/16/16 Update PollData and PollTimeout support for dual
+*	             parallel configurations, modified XQspiPsu_PollData()
+*	             and XQspiPsu_Create_PollConfigData()
 *
 * </pre>
 *
@@ -83,6 +91,10 @@ static inline void XQspiPsu_GenFifoEntryData(XQspiPsu *InstancePtr,
 static inline void XQspiPsu_GenFifoEntryCSDeAssert(XQspiPsu *InstancePtr);
 static inline void XQspiPsu_ReadRxFifo(XQspiPsu *InstancePtr,
 			XQspiPsu_Msg *Msg, s32 Size);
+static inline void XQspiPsu_PollData(XQspiPsu *QspiPsuPtr,
+		XQspiPsu_Msg *FlashMsg);
+static inline u32 XQspiPsu_Create_PollConfigData(XQspiPsu *QspiPsuPtr,
+		XQspiPsu_Msg *FlashMsg);
 
 /************************** Variable Definitions *****************************/
 
@@ -137,7 +149,7 @@ s32 XQspiPsu_CfgInitialize(XQspiPsu *InstancePtr, XQspiPsu_Config *ConfigPtr,
 		InstancePtr->Config.ConnectionMode = ConfigPtr->ConnectionMode;
 		InstancePtr->StatusHandler = StubStatusHandler;
 		InstancePtr->Config.BusWidth = ConfigPtr->BusWidth;
-
+		InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
 		/* Other instance variable initializations */
 		InstancePtr->SendBufferPtr = NULL;
 		InstancePtr->RecvBufferPtr = NULL;
@@ -152,7 +164,7 @@ s32 XQspiPsu_CfgInitialize(XQspiPsu *InstancePtr, XQspiPsu_Config *ConfigPtr,
 		InstancePtr->IsManualstart = TRUE;
 
 		/* Select QSPIPSU */
-		XQspiPsu_Select(InstancePtr);
+		XQspiPsu_Select(InstancePtr, XQSPIPSU_SEL_GQSPI_MASK);
 
 		/*
 		 * Reset the QSPIPSU device to get it into its initial state. It is
@@ -343,12 +355,10 @@ void XQspiPsu_Abort(XQspiPsu *InstancePtr)
 s32 XQspiPsu_PolledTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
 				u32 NumMsg)
 {
-	u32 StatusReg;
-	u32 ConfigReg;
+
 	s32 Index;
-	u32 QspiPsuStatusReg, DmaStatusReg;
+	u32 QspiPsuStatusReg;
 	u32 BaseAddress;
-	s32 Status;
 	s32 RxThr;
 	u32 IOPending = (u32)FALSE;
 
@@ -391,6 +401,9 @@ s32 XQspiPsu_PolledTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
 		XQspiPsu_GenFifoEntryData(InstancePtr, Msg, Index);
 
 		if (InstancePtr->IsManualstart == TRUE) {
+#ifdef DEBUG
+	xil_printf("\nManual Start\r\n");
+#endif
 			XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_CFG_OFFSET,
 				XQspiPsu_ReadReg(BaseAddress,
 					XQSPIPSU_CFG_OFFSET) |
@@ -484,6 +497,9 @@ s32 XQspiPsu_PolledTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
 	XQspiPsu_GenFifoEntryCSDeAssert(InstancePtr);
 
 	if (InstancePtr->IsManualstart == TRUE) {
+#ifdef DEBUG
+	xil_printf("\nManual Start\r\n");
+#endif
 		XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_CFG_OFFSET,
 			XQspiPsu_ReadReg(BaseAddress, XQSPIPSU_CFG_OFFSET) |
 				XQSPIPSU_CFG_START_GEN_FIFO_MASK);
@@ -526,11 +542,9 @@ s32 XQspiPsu_PolledTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
 s32 XQspiPsu_InterruptTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
 				u32 NumMsg)
 {
-	u32 StatusReg;
-	u32 ConfigReg;
+
 	s32 Index;
 	u32 BaseAddress;
-	s32 Status;
 
 	Xil_AssertNonvoid(InstancePtr != NULL);
 	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
@@ -543,10 +557,14 @@ s32 XQspiPsu_InterruptTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
 		return (s32)XST_DEVICE_BUSY;
 	}
 
-	/* Check for ByteCount upper limit - 2^28 for DMA */
-	for (Index = 0; Index < (s32)NumMsg; Index++) {
-		if ((Msg[Index].ByteCount > XQSPIPSU_DMA_BYTES_MAX) &&
-				((Msg[Index].Flags & XQSPIPSU_MSG_FLAG_RX) != FALSE)) {
+	if (Msg[0].Flags & XQSPIPSU_MSG_FLAG_POLL) {
+		InstancePtr->IsBusy = TRUE;
+		XQspiPsu_PollData(InstancePtr, Msg);
+	} else {
+		/* Check for ByteCount upper limit - 2^28 for DMA */
+		for (Index = 0; Index < (s32)NumMsg; Index++) {
+			if ((Msg[Index].ByteCount > XQSPIPSU_DMA_BYTES_MAX) &&
+					((Msg[Index].Flags & XQSPIPSU_MSG_FLAG_RX) != FALSE)) {
 			return (s32)XST_FAILURE;
 		}
 	}
@@ -574,6 +592,9 @@ s32 XQspiPsu_InterruptTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
 	XQspiPsu_GenFifoEntryData(InstancePtr, Msg, 0);
 
 	if (InstancePtr->IsManualstart == TRUE) {
+#ifdef DEBUG
+	xil_printf("\nManual Start\r\n");
+#endif
 		XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_CFG_OFFSET,
 			XQspiPsu_ReadReg(BaseAddress, XQSPIPSU_CFG_OFFSET) |
 				XQSPIPSU_CFG_START_GEN_FIFO_MASK);
@@ -589,7 +610,7 @@ s32 XQspiPsu_InterruptTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
 		XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_QSPIDMA_DST_I_EN_OFFSET,
 				XQSPIPSU_QSPIDMA_DST_I_EN_DONE_MASK);
 	}
-
+	}
 	return XST_SUCCESS;
 }
 
@@ -636,8 +657,7 @@ s32 XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr)
 		XQspiPsu_WriteReg(BaseAddress,
 			XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET, DmaIntrStatusReg);
 	}
-	if (((QspiPsuStatusReg & XQSPIPSU_ISR_POLL_TIME_EXPIRE_MASK) != FALSE) ||
-		((DmaIntrStatusReg & XQSPIPSU_QSPIDMA_DST_INTR_ERR_MASK) != FALSE)) {
+	if (((DmaIntrStatusReg & XQSPIPSU_QSPIDMA_DST_INTR_ERR_MASK) != FALSE)) {
 		/* Call status handler to indicate error */
 		InstancePtr->StatusHandler(InstancePtr->StatusRef,
 					XST_SPI_COMMAND_ERROR, 0);
@@ -681,6 +701,9 @@ s32 XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr)
 				XQspiPsu_GenFifoEntryData(InstancePtr, Msg,
 						MsgCnt);
 				if(InstancePtr->IsManualstart == TRUE) {
+#ifdef DEBUG
+	xil_printf("\nManual Start\r\n");
+#endif
 					XQspiPsu_WriteReg(BaseAddress,
 						XQSPIPSU_CFG_OFFSET,
 						XQspiPsu_ReadReg(BaseAddress,
@@ -727,6 +750,7 @@ s32 XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr)
 	if ((MsgCnt < NumMsg) && (DeltaMsgCnt == FALSE) &&
 		((TxRxFlag & XQSPIPSU_MSG_FLAG_RX) == FALSE) &&
 		((TxRxFlag & XQSPIPSU_MSG_FLAG_TX) == FALSE) &&
+		((TxRxFlag & XQSPIPSU_MSG_FLAG_POLL) == FALSE) &&
 		((QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK) != FALSE)) {
 		MsgCnt += 1;
 		DeltaMsgCnt = 1U;
@@ -754,6 +778,9 @@ s32 XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr)
 			XQspiPsu_GenFifoEntryData(InstancePtr, Msg, MsgCnt);
 
 			if (InstancePtr->IsManualstart == TRUE) {
+#ifdef DEBUG
+	xil_printf("\nManual Start\r\n");
+#endif
 				XQspiPsu_WriteReg(BaseAddress,
 					XQSPIPSU_CFG_OFFSET,
 					XQspiPsu_ReadReg(BaseAddress,
@@ -769,6 +796,9 @@ s32 XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr)
 			XQspiPsu_GenFifoEntryCSDeAssert(InstancePtr);
 
 			if (InstancePtr->IsManualstart == TRUE) {
+#ifdef DEBUG
+	xil_printf("\nManual Start\r\n");
+#endif
 				XQspiPsu_WriteReg(BaseAddress,
 					XQSPIPSU_CFG_OFFSET,
 					XQspiPsu_ReadReg(BaseAddress,
@@ -800,7 +830,34 @@ s32 XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr)
 						XST_SPI_TRANSFER_DONE, 0);
 		}
 	}
+	if ((TxRxFlag & XQSPIPSU_MSG_FLAG_POLL) != FALSE){
+		 if (QspiPsuStatusReg & XQSPIPSU_ISR_RXNEMPTY_MASK){
+			 /*
+			  * Read data from RXFIFO, since when data from the flash device
+			  * (status data) matched with configured value in poll_cfg, then
+			  * controller writes the matched data into RXFIFO.
+			  */
+			XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress, XQSPIPSU_RXD_OFFSET);
+
+			XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_IDR_OFFSET,
+					(u32)XQSPIPSU_IER_TXNOT_FULL_MASK |
+					(u32)XQSPIPSU_IER_TXEMPTY_MASK |
+					(u32)XQSPIPSU_IER_RXNEMPTY_MASK |
+					(u32)XQSPIPSU_IER_GENFIFOEMPTY_MASK |
+					(u32)XQSPIPSU_IER_RXEMPTY_MASK |
+					(u32)XQSPIPSU_IER_POLL_TIME_EXPIRE_MASK);
+			InstancePtr->StatusHandler(InstancePtr->StatusRef, XST_SPI_POLL_DONE, 0);
 
+			InstancePtr->IsBusy = FALSE;
+			/* Disable the device. */
+			XQspiPsu_Disable(InstancePtr);
+
+		 }
+		 if (QspiPsuStatusReg & XQSPIPSU_ISR_POLL_TIME_EXPIRE_MASK){
+			InstancePtr->StatusHandler(InstancePtr->StatusRef,
+					XST_FLASH_TIMEOUT_ERROR, 0);
+		 }
+	}
 	return XST_SUCCESS;
 }
 
@@ -892,6 +949,11 @@ static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
 static inline u32 XQspiPsu_SelectSpiMode(u8 SpiMode)
 {
 	u32 Mask;
+
+#ifdef DEBUG
+	xil_printf("\nXQspiPsu_SelectSpiMode\r\n");
+#endif
+
 	switch (SpiMode) {
 		case XQSPIPSU_SELECT_MODE_DUALSPI:
 			Mask = XQSPIPSU_GENFIFO_MODE_DUALSPI;
@@ -906,6 +968,9 @@ static inline u32 XQspiPsu_SelectSpiMode(u8 SpiMode)
 			Mask = XQSPIPSU_GENFIFO_MODE_SPI;
 			break;
 	}
+#ifdef DEBUG
+	xil_printf("\nSPIMode is %08x\r\n", SpiMode);
+#endif
 
 	return Mask;
 }
@@ -1014,6 +1079,10 @@ static inline void XQspiPsu_FillTxFifo(XQspiPsu *InstancePtr,
 
 	Xil_AssertVoid(InstancePtr != NULL);
 
+#ifdef DEBUG
+	xil_printf("\nXQspiPsu_FillTxFifo\r\n");
+#endif
+
 	while ((InstancePtr->TxBytes > 0) && (Count < Size)) {
 		if (InstancePtr->TxBytes >= 4) {
 			(void)memcpy(&Data, Msg->TxBfrPtr, 4);
@@ -1028,6 +1097,9 @@ static inline void XQspiPsu_FillTxFifo(XQspiPsu *InstancePtr,
 		}
 		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
 				XQSPIPSU_TXD_OFFSET, Data);
+#ifdef DEBUG
+	xil_printf("\nData is %08x\r\n", Data);
+#endif
 
 	}
 	if (InstancePtr->TxBytes < 0) {
@@ -1104,6 +1176,10 @@ static inline void XQspiPsu_GenFifoEntryCSAssert(XQspiPsu *InstancePtr)
 {
 	u32 GenFifoEntry;
 
+#ifdef DEBUG
+	xil_printf("\nXQspiPsu_GenFifoEntryCSAssert\r\n");
+#endif
+
 	GenFifoEntry = 0x0U;
 	GenFifoEntry &= ~((u32)XQSPIPSU_GENFIFO_DATA_XFER | (u32)XQSPIPSU_GENFIFO_EXP);
 	GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_MODE_MASK);
@@ -1114,7 +1190,9 @@ static inline void XQspiPsu_GenFifoEntryCSAssert(XQspiPsu *InstancePtr)
 	GenFifoEntry &= ~(XQSPIPSU_GENFIFO_TX | XQSPIPSU_GENFIFO_RX |
 			XQSPIPSU_GENFIFO_STRIPE | XQSPIPSU_GENFIFO_POLL);
 	GenFifoEntry |= XQSPIPSU_GENFIFO_CS_SETUP;
-
+#ifdef DEBUG
+	xil_printf("\nFifoEntry=%08x\r\n",GenFifoEntry);
+#endif
 	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
 		XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry);
 }
@@ -1144,6 +1222,10 @@ static inline void XQspiPsu_GenFifoEntryData(XQspiPsu *InstancePtr,
 	u32 TempCount;
 	u32 ImmData;
 
+#ifdef DEBUG
+	xil_printf("\nXQspiPsu_GenFifoEntryData\r\n");
+#endif
+
 	BaseAddress = InstancePtr->Config.BaseAddress;
 
 	GenFifoEntry = 0x0U;
@@ -1177,6 +1259,9 @@ static inline void XQspiPsu_GenFifoEntryData(XQspiPsu *InstancePtr,
 	if (Msg[Index].ByteCount < XQSPIPSU_GENFIFO_IMM_DATA_MASK) {
 		GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_IMM_DATA_MASK);
 		GenFifoEntry |= Msg[Index].ByteCount;
+#ifdef DEBUG
+	xil_printf("\nFifoEntry=%08x\r\n",GenFifoEntry);
+#endif
 		XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_GEN_FIFO_OFFSET,
 				GenFifoEntry);
 	} else {
@@ -1190,6 +1275,9 @@ static inline void XQspiPsu_GenFifoEntryData(XQspiPsu *InstancePtr,
 			if ((TempCount & XQSPIPSU_GENFIFO_EXP_START) != FALSE) {
 				GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_IMM_DATA_MASK);
 				GenFifoEntry |= Exponent;
+#ifdef DEBUG
+	xil_printf("\nFifoEntry=%08x\r\n",GenFifoEntry);
+#endif
 				XQspiPsu_WriteReg(BaseAddress,
 					XQSPIPSU_GEN_FIFO_OFFSET,
 					GenFifoEntry);
@@ -1203,6 +1291,9 @@ static inline void XQspiPsu_GenFifoEntryData(XQspiPsu *InstancePtr,
 		if ((ImmData & 0xFFU) != FALSE) {
 			GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_IMM_DATA_MASK);
 			GenFifoEntry |= ImmData & 0xFFU;
+#ifdef DEBUG
+	xil_printf("\nFifoEntry=%08x\r\n",GenFifoEntry);
+#endif
 			XQspiPsu_WriteReg(BaseAddress,
 				XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry);
 		}
@@ -1212,6 +1303,9 @@ static inline void XQspiPsu_GenFifoEntryData(XQspiPsu *InstancePtr,
 	if ((InstancePtr->ReadMode == XQSPIPSU_READMODE_IO) &&
 			((Msg[Index].Flags & XQSPIPSU_MSG_FLAG_RX) != FALSE)) {
 		GenFifoEntry = 0x0U;
+#ifdef DEBUG
+	xil_printf("\nDummy FifoEntry=%08x\r\n",GenFifoEntry);
+#endif
 		XQspiPsu_WriteReg(BaseAddress,
 				XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry);
 	}
@@ -1233,6 +1327,10 @@ static inline void XQspiPsu_GenFifoEntryCSDeAssert(XQspiPsu *InstancePtr)
 {
 	u32 GenFifoEntry;
 
+#ifdef DEBUG
+	xil_printf("\nXQspiPsu_GenFifoEntryCSDeAssert\r\n");
+#endif
+
 	GenFifoEntry = 0x0U;
 	GenFifoEntry &= ~((u32)XQSPIPSU_GENFIFO_DATA_XFER | (u32)XQSPIPSU_GENFIFO_EXP);
 	GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_MODE_MASK);
@@ -1242,7 +1340,9 @@ static inline void XQspiPsu_GenFifoEntryCSDeAssert(XQspiPsu *InstancePtr)
 	GenFifoEntry &= ~(XQSPIPSU_GENFIFO_TX | XQSPIPSU_GENFIFO_RX |
 			XQSPIPSU_GENFIFO_STRIPE | XQSPIPSU_GENFIFO_POLL);
 	GenFifoEntry |= XQSPIPSU_GENFIFO_CS_HOLD;
-
+#ifdef DEBUG
+	xil_printf("\nFifoEntry=%08x\r\n",GenFifoEntry);
+#endif
 	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
 		XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry);
 }
@@ -1267,12 +1367,19 @@ static inline void XQspiPsu_ReadRxFifo(XQspiPsu *InstancePtr,
 	s32 Count = 0;
 	u32 Data;
 
+#ifdef DEBUG
+	xil_printf("\nXQspiPsu_ReadRxFifo\r\n");
+#endif
+
 	Xil_AssertVoid(InstancePtr != NULL);
 	Xil_AssertVoid(Msg != NULL);
 
 	while ((InstancePtr->RxBytes != 0) && (Count < Size)) {
 		Data = XQspiPsu_ReadReg(InstancePtr->
 				Config.BaseAddress, XQSPIPSU_RXD_OFFSET);
+#ifdef DEBUG
+	xil_printf("\nData is %08x\r\n", Data);
+#endif
 		if (InstancePtr->RxBytes >= 4) {
 			(void)memcpy(Msg->RxBfrPtr, &Data, 4);
 			InstancePtr->RxBytes -= 4;
@@ -1287,4 +1394,121 @@ static inline void XQspiPsu_ReadRxFifo(XQspiPsu *InstancePtr,
 		}
 	}
 }
+
+/*****************************************************************************/
+/**
+*
+* This function enables the polling functionality of controller
+*
+* @param	QspiPsuPtr is a pointer to the XQspiPsu instance.
+*
+* @param	Statuscommand is the status command which send by controller.
+*
+* @param	FlashMsg is a pointer to the structure containing transfer data
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XQspiPsu_PollData(XQspiPsu *QspiPsuPtr, XQspiPsu_Msg *FlashMsg)
+{
+
+	u32 GenFifoEntry ;
+	u32 Value;
+
+	Xil_AssertVoid(QspiPsuPtr != NULL);
+	Xil_AssertVoid(FlashMsg != NULL );
+
+	Value = XQspiPsu_Create_PollConfigData(QspiPsuPtr, FlashMsg);
+	XQspiPsu_WriteReg(QspiPsuPtr->Config.BaseAddress,
+			XQSPIPSU_POLL_CFG_OFFSET, Value);
+	XQspiPsu_WriteReg(QspiPsuPtr->Config.BaseAddress,
+			XQSPIPSU_P_TO_OFFSET, FlashMsg->PollTimeout);
+
+	XQspiPsu_Enable(QspiPsuPtr);
+
+	GenFifoEntry = (u32)0;
+	GenFifoEntry |= (u32)XQSPIPSU_GENFIFO_TX;
+	GenFifoEntry |= QspiPsuPtr->GenFifoBus;
+	GenFifoEntry |= QspiPsuPtr->GenFifoCS;
+	GenFifoEntry |= (u32)XQSPIPSU_GENFIFO_MODE_SPI;
+	GenFifoEntry |= (u32)FlashMsg->PollStatusCmd;
+
+	XQspiPsu_WriteReg(QspiPsuPtr->Config.BaseAddress,
+		XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry);
+	XQspiPsu_WriteReg(QspiPsuPtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
+				(XQSPIPSU_CFG_START_GEN_FIFO_MASK
+				| XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK));
+
+	GenFifoEntry = (u32)0;
+	GenFifoEntry = (u32)XQSPIPSU_GENFIFO_POLL;
+	GenFifoEntry |= (u32)XQSPIPSU_GENFIFO_RX;
+	GenFifoEntry |= QspiPsuPtr->GenFifoBus;
+	GenFifoEntry |= QspiPsuPtr->GenFifoCS;
+	GenFifoEntry |= (u32)XQSPIPSU_GENFIFO_MODE_SPI;
+	if (((FlashMsg->Flags) & XQSPIPSU_MSG_FLAG_STRIPE) != FALSE)
+		GenFifoEntry |= XQSPIPSU_GENFIFO_STRIPE;
+	else
+		GenFifoEntry &= ~XQSPIPSU_GENFIFO_STRIPE;
+
+	XQspiPsu_WriteReg(QspiPsuPtr->Config.BaseAddress,
+		XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry);
+
+	QspiPsuPtr->Msg = FlashMsg;
+	QspiPsuPtr->NumMsg = (s32)1;
+	QspiPsuPtr->MsgCnt = 0;
+
+	Value = XQspiPsu_ReadReg(QspiPsuPtr->Config.BaseAddress,
+			XQSPIPSU_CFG_OFFSET);
+	Value |= (XQSPIPSU_CFG_START_GEN_FIFO_MASK |
+			XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK |
+			XQSPIPSU_CFG_EN_POLL_TO_MASK);
+	XQspiPsu_WriteReg(QspiPsuPtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
+			Value);
+
+	/* Enable interrupts */
+	Value = ((u32)XQSPIPSU_IER_TXNOT_FULL_MASK |
+		(u32)XQSPIPSU_IER_TXEMPTY_MASK |
+		(u32)XQSPIPSU_IER_RXNEMPTY_MASK |
+		(u32)XQSPIPSU_IER_GENFIFOEMPTY_MASK |
+		(u32)XQSPIPSU_IER_RXEMPTY_MASK |
+		(u32)XQSPIPSU_IER_POLL_TIME_EXPIRE_MASK);
+	XQspiPsu_WriteReg(QspiPsuPtr->Config.BaseAddress, XQSPIPSU_IER_OFFSET,
+			Value);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function creates Poll config register data to write
+*
+* @param	BusMask is mask to enable/disable upper/lower data bus masks.
+*
+* @param	DataBusMask is Data bus mask value during poll operation.
+*
+* @param	Data is the poll data value to write into config regsiter.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static inline u32 XQspiPsu_Create_PollConfigData(XQspiPsu *QspiPsuPtr,
+		XQspiPsu_Msg *FlashMsg)
+{
+	u32 ConfigData = 0;
+
+	if (QspiPsuPtr->GenFifoBus & XQSPIPSU_GENFIFO_BUS_UPPER)
+		ConfigData = XQSPIPSU_SELECT_FLASH_BUS_LOWER <<
+			           XQSPIPSU_POLL_CFG_EN_MASK_UPPER_SHIFT;
+	if (QspiPsuPtr->GenFifoBus & XQSPIPSU_GENFIFO_BUS_LOWER)
+		ConfigData |= XQSPIPSU_SELECT_FLASH_BUS_LOWER <<
+			           XQSPIPSU_POLL_CFG_EN_MASK_LOWER_SHIFT;
+	ConfigData |= ((FlashMsg->PollBusMask << XQSPIPSU_POLL_CFG_MASK_EN_SHIFT)
+			& XQSPIPSU_POLL_CFG_MASK_EN_MASK);
+	ConfigData |= ((FlashMsg->PollData << XQSPIPSU_POLL_CFG_DATA_VALUE_SHIFT)
+		          & XQSPIPSU_POLL_CFG_DATA_VALUE_MASK);
+	return ConfigData;
+}
 /** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu.h
index d34438df6..94801949c 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu.h
@@ -95,6 +95,23 @@
 *       sk  04/24/15 Modified the code according to MISRAC-2012.
 *       sk  06/17/15 Removed NULL checks for Rx/Tx buffers. As
 *                    writing/reading from 0x0 location is permitted.
+* 1.1   sk  04/12/16 Added debug message prints.
+* 1.2	nsk 07/01/16 Added LQSPI support
+*		     Modified XQspiPsu_Select() macro in xqspipsu.h
+*		     Added XQspiPsu_GetLqspiConfigReg() in xqspipsu.h
+*		     Added required macros in xqspipsu_hw.h
+*		     Modified XQspiPsu_SetOptions() to support
+*		     LQSPI options and updated OptionsTable in
+*		     xqspipsu_options.c
+*       rk  07/15/16 Added support for TapDelays at different frequencies.
+*	nsk 08/05/16 Added example support PollData and PollTimeout
+*		     Added  XQSPIPSU_MSG_FLAG_POLL macro in xqspipsu.h
+*		     Added XQspiPsu_Create_PollConfigData and
+*		     XQspiPsu_PollData() functions in xqspipsu.c
+* 1.3	nsk 09/16/16 Update PollData and Polltimeout support for dual parallel
+*	             configuration. Updated XQspiPsu_PollData() and
+*	             XQspiPsu_Create_PollConfigData() functions in xqspipsu.c
+*                    and also modified the polldata example
 *
 * </pre>
 *
@@ -143,6 +160,10 @@ typedef struct {
 	u32 ByteCount;
 	u32 BusWidth;
 	u32 Flags;
+	u8 PollData;
+	u32 PollTimeout;
+	u8 PollStatusCmd;
+	u8 PollBusMask;
 } XQspiPsu_Msg;
 
 /**
@@ -207,6 +228,7 @@ typedef struct {
 #define XQSPIPSU_CLK_ACTIVE_LOW_OPTION	0x2U
 #define XQSPIPSU_CLK_PHASE_1_OPTION	0x4U
 #define XQSPIPSU_MANUAL_START_OPTION	0x8U
+#define XQSPIPSU_LQSPI_MODE_OPTION	0x20U
 
 #define XQSPIPSU_GENFIFO_EXP_START	0x100U
 
@@ -226,17 +248,25 @@ typedef struct {
 #define XQSPIPSU_CONNECTION_MODE_STACKED	1U
 #define XQSPIPSU_CONNECTION_MODE_PARALLEL	2U
 
+/*QSPI Frequencies*/
+#define XQSPIPSU_FREQ_40MHZ 40000000
+#define XQSPIPSU_FREQ_100MHZ 100000000
+#define XQSPIPSU_FREQ_150MHZ 150000000
+
 /* Add more flags as required */
 #define XQSPIPSU_MSG_FLAG_STRIPE	0x1U
 #define XQSPIPSU_MSG_FLAG_RX		0x2U
 #define XQSPIPSU_MSG_FLAG_TX		0x4U
+#define XQSPIPSU_MSG_FLAG_POLL		0x8U
 
-#define XQspiPsu_Select(InstancePtr)	XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + XQSPIPSU_SEL_OFFSET, XQSPIPSU_SEL_MASK)
+#define XQspiPsu_Select(InstancePtr, Mask)	XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + XQSPIPSU_SEL_OFFSET, Mask)
 
 #define XQspiPsu_Enable(InstancePtr)	XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + XQSPIPSU_EN_OFFSET, XQSPIPSU_EN_MASK)
 
 #define XQspiPsu_Disable(InstancePtr)	XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + XQSPIPSU_EN_OFFSET, 0x0U)
 
+#define XQspiPsu_GetLqspiConfigReg(InstancePtr)   XQspiPsu_In32((XQSPIPS_BASEADDR) + XQSPIPSU_LQSPI_CR_OFFSET)
+
 /************************** Function Prototypes ******************************/
 
 /* Initialization and reset */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_g.c
index daa5bde27..969fa96b0 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu_g.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_hw.h
index 508109019..40314d6e1 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu_hw.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_hw.h
@@ -47,6 +47,8 @@
 * 1.0   hk  08/21/14 First release
 *       hk  03/18/15 Add DMA status register masks required.
 *       sk  04/24/15 Modified the code according to MISRAC-2012.
+* 1.2	nsk 07/01/16 Added LQSPI supported Masks
+*       rk  07/15/16 Added support for TapDelays at different frequencies.
 *
 * </pre>
 *
@@ -91,6 +93,7 @@ extern "C" {
  * Register: XQSPIPSU_CFG
  */
 #define XQSPIPSU_CFG_OFFSET    0X00000000U
+#define XQSPIPSU_LQSPI_CR_OFFSET    0X000000A0U
 
 #define XQSPIPSU_CFG_MODE_EN_SHIFT   30
 #define XQSPIPSU_CFG_MODE_EN_WIDTH   2
@@ -130,6 +133,22 @@ extern "C" {
 #define XQSPIPSU_CFG_CLK_POL_MASK    0X00000002U
 
 /**
+ * Register: XQSPIPSU_CFG
+ */
+#define XQSPIPSU_LQSPI_CR_OFFSET	0X000000A0U
+#define XQSPIPSU_LQSPI_CR_LINEAR_MASK     0x80000000 /**< LQSPI mode enable */
+#define XQSPIPSU_LQSPI_CR_TWO_MEM_MASK    0x40000000 /**< Both memories or one */
+#define XQSPIPSU_LQSPI_CR_SEP_BUS_MASK    0x20000000 /**< Seperate memory bus */
+#define XQSPIPSU_LQSPI_CR_U_PAGE_MASK     0x10000000 /**< Upper memory page */
+#define XQSPIPSU_LQSPI_CR_ADDR_32BIT_MASK     0x01000000 /**< Upper memory page */
+#define XQSPIPSU_LQSPI_CR_MODE_EN_MASK    0x02000000 /**< Enable mode bits */
+#define XQSPIPSU_LQSPI_CR_MODE_ON_MASK    0x01000000 /**< Mode on */
+#define XQSPIPSU_LQSPI_CR_MODE_BITS_MASK  0x00FF0000 /**< Mode value for dual I/O
+                                                         or quad I/O */
+#define XQSPIPS_LQSPI_CR_INST_MASK       0x000000FF /**< Read instr code */
+#define XQSPIPS_LQSPI_CR_RST_STATE       0x80000003 /**< Default LQSPI CR value */
+#define XQSPIPS_LQSPI_CFG_RST_STATE       0x800238C1 /**< Default LQSPI CFG value */
+/**
  * Register: XQSPIPSU_ISR
  */
 #define XQSPIPSU_ISR_OFFSET	0X00000004U
@@ -406,7 +425,8 @@ extern "C" {
 
 #define XQSPIPSU_SEL_SHIFT   0
 #define XQSPIPSU_SEL_WIDTH   1
-#define XQSPIPSU_SEL_MASK    0X00000001U
+#define XQSPIPSU_SEL_LQSPI_MASK    0X0U
+#define XQSPIPSU_SEL_GQSPI_MASK    0X00000001U
 
 /**
  * Register: XQSPIPSU_FIFO_CTRL
@@ -792,6 +812,23 @@ extern "C" {
 #define XQSPIPSU_GENFIFO_STRIPE		0x40000U
 #define XQSPIPSU_GENFIFO_POLL		0x80000U
 
+/*QSPI Data delay register*/
+#define XQSPIPSU_DATA_DLY_ADJ_OFFSET    0X000000F8U
+
+#define XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_SHIFT   31
+#define XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_WIDTH   1
+#define XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_MASK    0X80000000U
+
+#define XQSPIPSU_DATA_DLY_ADJ_DLY_SHIFT   28
+#define XQSPIPSU_DATA_DLY_ADJ_DLY_WIDTH   3
+#define XQSPIPSU_DATA_DLY_ADJ_DLY_MASK    0X70000000U
+
+/* Tapdelay Bypass register*/
+#define IOU_TAPDLY_BYPASS_OFFSET 0X00000390
+#define IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT 0X02
+#define IOU_TAPDLY_BYPASS_LQSPI_RX_WIDTH 0X01
+#define IOU_TAPDLY_BYPASS_LQSPI_RX_MASK 0x00000004
+
 /***************** Macros (Inline Functions) Definitions *********************/
 
 #define XQspiPsu_In32 Xil_In32
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu_options.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_options.c
index 97eee8cfd..2c77a0881 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu_options.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_options.c
@@ -47,6 +47,10 @@
 * 1.0   hk  08/21/14 First release
 *       sk  03/13/15 Added IO mode support.
 *       sk  04/24/15 Modified the code according to MISRAC-2012.
+* 1.1   sk  04/12/16 Added debug message prints.
+* 1.2	nsk 07/01/16 Modified XQspiPsu_SetOptions() to support
+*		     LQSPI options and updated OptionsTable
+*       rk  07/15/16 Added support for TapDelays at different frequencies.
 *
 * </pre>
 *
@@ -62,8 +66,23 @@
 
 /***************** Macros (Inline Functions) Definitions *********************/
 
+#if defined (ARMR5) || (__aarch64__)
+#define TAPDLY_BYPASS_VALVE_40MHZ 0x01
+#define TAPDLY_BYPASS_VALVE_100MHZ 0x01
+#define USE_DLY_LPBK  0x01
+#define USE_DATA_DLY_ADJ 0x01
+#define DATA_DLY_ADJ_DLY 0X02
+#define LPBK_DLY_ADJ_DLY0 0X02
+#endif
+
 /************************** Function Prototypes ******************************/
 
+#if defined (ARMR5) || (__aarch64__)
+s32 XQspi_Set_TapDelay(XQspiPsu * InstancePtr,u32 TapdelayBypass,
+						u32 LPBKDelay,u32 Datadelay);
+static s32 XQspipsu_Calculate_Tapdelay(XQspiPsu *InstancePtr, u8 Prescaler);
+#endif
+
 /************************** Variable Definitions *****************************/
 
 /*
@@ -80,6 +99,7 @@ static OptionsMap OptionsTable[] = {
 	{XQSPIPSU_CLK_ACTIVE_LOW_OPTION, XQSPIPSU_CFG_CLK_POL_MASK},
 	{XQSPIPSU_CLK_PHASE_1_OPTION, XQSPIPSU_CFG_CLK_PHA_MASK},
 	{XQSPIPSU_MANUAL_START_OPTION, XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK},
+	{XQSPIPSU_LQSPI_MODE_OPTION, XQSPIPSU_CFG_WP_HOLD_MASK},
 };
 
 #define XQSPIPSU_NUM_OPTIONS	(sizeof(OptionsTable) / sizeof(OptionsMap))
@@ -127,7 +147,8 @@ s32 XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options)
 
 		ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
 					      XQSPIPSU_CFG_OFFSET);
-
+		QspiPsuOptions = Options & XQSPIPSU_LQSPI_MODE_OPTION;
+		Options &= ~XQSPIPSU_LQSPI_MODE_OPTION;
 		/*
 		 * Loop through the options table, turning the option on
 		 * depending on whether the bit is set in the incoming options flag.
@@ -136,9 +157,12 @@ s32 XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options)
 			if ((Options & OptionsTable[Index].Option) != FALSE) {
 				/* Turn it on */
 				ConfigReg |= OptionsTable[Index].Mask;
-			}
-		}
+			} else {
+                /* Turn it off */
+                ConfigReg &= ~(OptionsTable[Index].Mask);
+        }
 
+		}
 		/*
 		 * Now write the control register. Leave it to the upper layers
 		 * to restart the device.
@@ -149,6 +173,21 @@ s32 XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options)
 		if ((Options & XQSPIPSU_MANUAL_START_OPTION) != FALSE) {
 			InstancePtr->IsManualstart = TRUE;
 		}
+		/*
+		 * Check for the LQSPI configuration options.
+		 */
+		ConfigReg = XQspiPsu_ReadReg(XQSPIPS_BASEADDR,XQSPIPSU_LQSPI_CR_OFFSET);
+
+			if (QspiPsuOptions & XQSPIPSU_LQSPI_MODE_OPTION) {
+			XQspiPsu_WriteReg(XQSPIPS_BASEADDR,XQSPIPSU_LQSPI_CR_OFFSET,XQSPIPS_LQSPI_CR_RST_STATE);
+			XQspiPsu_WriteReg(XQSPIPS_BASEADDR,XQSPIPSU_CFG_OFFSET,XQSPIPS_LQSPI_CFG_RST_STATE);
+			/* Enable the QSPI controller */
+			XQspiPsu_WriteReg(XQSPIPS_BASEADDR,XQSPIPSU_EN_OFFSET,XQSPIPSU_EN_MASK);
+		}
+		 else {
+			ConfigReg &= ~(XQSPIPSU_LQSPI_CR_LINEAR_MASK);
+			XQspiPsu_WriteReg(XQSPIPS_BASEADDR,XQSPIPSU_LQSPI_CR_OFFSET, ConfigReg);
+		}
 
 		Status = XST_SUCCESS;
 	}
@@ -183,7 +222,6 @@ s32 XQspiPsu_ClearOptions(XQspiPsu *InstancePtr, u32 Options)
 {
 	u32 ConfigReg;
 	u32 Index;
-	u32 QspiPsuOptions;
 	s32 Status;
 
 	Xil_AssertNonvoid(InstancePtr != NULL);
@@ -270,6 +308,119 @@ u32 XQspiPsu_GetOptions(XQspiPsu *InstancePtr)
 	return OptionsFlag;
 }
 
+#if defined (ARMR5) || (__aarch64__)
+/*****************************************************************************/
+/**
+*
+* This function sets the Tapdelay values for the QSPIPSU device driver.The device
+* must be idle rather than busy transferring data before setting Tapdelay.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	TapdelayBypss contains the IOU_TAPDLY_BYPASS register value.
+* @param	LPBKDelay contains the GQSPI_LPBK_DLY_ADJ register value.
+* @param	Datadelay contains the QSPI_DATA_DLY_ADJ register value.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_DEVICE_BUSY if the device is currently transferring data.
+*		The transfer must complete or be aborted before setting TapDelay.
+*
+* @note
+* This function is not thread-safe.
+*
+******************************************************************************/
+s32 XQspi_Set_TapDelay(XQspiPsu * InstancePtr,u32 TapdelayBypass,
+						u32 LPBKDelay,u32 Datadelay)
+{
+	s32 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Do not allow to modify the Control Register while a transfer is in
+	 * progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy == TRUE) {
+		Status = XST_DEVICE_BUSY;
+	} else {
+		XQspiPsu_WriteReg(XPS_SYS_CTRL_BASEADDR,IOU_TAPDLY_BYPASS_OFFSET,
+				TapdelayBypass);
+		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XQSPIPSU_LPBK_DLY_ADJ_OFFSET,LPBKDelay);
+		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XQSPIPSU_DATA_DLY_ADJ_OFFSET,Datadelay);
+		Status = XST_SUCCESS;
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* Configures the clock according to the prescaler passed.
+*
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	Prescaler - clock prescaler.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_DEVICE_BUSY if the device is currently transferring data.
+*		The transfer must complete or be aborted before setting Tapdelay.
+*
+* @note		None.
+*
+******************************************************************************/
+static s32 XQspipsu_Calculate_Tapdelay(XQspiPsu *InstancePtr, u8 Prescaler)
+{
+	u32 FreqDiv, Divider, Tapdelay, LBkModeReg, delayReg;
+	s32 Status;
+
+	Divider = (1 << (Prescaler+1));
+
+	FreqDiv = (InstancePtr->Config.InputClockHz)/Divider;
+	Tapdelay = XQspiPsu_ReadReg(XPS_SYS_CTRL_BASEADDR,
+					IOU_TAPDLY_BYPASS_OFFSET);
+
+	Tapdelay = Tapdelay & (~IOU_TAPDLY_BYPASS_LQSPI_RX_MASK);
+
+	LBkModeReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+			XQSPIPSU_LPBK_DLY_ADJ_OFFSET);
+
+	LBkModeReg = (LBkModeReg &
+			(~(XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_MASK))) &
+			(LBkModeReg & (~(XQSPIPSU_LPBK_DLY_ADJ_DLY1_MASK))) &
+			(LBkModeReg & (~(XQSPIPSU_LPBK_DLY_ADJ_DLY0_MASK)));
+
+	delayReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+			XQSPIPSU_DATA_DLY_ADJ_OFFSET);
+
+	delayReg = (delayReg &
+			(~(XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_MASK))) &
+			(delayReg & (~( XQSPIPSU_DATA_DLY_ADJ_DLY_MASK)));
+
+	if(FreqDiv < XQSPIPSU_FREQ_40MHZ){
+		Tapdelay = Tapdelay |
+				(TAPDLY_BYPASS_VALVE_40MHZ << IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT);
+	} else if (FreqDiv <= XQSPIPSU_FREQ_100MHZ) {
+		Tapdelay = Tapdelay | (TAPDLY_BYPASS_VALVE_100MHZ << IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT);
+		LBkModeReg = LBkModeReg |
+				(USE_DLY_LPBK <<  XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_SHIFT);
+		delayReg = delayReg |
+				(USE_DATA_DLY_ADJ  << XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_SHIFT) |
+				(DATA_DLY_ADJ_DLY  << XQSPIPSU_DATA_DLY_ADJ_DLY_SHIFT);
+	} else if (FreqDiv <= XQSPIPSU_FREQ_150MHZ) {
+		LBkModeReg = LBkModeReg |
+				(USE_DLY_LPBK  <<  XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_SHIFT ) |
+				(LPBK_DLY_ADJ_DLY0  << XQSPIPSU_LPBK_DLY_ADJ_DLY0_SHIFT);
+	}
+	Status = XQspi_Set_TapDelay(InstancePtr, Tapdelay, LBkModeReg, delayReg);
+
+	return Status;
+}
+#endif
+
 /*****************************************************************************/
 /**
 *
@@ -282,6 +433,7 @@ u32 XQspiPsu_GetOptions(XQspiPsu *InstancePtr)
 * @return
 *		- XST_SUCCESS if successful.
 *		- XST_DEVICE_IS_STARTED if the device is already started.
+*		- XST_DEVICE_BUSY if the device is currently transferring data.
 *		It must be stopped to re-initialize.
 *
 * @note		None.
@@ -319,7 +471,11 @@ s32 XQspiPsu_SetClkPrescaler(XQspiPsu *InstancePtr, u8 Prescaler)
 		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
 				  XQSPIPSU_CFG_OFFSET, ConfigReg);
 
+#if defined (ARMR5) || (__aarch64__)
+		Status = XQspipsu_Calculate_Tapdelay(InstancePtr,Prescaler);
+#else
 		Status = XST_SUCCESS;
+#endif
 	}
 
 	return Status;
@@ -351,6 +507,10 @@ void XQspiPsu_SelectFlash(XQspiPsu *InstancePtr, u8 FlashCS, u8 FlashBus)
 {
 	Xil_AssertVoid(InstancePtr != NULL);
 
+#ifdef DEBUG
+	xil_printf("\nXQspiPsu_SelectFlash\r\n");
+#endif
+
 	/*
 	 * Bus and CS lines selected here will be updated in the instance and
 	 * used for subsequent GENFIFO entries during transfer.
@@ -389,6 +549,11 @@ void XQspiPsu_SelectFlash(XQspiPsu *InstancePtr, u8 FlashCS, u8 FlashBus)
 			InstancePtr->GenFifoBus = XQSPIPSU_GENFIFO_BUS_LOWER;
 			break;
 	}
+#ifdef DEBUG
+	xil_printf("\nGenFifoCS is %08x and GenFifoBus is %08x\r\n",
+				InstancePtr->GenFifoCS, InstancePtr->GenFifoBus);
+#endif
+
 }
 
 /*****************************************************************************/
@@ -416,6 +581,10 @@ s32 XQspiPsu_SetReadMode(XQspiPsu *InstancePtr, u32 Mode)
 	u32 ConfigReg;
 	s32 Status;
 
+#ifdef DEBUG
+	xil_printf("\nXQspiPsu_SetReadMode\r\n");
+#endif
+
 	Xil_AssertNonvoid(InstancePtr != NULL);
 	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
@@ -444,6 +613,9 @@ s32 XQspiPsu_SetReadMode(XQspiPsu *InstancePtr, u32 Mode)
 
 		Status = XST_SUCCESS;
 	}
+#ifdef DEBUG
+	xil_printf("\nRead Mode is %08x\r\n", InstancePtr->ReadMode);
+#endif
 	return Status;
 }
 /** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_sinit.c
index 63aaed0bb..63aaed0bb 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu_sinit.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_sinit.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/Makefile
index dc8cbdf6b..dc8cbdf6b 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/Makefile
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/Makefile
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu.c
index 58163eb34..c91f61279 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu.c
@@ -52,6 +52,7 @@
 *                       switching when vcc_psaux is not available.
 * 1.2          02/15/16 Corrected Calibration mask and Fractional
 *                       mask in CalculateCalibration API.
+* 1.3   vak    04/25/16 Corrected the RTC read and write time logic(cr#948833).
 * </pre>
 *
 ******************************************************************************/
@@ -59,6 +60,7 @@
 /***************************** Include Files *********************************/
 
 #include "xrtcpsu.h"
+#include "xrtcpsu_hw.h"
 
 /************************** Constant Definitions *****************************/
 
@@ -139,6 +141,10 @@ s32 XRtcPsu_CfgInitialize(XRtcPsu *InstancePtr, XRtcPsu_Config *ConfigPtr,
 	/* Indicate the component is now ready to use. */
 	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
 
+	/* Clear TimeUpdated and CurrTimeUpdated */
+	InstancePtr->TimeUpdated = 0;
+	InstancePtr->CurrTimeUpdated = 0;
+
 	Status = XST_SUCCESS;
 	return Status;
 }
@@ -169,6 +175,90 @@ static void XRtcPsu_StubHandler(void *CallBackRef, u32 Event)
 /****************************************************************************/
 /**
 *
+* This function sets the RTC time by writing into rtc write register.
+*
+* @param	InstancePtr is a pointer to the XRtcPsu instance.
+* @param	Time that should be updated into RTC write register.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XRtcPsu_SetTime(XRtcPsu *InstancePtr,u32 Time)
+{
+	/* Set the calibration value in calibration register, so that
+	 * next Second is triggered exactly at 1 sec period
+	 */
+	XRtcPsu_WriteReg(InstancePtr->RtcConfig.BaseAddr + XRTC_CALIB_WR_OFFSET,
+							InstancePtr->CalibrationValue);
+	/* clear the RTC secs interrupt from status register */
+	XRtcPsu_WriteReg(InstancePtr->RtcConfig.BaseAddr + XRTC_INT_STS_OFFSET,
+								XRTC_INT_STS_SECS_MASK);
+	InstancePtr->CurrTimeUpdated = 0;
+	/* Update the flag before setting the time */
+	InstancePtr->TimeUpdated = 1;
+	/* Since RTC takes 1 sec to update the time into current time register, write
+	 * load time + 1sec into the set time register.
+	 */
+	XRtcPsu_WriteSetTime(InstancePtr, Time + 1);
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the current RTC time.
+*
+* @param	InstancePtr is a pointer to the XRtcPsu instance.
+*
+* @return	RTC Current time.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XRtcPsu_GetCurrentTime(XRtcPsu *InstancePtr)
+{
+	u32 Status, IntMask, CurrTime;
+
+	IntMask = XRtcPsu_ReadReg(InstancePtr->RtcConfig.BaseAddr + XRTC_INT_MSK_OFFSET);
+
+	if((IntMask & XRTC_INT_STS_SECS_MASK) != (u32)0) {
+		/* We come here if interrupts are disabled */
+		Status = XRtcPsu_ReadReg(InstancePtr->RtcConfig.BaseAddr + XRTC_INT_STS_OFFSET);
+		if((InstancePtr->TimeUpdated == (u32)1) &&
+			(Status & XRTC_INT_STS_SECS_MASK) == (u32)0) {
+			/* Give the previous written time */
+			CurrTime = XRtcPsu_GetLastSetTime(InstancePtr) - 1;
+		} else {
+			/* Clear TimeUpdated */
+			if((InstancePtr->TimeUpdated == (u32)1) &&
+				((Status & XRTC_INT_STS_SECS_MASK) == (u32)1)) {
+				InstancePtr->TimeUpdated = (u32)0;
+			}
+
+			/* RTC time got updated */
+			CurrTime = XRtcPsu_ReadCurrentTime(InstancePtr);
+		}
+	} else {
+		/* We come here if interrupts are enabled */
+		if((InstancePtr->TimeUpdated == (u32)1) &&
+			(InstancePtr->CurrTimeUpdated == (u32)0)) {
+			/* Give the previous written time -1 sec */
+			CurrTime = XRtcPsu_GetLastSetTime(InstancePtr) - 1;
+		} else {
+			/* Clear TimeUpdated */
+			if(InstancePtr->TimeUpdated == (u32)1)
+				InstancePtr->TimeUpdated = (u32)0;
+			/* RTC time got updated */
+			CurrTime = XRtcPsu_ReadCurrentTime(InstancePtr);
+		}
+	}
+	return CurrTime;
+}
+
+/****************************************************************************/
+/**
+*
 * This function sets the alarm value of RTC device.
 *
 * @param	InstancePtr is a pointer to the XRtcPsu instance
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu.h
index 98e668911..164ddf64a 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu.h
@@ -100,6 +100,7 @@
 * 1.00  kvn    04/21/15 First release
 * 1.1   kvn    09/25/15 Modify control register to enable battery
 *                       switching when vcc_psaux is not available.
+* 1.3   vak    04/25/16 Corrected the RTC read and write time logic(cr#948833).
 * </pre>
 *
 ******************************************************************************/
@@ -179,6 +180,8 @@ typedef struct {
 	u32 CalibrationValue;
 	XRtcPsu_Handler Handler;
 	void *CallBackRef;			/**< Callback reference for event handler */
+	u32 TimeUpdated;
+	u32 CurrTimeUpdated;
 } XRtcPsu;
 
 /**
@@ -217,7 +220,7 @@ typedef struct {
 * 		void XRtcPsu_SetTime(XRtcPsu *InstancePtr, u32 Time)
 *
 *****************************************************************************/
-#define XRtcPsu_SetTime(InstancePtr,Time) \
+#define XRtcPsu_WriteSetTime(InstancePtr,Time) \
 	XRtcPsu_WriteReg(((InstancePtr)->RtcConfig.BaseAddr + \
 				XRTC_SET_TIME_WR_OFFSET),(Time))
 
@@ -264,10 +267,10 @@ typedef struct {
 * @return	Current Time. This current time will be in seconds.
 *
 * @note		C-Style signature:
-* 		u32 XRtcPsu_GetCurrentTime(XRtcPsu *InstancePtr)
+* 		u32 XRtcPsu_ReadCurrentTime(XRtcPsu *InstancePtr)
 *
 *****************************************************************************/
-#define XRtcPsu_GetCurrentTime(InstancePtr) \
+#define XRtcPsu_ReadCurrentTime(InstancePtr) \
 	XRtcPsu_ReadReg((InstancePtr)->RtcConfig.BaseAddr+XRTC_CUR_TIME_OFFSET)
 
 /****************************************************************************/
@@ -368,6 +371,8 @@ void XRtcPsu_CalculateCalibration(XRtcPsu *InstancePtr,u32 TimeReal,
 		u32 CrystalOscFreq);
 u32 XRtcPsu_IsSecondsEventGenerated(XRtcPsu *InstancePtr);
 u32 XRtcPsu_IsAlarmEventGenerated(XRtcPsu *InstancePtr);
+u32 XRtcPsu_GetCurrentTime(XRtcPsu *InstancePtr);
+void XRtcPsu_SetTime(XRtcPsu *InstancePtr,u32 Time);
 
 /* interrupt functions in xrtcpsu_intr.c */
 void XRtcPsu_SetInterruptMask(XRtcPsu *InstancePtr, u32 Mask);
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_g.c
index 8dc37775a..5913cd8d4 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_g.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_hw.h
index 532ef7e3c..532ef7e3c 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_hw.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_hw.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_intr.c
index bca20af12..89d3cd990 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_intr.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_intr.c
@@ -44,6 +44,8 @@
 * Ver   Who    Date	Changes
 * ----- -----  -------- -----------------------------------------------
 * 1.00  kvn    04/21/15 First release
+* 1.3   vak    04/25/16 Changed the XRtcPsu_InterruptHandler() for updating RTC
+*                       read and write time logic(cr#948833).
 * </pre>
 *
 ******************************************************************************/
@@ -219,6 +221,14 @@ void XRtcPsu_InterruptHandler(XRtcPsu *InstancePtr)
 
 	/* Seconds interrupt */
 	if((IsrStatus & XRTC_INT_STS_SECS_MASK) != (u32)0) {
+		/* Set the CurrTimeUpdated flag to 1 */
+		InstancePtr->CurrTimeUpdated = 1;
+
+		if(InstancePtr->TimeUpdated == (u32)1) {
+			/* Clear the TimeUpdated */
+			InstancePtr->TimeUpdated = (u32)0;
+		}
+
 		/*
 		 * Call the application handler to indicate that there is an
 		 * seconds interrupt. If the application cares about this seconds
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_selftest.c
index 67c562c64..67c562c64 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_selftest.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_selftest.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_sinit.c
index d3a8b7dfc..d3a8b7dfc 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_sinit.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_sinit.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/Makefile
index 04867a484..04867a484 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/Makefile
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/Makefile
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic.c
index 1806274c7..bf7ac12e8 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -46,44 +46,67 @@
 * ----- ---- -------- --------------------------------------------------------
 * 1.00a drg  01/19/10 First release
 * 1.01a sdm  11/09/11 Changes are made in function XScuGic_CfgInitialize. Since
-*		      "Config" entry is now made as pointer in the XScuGic
-*		      structure, necessary changes are made.
-*		      The HandlerTable can now be populated through the low
-*		      level routine XScuGic_RegisterHandler added in this
-*		      release. Hence necessary checks are added not to
-*		      overwrite the HandlerTable entriesin function
-*		      XScuGic_CfgInitialize.
+*		      		  "Config" entry is now made as pointer in the XScuGic
+*		      		  structure, necessary changes are made.
+*		      		  The HandlerTable can now be populated through the low
+*		      		  level routine XScuGic_RegisterHandler added in this
+*		      		  release. Hence necessary checks are added not to
+*		      		  overwrite the HandlerTable entriesin function
+*		      		  XScuGic_CfgInitialize.
 * 1.03a srt  02/27/13 Added APIs
-*			- XScuGic_SetPriTrigTypeByDistAddr()
-*			- XScuGic_GetPriTrigTypeByDistAddr()
-* 		      Removed Offset calculation macros, defined in _hw.h
-*		      (CR 702687)
-*			  Added support to direct interrupts to the appropriate CPU. Earlier
-*			  interrupts were directed to CPU1 (hard coded). Now depending
-*			  upon the CPU selected by the user (xparameters.h), interrupts
-*			  will be directed to the relevant CPU. This fixes CR 699688.
+*					  - XScuGic_SetPriTrigTypeByDistAddr()
+*					  - XScuGic_GetPriTrigTypeByDistAddr()
+* 		    		  Removed Offset calculation macros, defined in _hw.h
+*		      		  (CR 702687)
+*			  		  Added support to direct interrupts to the appropriate CPU. Earlier
+*			  		  interrupts were directed to CPU1 (hard coded). Now depending
+*			  		  upon the CPU selected by the user (xparameters.h), interrupts
+*			  		  will be directed to the relevant CPU. This fixes CR 699688.
 *
 * 1.04a hk   05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
-*			  XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
-*			  Moved functions XScuGic_SetPriTrigTypeByDistAddr and
-*             XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
-*			  This is fix for CR#705621.
+*			  		  XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
+*			  		  Moved functions XScuGic_SetPriTrigTypeByDistAddr and
+*             		  XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
+*			  		  This is fix for CR#705621.
 * 1.06a asa  16/11/13 Fix for CR#749178. Assignment for EffectiveAddr
-*			  in function XScuGic_CfgInitialize is removed as it was
-*		      a bug.
+*			  		  in function XScuGic_CfgInitialize is removed as it was
+*		      		  a bug.
 * 3.00  kvn  02/13/14 Modified code for MISRA-C:2012 compliance.
 * 3.01	pkp	 06/19/15 Added XScuGic_InterruptMaptoCpu API for an interrupt
-*			  target CPU mapping
+*			  		  target CPU mapping
 * 3.02	pkp	 11/09/15 Modified DistributorInit function for AMP case to add
 *					  the current cpu to interrupt processor targets registers
 * 3.2   asa  02/29/16 Modified DistributorInit function for Zynq AMP case. The
-*			  distributor is left uninitialized for Zynq AMP. It is assumed
-*             that the distributor will be initialized by Linux master. However
-*             for CortexR5 case, the earlier code is left unchanged where the
-*             the interrupt processor target registers in the distributor is
-*             initialized with the corresponding CPU ID on which the application
-*             built over the scugic driver runs.
-*             These changes fix CR#937243.
+*			  		  distributor is left uninitialized for Zynq AMP. It is assumed
+*             		  that the distributor will be initialized by Linux master. However
+*             		  for CortexR5 case, the earlier code is left unchanged where the
+*             		  the interrupt processor target registers in the distributor is
+*             		  initialized with the corresponding CPU ID on which the application
+*             		  built over the scugic driver runs.
+*             		  These changes fix CR#937243.
+* 3.3	pkp  05/12/16 Modified XScuGic_InterruptMaptoCpu to write proper value
+*					  to interrupt target register to fix CR#951848
+*
+* 3.4   asa  04/07/16 Created a new static function DoDistributorInit to simplify
+*                     the flow and avoid code duplication. Changes are made for
+*                     USE_AMP use case for R5. In a scenario (in R5 split mode) when
+*                     one R5 is operating with A53 in open amp config and other
+*                     R5 running baremetal app, the existing code
+*                     had the potential to stop the whole AMP solution to work (if
+*                     for some reason the R5 running the baremetal app tasked to
+*                     initialize the Distributor hangs or crashes before initializing).
+*                     Changes are made so that the R5 under AMP first checks if
+*                     the distributor is enabled or not and if not, it does the
+*                     standard Distributor initialization.
+*                     This fixes the CR#952962.
+* 3.4   mus  09/08/16 Added assert to avoid invalid access of GIC from CPUID 1
+*                     for single core zynq-7000s
+* 3.5   mus  10/05/16 Modified DistributorInit function to avoid re-initialization of
+*                     distributor,If it is already initialized by other CPU.
+* 3.5	pkp	 10/17/16 Modified XScuGic_InterruptMaptoCpu to correct the CPU Id value
+*					  and properly mask interrupt target processor value to modify
+*					  interrupt target processor register for a given interrupt ID
+*					  and cpu ID
 *
 *
 * </pre>
@@ -94,7 +117,6 @@
 #include "xil_types.h"
 #include "xil_assert.h"
 #include "xscugic.h"
-#include "xparameters.h"
 
 /************************** Constant Definitions *****************************/
 
@@ -113,7 +135,7 @@ static void StubHandler(void *CallBackRef);
 /*****************************************************************************/
 /**
 *
-* DistributorInit initializes the distributor of the GIC. The
+* DoDistributorInit initializes the distributor of the GIC. The
 * initialization entails:
 *
 * - Write the trigger mode, priority and target CPU
@@ -128,35 +150,11 @@ static void StubHandler(void *CallBackRef);
 * @note		None.
 *
 ******************************************************************************/
-static void DistributorInit(XScuGic *InstancePtr, u32 CpuID)
+static void DoDistributorInit(XScuGic *InstancePtr, u32 CpuID)
 {
 	u32 Int_Id;
 	u32 LocalCpuID = CpuID;
 
-#if USE_AMP==1
-	#warning "Building GIC for AMP"
-#ifdef ARMR5
-    u32 RegValue;
-
-	/*
-	 * The overall distributor should not be initialized in AMP case where
-	 * another CPU is taking care of it.
-	 */
-	LocalCpuID |= LocalCpuID << 8U;
-	LocalCpuID |= LocalCpuID << 16U;
-	for (Int_Id = 32U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+4U) {
-		RegValue = XScuGic_DistReadReg(InstancePtr,
-						XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
-		RegValue |= LocalCpuID;
-		XScuGic_DistWriteReg(InstancePtr,
-				     XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
-				     RegValue);
-	}
-#endif
-	return;
-#endif
-
-	Xil_AssertVoid(InstancePtr != NULL);
 	XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET, 0U);
 
 	/*
@@ -207,8 +205,8 @@ static void DistributorInit(XScuGic *InstancePtr, u32 CpuID)
 		LocalCpuID |= LocalCpuID << 16U;
 
 		XScuGic_DistWriteReg(InstancePtr,
-				     XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
-				     LocalCpuID);
+					 XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
+					 LocalCpuID);
 	}
 
 	for (Int_Id = 0U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+32U) {
@@ -223,8 +221,59 @@ static void DistributorInit(XScuGic *InstancePtr, u32 CpuID)
 	}
 
 	XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET,
-						XSCUGIC_EN_INT_MASK);
+					XSCUGIC_EN_INT_MASK);
+}
+
+/*****************************************************************************/
+/**
+*
+* DistributorInit initializes the distributor of the GIC. It calls
+* DoDistributorInit to finish the initialization.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	CpuID is the Cpu ID to be initialized.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void DistributorInit(XScuGic *InstancePtr, u32 CpuID)
+{
+	u32 Int_Id;
+	u32 LocalCpuID = CpuID;
+	u32 RegValue;
 
+#if USE_AMP==1 && (defined (ARMA9) || defined(__aarch64__))
+#warning "Building GIC for AMP"
+	/*
+	 * GIC initialization is taken care by master CPU in
+	 * openamp configuration, so do nothing and return.
+	 */
+	return;
+#endif
+
+	RegValue = XScuGic_DistReadReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET);
+	if (!(RegValue & XSCUGIC_EN_INT_MASK)) {
+		Xil_AssertVoid(InstancePtr != NULL);
+		DoDistributorInit(InstancePtr, CpuID);
+		return;
+	}
+
+	/*
+	 * The overall distributor should not be initialized in AMP case where
+	 * another CPU is taking care of it.
+	 */
+	LocalCpuID |= LocalCpuID << 8U;
+	LocalCpuID |= LocalCpuID << 16U;
+	for (Int_Id = 32U; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id=Int_Id+4U) {
+		RegValue = XScuGic_DistReadReg(InstancePtr,
+						XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
+		RegValue |= LocalCpuID;
+		XScuGic_DistWriteReg(InstancePtr,
+				     XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
+				     RegValue);
+	}
 }
 
 /*****************************************************************************/
@@ -309,10 +358,21 @@ s32  XScuGic_CfgInitialize(XScuGic *InstancePtr,
 
 	Xil_AssertNonvoid(InstancePtr != NULL);
 	Xil_AssertNonvoid(ConfigPtr != NULL);
+	/*
+     * Detect Zynq-7000 base silicon configuration,Dual or Single CPU.
+     * If it is single CPU cnfiguration then invoke assert for CPU ID=1
+	 */
+#ifdef ARMA9
+	if ( XPAR_CPU_ID == 0x01 )
+	{
+		Xil_AssertNonvoid((Xil_In32(XPS_EFUSE_BASEADDR + EFUSE_STATUS_OFFSET)
+		 & EFUSE_STATUS_CPU_MASK ) == 0);
+	}
+#endif
 
 	if(InstancePtr->IsReady != XIL_COMPONENT_IS_READY) {
 
-		InstancePtr->IsReady = 0;
+		InstancePtr->IsReady = 0U;
 		InstancePtr->Config = ConfigPtr;
 
 
@@ -757,10 +817,11 @@ void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id)
 	RegValue = XScuGic_DistReadReg(InstancePtr,
 			XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
 
-	Offset =  (Int_Id & 0x3);
+	Offset = (Int_Id & 0x3U);
+	Cpu_Id = (0x1U << Cpu_Id);
 
-	RegValue = (RegValue | (~(0xFF << (Offset*8))) );
-	RegValue |= ((Cpu_Id) << (Offset*8));
+	RegValue = (RegValue & (~(0xFFU << (Offset*8U))) );
+	RegValue |= ((Cpu_Id) << (Offset*8U));
 
 	XScuGic_DistWriteReg(InstancePtr,
 						 XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic.h
index d8efce92e..1f02a73ff 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic.h
@@ -145,6 +145,19 @@
 *             built over the scugic driver runs.
 *             These changes fix CR#937243.
 *
+* 3.4   asa  04/07/16 Created a new static function DoDistributorInit to simplify
+*            the flow and avoid code duplication. Changes are made for
+*            USE_AMP use case for R5. In a scenario (in R5 split mode) when
+*            one R5 is operating with A53 in open amp config and other
+*            R5 running baremetal app, the existing code
+*            had the potential to stop the whole AMP solution to work (if
+*            for some reason the R5 running the baremetal app tasked to
+*            initialize the Distributor hangs or crashes before initializing).
+*            Changes are made so that the R5 under AMP first checks if
+*            the distributor is enabled or not and if not, it does the
+*            standard Distributor initialization.
+*            This fixes the CR#952962.
+*
 * </pre>
 *
 ******************************************************************************/
@@ -166,7 +179,12 @@ extern "C" {
 
 /************************** Constant Definitions *****************************/
 
+#define EFUSE_STATUS_OFFSET   0x10
+#define EFUSE_STATUS_CPU_MASK 0x80
 
+#if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
+#define ARMA9
+#endif
 /**************************** Type Definitions *******************************/
 
 /* The following data type defines each entry in an interrupt vector table.
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_g.c
index 2457f6b23..4bb186e5a 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_g.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_hw.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_hw.c
index 626779720..626779720 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_hw.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_hw.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_hw.h
index 5eaa633e3..5eaa633e3 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_hw.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_hw.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_intr.c
index d05a51c5e..d05a51c5e 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_intr.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_intr.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_selftest.c
index 47620d644..47620d644 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_selftest.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_selftest.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_sinit.c
index d30390ab8..d30390ab8 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_sinit.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_sinit.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/Makefile
index f57081af6..f57081af6 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/Makefile
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/Makefile
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps.c
index 6425a791b..ac3f9469e 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2013 - 2016 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -64,28 +64,24 @@
 *       sk     12/10/15 Added support for MMC cards.
 *       sk     02/16/16 Corrected the Tuning logic.
 *       sk     03/01/16 Removed Bus Width check for eMMC. CR# 938311.
+* 2.8   sk     05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024
+* 3.0   sk     06/09/16 Added support for mkfs to calculate sector count.
+*       sk     07/16/16 Added support for UHS modes.
+*       sk     07/07/16 Used usleep API for both arm and microblaze.
+*       sk     07/16/16 Added Tap delays accordingly to different SD/eMMC
+*                       operating modes.
+* 3.1   mi     09/07/16 Removed compilation warnings with extra compiler flags.
+*       sk     10/13/16 Reduced the delay during power cycle to 1ms as per spec
+*       sk     10/19/16 Used emmc_hwreset pin to reset eMMC.
+*       sk     11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
 * </pre>
 *
 ******************************************************************************/
 
 /***************************** Include Files *********************************/
 #include "xsdps.h"
-/*
- * The header sleep.h and API usleep() can only be used with an arm design.
- * MB_Sleep() is used for microblaze design.
- */
-#if defined (__arm__) || defined (__aarch64__)
-
 #include "sleep.h"
 
-#endif
-
-#ifdef __MICROBLAZE__
-
-#include "microblaze_sleep.h"
-
-#endif
-
 /************************** Constant Definitions *****************************/
 #define XSDPS_CMD8_VOL_PATTERN	0x1AAU
 #define XSDPS_RESPOCR_READY	0x80000000U
@@ -96,8 +92,10 @@
 #define HIGH_SPEED_SUPPORT	0x2U
 #define WIDTH_4_BIT_SUPPORT	0x4U
 #define SD_CLK_25_MHZ		25000000U
+#define SD_CLK_19_MHZ		19000000U
 #define SD_CLK_26_MHZ		26000000U
 #define EXT_CSD_DEVICE_TYPE_BYTE	196U
+#define EXT_CSD_SEC_COUNT	212U
 #define EXT_CSD_DEVICE_TYPE_HIGH_SPEED			0x2U
 #define EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED	0x4U
 #define EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED	0x8U
@@ -118,7 +116,9 @@ s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt);
 void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff);
 extern s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode);
 static s32 XSdPs_IdentifyCard(XSdPs *InstancePtr);
+#ifndef UHS_BROKEN
 static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr);
+#endif
 
 /*****************************************************************************/
 /**
@@ -163,28 +163,31 @@ s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
 	Xil_AssertNonvoid(ConfigPtr != NULL);
 
 	/* Set some default values. */
+	InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
 	InstancePtr->Config.BaseAddress = EffectiveAddr;
 	InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
 	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
 	InstancePtr->Config.CardDetect =  ConfigPtr->CardDetect;
 	InstancePtr->Config.WriteProtect =  ConfigPtr->WriteProtect;
-
-	/* Disable bus power */
-	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
-			XSDPS_POWER_CTRL_OFFSET, 0U);
+	InstancePtr->Config.BusWidth = ConfigPtr->BusWidth;
+	InstancePtr->Config.BankNumber = ConfigPtr->BankNumber;
+	InstancePtr->Config.HasEMIO = ConfigPtr->HasEMIO;
+	InstancePtr->SectorCount = 0;
+	InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE;
+	InstancePtr->Config_TapDelay = NULL;
+
+	/* Disable bus power and issue emmc hw reset */
+	if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK) ==
+			XSDPS_HC_SPEC_V3)
+		XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+				XSDPS_POWER_CTRL_OFFSET, XSDPS_PC_EMMC_HW_RST_MASK);
+	else
+		XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+				XSDPS_POWER_CTRL_OFFSET, 0x0);
 
 	/* Delay to poweroff card */
-#if defined (__arm__) || defined (__aarch64__)
-
-    (void)sleep(1U);
-
-#endif
-
-#ifdef __MICROBLAZE__
-
-    MB_Sleep(1000U);
-
-#endif
+    (void)usleep(1000U);
 
 	/* "Software reset for all" is initiated */
 	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET,
@@ -210,9 +213,21 @@ s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
 						XSDPS_CAPS_OFFSET);
 
 	/* Select voltage and enable bus power. */
-	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
-			XSDPS_POWER_CTRL_OFFSET,
-			XSDPS_PC_BUS_VSEL_3V3_MASK | XSDPS_PC_BUS_PWR_MASK);
+	if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3)
+		XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+				XSDPS_POWER_CTRL_OFFSET,
+				(XSDPS_PC_BUS_VSEL_3V3_MASK | XSDPS_PC_BUS_PWR_MASK) &
+				~XSDPS_PC_EMMC_HW_RST_MASK);
+	else
+		XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+				XSDPS_POWER_CTRL_OFFSET,
+				XSDPS_PC_BUS_VSEL_3V3_MASK | XSDPS_PC_BUS_PWR_MASK);
+
+	/* Delay before issuing the command after emmc reset */
+	if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3)
+		if ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK) ==
+				XSDPS_CAPS_EMB_SLOT)
+			usleep(200);
 
 	/* Change the clock frequency to 400 KHz */
 	Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_400_KHZ);
@@ -308,6 +323,7 @@ s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr)
 	u32 CSD[4];
 	u32 Arg;
 	u8 ReadReg;
+	u32 BlkLen, DeviceSize, Mult;
 
 	Xil_AssertNonvoid(InstancePtr != NULL);
 	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
@@ -470,6 +486,19 @@ s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr)
 	CSD[3] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
 			XSDPS_RESP3_OFFSET);
 
+	if (((CSD[3] & CSD_STRUCT_MASK) >> 22U) == 0U) {
+		BlkLen = 1 << ((CSD[2] & READ_BLK_LEN_MASK) >> 8U);
+		Mult = 1 << (((CSD[1] & C_SIZE_MULT_MASK) >> 7U) + 2U);
+		DeviceSize = (CSD[1] & C_SIZE_LOWER_MASK) >> 22U;
+		DeviceSize |= (CSD[2] & C_SIZE_UPPER_MASK) << 10U;
+		DeviceSize = (DeviceSize + 1U) * Mult;
+		DeviceSize =  DeviceSize * BlkLen;
+		InstancePtr->SectorCount = (DeviceSize/XSDPS_BLK_SIZE_512_MASK);
+	} else if (((CSD[3] & CSD_STRUCT_MASK) >> 22U) == 1U) {
+		InstancePtr->SectorCount = (((CSD[1] & CSD_V2_C_SIZE_MASK) >> 8U) +
+										1U) * 1024U;
+	}
+
 	Status = XST_SUCCESS;
 
 RETURN_PATH:
@@ -495,12 +524,8 @@ RETURN_PATH:
 *
 *
 ******************************************************************************/
-s32 XSdPs_CardInitialize(XSdPs *InstancePtr) {
-	u8 Tmp;
-	u32 Cnt;
-	u32 PresentStateReg;
-	u32 CtrlReg;
-	u32 CSD[4];
+s32 XSdPs_CardInitialize(XSdPs *InstancePtr)
+{
 #ifdef __ICCARM__
 #pragma data_alignment = 32
 static u8 ExtCsd[512];
@@ -511,6 +536,7 @@ static u8 ExtCsd[512] __attribute__ ((aligned(32)));
 	u8 SCR[8] = { 0U };
 	u8 ReadBuff[64] = { 0U };
 	s32 Status;
+	u32 Arg;
 
 	Xil_AssertNonvoid(InstancePtr != NULL);
 	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
@@ -547,7 +573,15 @@ static u8 ExtCsd[512] __attribute__ ((aligned(32)));
 		}
 
 		/* Change clock to default clock 25MHz */
-		InstancePtr->BusSpeed = SD_CLK_25_MHZ;
+		/*
+		 * SD default speed mode timing should be closed at 19 MHz.
+		 * The reason for this is SD requires a voltage level shifter.
+		 * This limitation applies to ZynqMPSoC.
+		 */
+		if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3)
+			InstancePtr->BusSpeed = SD_CLK_19_MHZ;
+		else
+			InstancePtr->BusSpeed = SD_CLK_25_MHZ;
 		Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
 		if (Status != XST_SUCCESS) {
 			Status = XST_FAILURE;
@@ -601,33 +635,39 @@ static u8 ExtCsd[512] __attribute__ ((aligned(32)));
 			}
 		}
 
+		/* Get speed supported by device */
+		Status = XSdPs_Get_BusSpeed(InstancePtr, ReadBuff);
+		if (Status != XST_SUCCESS) {
+			goto RETURN_PATH;
+		}
+
+#if defined (ARMR5) || defined (__aarch64__)
 		if ((InstancePtr->Switch1v8 != 0U) &&
 				(InstancePtr->BusWidth == XSDPS_4_BIT_WIDTH)) {
+
+			/* Identify the UHS mode supported by card */
+			XSdPs_Identify_UhsMode(InstancePtr, ReadBuff);
+
 			/* Set UHS-I SDR104 mode */
-			Status = XSdPs_Uhs_ModeInit(InstancePtr,
-					XSDPS_UHS_SPEED_MODE_SDR104);
+			Status = XSdPs_Uhs_ModeInit(InstancePtr, InstancePtr->Mode);
 			if (Status != XST_SUCCESS) {
-				Status = XST_FAILURE;
 				goto RETURN_PATH;
 			}
 
 		} else {
-
+#endif
 			/*
 			 * card supports CMD6 when SD_SPEC field in SCR register
 			 * indicates that the Physical Layer Specification Version
 			 * is 1.10 or later. So for SD v1.0 cmd6 is not supported.
 			 */
 			if (SCR[0] != 0U) {
-				/* Get speed supported by device */
-				Status = XSdPs_Get_BusSpeed(InstancePtr, ReadBuff);
-				if (Status != XST_SUCCESS) {
-					Status = XST_FAILURE;
-					goto RETURN_PATH;
-				}
-
 				/* Check for high speed support */
 				if ((ReadBuff[13] & HIGH_SPEED_SUPPORT) != 0U) {
+					InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE;
+#if defined (ARMR5) || defined (__aarch64__)
+					InstancePtr->Config_TapDelay = XSdPs_hsd_sdr25_tapdelay;
+#endif
 					Status = XSdPs_Change_BusSpeed(InstancePtr);
 					if (Status != XST_SUCCESS) {
 						Status = XST_FAILURE;
@@ -635,7 +675,9 @@ static u8 ExtCsd[512] __attribute__ ((aligned(32)));
 					}
 				}
 			}
+#if defined (ARMR5) || defined (__aarch64__)
 		}
+#endif
 
 	} else if (((InstancePtr->CardType == XSDPS_CARD_MMC) &&
 				(InstancePtr->Card_Version > CSD_SPEC_VER_3)) &&
@@ -653,8 +695,11 @@ static u8 ExtCsd[512] __attribute__ ((aligned(32)));
 			goto RETURN_PATH;
 		}
 
+		InstancePtr->SectorCount = *(u32 *)&ExtCsd[EXT_CSD_SEC_COUNT];
+
 		if ((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
 				EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) {
+			InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE;
 			Status = XSdPs_Change_BusSpeed(InstancePtr);
 			if (Status != XST_SUCCESS) {
 				Status = XST_FAILURE;
@@ -687,9 +732,15 @@ static u8 ExtCsd[512] __attribute__ ((aligned(32)));
 			goto RETURN_PATH;
 		}
 
+		InstancePtr->SectorCount = *(u32 *)&ExtCsd[EXT_CSD_SEC_COUNT];
+
 		if ((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
 				(EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 |
 				EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200)) != 0U) {
+			InstancePtr->Mode = XSDPS_HS200_MODE;
+#if defined (ARMR5) || defined (__aarch64__)
+			InstancePtr->Config_TapDelay = XSdPs_sdr104_hs200_tapdelay;
+#endif
 			Status = XSdPs_Change_BusSpeed(InstancePtr);
 			if (Status != XST_SUCCESS) {
 				Status = XST_FAILURE;
@@ -707,6 +758,16 @@ static u8 ExtCsd[512] __attribute__ ((aligned(32)));
 				goto RETURN_PATH;
 			}
 		}
+
+		/* Enable Rst_n_Fun bit if it is disabled */
+		if(ExtCsd[EXT_CSD_RST_N_FUN_BYTE] == EXT_CSD_RST_N_FUN_TEMP_DIS) {
+			Arg = XSDPS_MMC_RST_FUN_EN_ARG;
+			Status = XSdPs_Set_Mmc_ExtCsd(InstancePtr, Arg);
+			if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		}
 	}
 
 	Status = XSdPs_SetBlkSize(InstancePtr, XSDPS_BLK_SIZE_512_MASK);
@@ -731,26 +792,14 @@ RETURN_PATH:
 static s32 XSdPs_IdentifyCard(XSdPs *InstancePtr)
 {
 	s32 Status;
-	u32 OperCondReg;
 	u8 ReadReg;
 
 	Xil_AssertNonvoid(InstancePtr != NULL);
 	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
 	/* 74 CLK delay after card is powered up, before the first command. */
-#if defined (__arm__) || defined (__aarch64__)
-
 	usleep(XSDPS_INIT_DELAY);
 
-#endif
-
-#ifdef __MICROBLAZE__
-
-	/* 2 msec delay */
-	MB_Sleep(2);
-
-#endif
-
 	/* CMD0 no response expected */
 	Status = XSdPs_CmdTransfer(InstancePtr, CMD0, 0U, 0U);
 	if (Status != XST_SUCCESS) {
@@ -790,6 +839,7 @@ RETURN_PATH:
 	return Status;
 }
 
+#ifndef UHS_BROKEN
 /*****************************************************************************/
 /**
 *
@@ -828,18 +878,8 @@ static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr)
 			CtrlReg);
 
 	/* Wait minimum 5mSec */
-#if defined (__arm__) || defined (__aarch64__)
-
 	(void)usleep(5000U);
 
-#endif
-
-#ifdef __MICROBLAZE__
-
-	MB_Sleep(5U);
-
-#endif
-
 	/* Enabling 1.8V in controller */
 	CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
 			XSDPS_HOST_CTRL2_OFFSET);
@@ -866,6 +906,7 @@ static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr)
 RETURN_PATH:
 	return Status;
 }
+#endif
 
 /*****************************************************************************/
 /**
@@ -1398,6 +1439,7 @@ s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr)
 	s32 Status;
 	u32 RespOCR;
 	u32 CSD[4];
+	u32 BlkLen, DeviceSize, Mult;
 
 	Xil_AssertNonvoid(InstancePtr != NULL);
 	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
@@ -1498,6 +1540,16 @@ s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr)
 
 	InstancePtr->Card_Version =  (CSD[3] & CSD_SPEC_VER_MASK) >>18U;
 
+	/* Calculating the memory capacity */
+	BlkLen = 1 << ((CSD[2] & READ_BLK_LEN_MASK) >> 8U);
+	Mult = 1 << (((CSD[1] & C_SIZE_MULT_MASK) >> 7U) + 2U);
+	DeviceSize = (CSD[1] & C_SIZE_LOWER_MASK) >> 22U;
+	DeviceSize |= (CSD[2] & C_SIZE_UPPER_MASK) << 10U;
+	DeviceSize = (DeviceSize + 1U) * Mult;
+	DeviceSize =  DeviceSize * BlkLen;
+
+	InstancePtr->SectorCount = (DeviceSize/XSDPS_BLK_SIZE_512_MASK);
+
 	Status = XST_SUCCESS;
 
 RETURN_PATH:
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps.h
index 409653891..46fe545d9 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps.h
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2013 - 2016 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -125,6 +125,20 @@
 *                       of SDR50, SDR104 and HS200.
 *       sk     02/16/16 Corrected the Tuning logic.
 *       sk     03/01/16 Removed Bus Width check for eMMC. CR# 938311.
+* 2.8   sk     04/20/16 Added new workaround for auto tuning.
+*              05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024
+* 3.0   sk     06/09/16 Added support for mkfs to calculate sector count.
+*       sk     07/16/16 Added support for UHS modes.
+*       sk     07/07/16 Used usleep API for both arm and microblaze.
+*       sk     07/16/16 Added Tap delays accordingly to different SD/eMMC
+*                       operating modes.
+*       sk     08/13/16 Removed sleep.h from xsdps.h as a temporary fix for
+*                       CR#956899.
+* 3.1   mi     09/07/16 Removed compilation warnings with extra compiler flags.
+*       sk     10/13/16 Reduced the delay during power cycle to 1ms as per spec
+*       sk     10/19/16 Used emmc_hwreset pin to reset eMMC.
+*       sk     11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+*       sk     11/16/16 Issue DLL reset at 31 iteration to load new zero value.
 *
 * </pre>
 *
@@ -150,6 +164,9 @@ extern "C" {
 #define MAX_TUNING_COUNT	40U		/**< Maximum Tuning count */
 
 /**************************** Type Definitions *******************************/
+
+typedef void (*XSdPs_ConfigTap) (u32 Bank, u32 DeviceId, u32 CardType);
+
 /**
  * This typedef contains configuration information for the device.
  */
@@ -159,6 +176,9 @@ typedef struct {
 	u32 InputClockHz;		/**< Input clock frequency */
 	u32 CardDetect;			/**< Card Detect */
 	u32 WriteProtect;			/**< Write Protect */
+	u32 BusWidth;			/**< Bus Width */
+	u32 BankNumber;			/**< MIO Bank selection for SD */
+	u32 HasEMIO;			/**< If SD is connected to EMIO */
 } XSdPs_Config;
 
 /* ADMA2 descriptor table */
@@ -188,7 +208,10 @@ typedef struct {
 	u32 CardID[4];		/**< Card ID Register */
 	u32 RelCardAddr;	/**< Relative Card Address */
 	u32 CardSpecData[4];	/**< Card Specific Data Register */
+	u32 SectorCount;		/**< Sector Count */
 	u32 SdCardConfig;	/**< Sd Card Configuration Register */
+	u32 Mode;			/**< Bus Speed Mode */
+	XSdPs_ConfigTap Config_TapDelay;	/**< Configuring the tap delays */
 	/**< ADMA Descriptors */
 #ifdef __ICCARM__
 #pragma data_alignment = 32
@@ -219,6 +242,12 @@ s32 XSdPs_Pullup(XSdPs *InstancePtr);
 s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr);
 s32 XSdPs_CardInitialize(XSdPs *InstancePtr);
 s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff);
+s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg);
+#if defined (ARMR5) || defined (__aarch64__)
+void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff);
+void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+void XSdPs_sdr104_hs200_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+#endif
 
 #ifdef __cplusplus
 }
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_g.c
index b5d2e4be8..72981b551 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps_g.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
@@ -51,7 +51,10 @@ XSdPs_Config XSdPs_ConfigTable[] =
 		XPAR_PSU_SD_1_BASEADDR,
 		XPAR_PSU_SD_1_SDIO_CLK_FREQ_HZ,
 		XPAR_PSU_SD_1_HAS_CD,
-		XPAR_PSU_SD_1_HAS_WP
+		XPAR_PSU_SD_1_HAS_WP,
+		XPAR_PSU_SD_1_BUS_WIDTH,
+		XPAR_PSU_SD_1_MIO_BANK,
+		XPAR_PSU_SD_1_HAS_EMIO
 	}
 };
 
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_hw.h
index c797e8216..2c5d712d2 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps_hw.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_hw.h
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2013 - 2016 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -50,6 +50,12 @@
 *       kvn    07/15/15 Modified the code according to MISRAC-2012.
 * 2.7   sk     12/10/15 Added support for MMC cards.
 *       sk     03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
+* 2.8   sk     04/20/16 Added new workaround for auto tuning.
+* 3.0   sk     06/09/16 Added support for mkfs to calculate sector count.
+*       sk     07/16/16 Added support for UHS modes.
+*       sk     07/16/16 Added Tap delays accordingly to different SD/eMMC
+*                       operating modes.
+* 3.1   sk     11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
 * </pre>
 *
 ******************************************************************************/
@@ -796,6 +802,12 @@ extern "C" {
 #define XSDPS_CUR_LIM_800		3U
 
 #define CSD_SPEC_VER_MASK		0x3C0000U
+#define READ_BLK_LEN_MASK		0x00000F00U
+#define C_SIZE_MULT_MASK		0x00000380U
+#define C_SIZE_LOWER_MASK		0xFFC00000U
+#define C_SIZE_UPPER_MASK		0x00000003U
+#define CSD_STRUCT_MASK			0x00C00000U
+#define CSD_V2_C_SIZE_MASK		0x3FFFFF00U
 
 /* EXT_CSD field definitions */
 #define XSDPS_EXT_CSD_SIZE		512U
@@ -842,6 +854,10 @@ extern "C" {
 #define EXT_CSD_HS_TIMING_HIGH		1U	/* Card is in high speed mode */
 #define EXT_CSD_HS_TIMING_HS200		2U	/* Card is in HS200 mode */
 
+#define EXT_CSD_RST_N_FUN_BYTE		162U
+#define EXT_CSD_RST_N_FUN_TEMP_DIS	0U	/* RST_n signal is temporarily disabled */
+#define EXT_CSD_RST_N_FUN_PERM_EN	1U	/* RST_n signal is permanently enabled */
+#define EXT_CSD_RST_N_FUN_PERM_DIS	2U	/* RST_n signal is permanently disabled */
 
 #define XSDPS_EXT_CSD_CMD_SET		0U
 #define XSDPS_EXT_CSD_SET_BITS		1U
@@ -880,6 +896,10 @@ extern "C" {
 					 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
 					 | ((u32)EXT_CSD_BUS_WIDTH_DDR_8_BIT << 8))
 
+#define XSDPS_MMC_RST_FUN_EN_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_RST_N_FUN_BYTE << 16) \
+					 | ((u32)EXT_CSD_RST_N_FUN_PERM_EN << 8))
+
 #define XSDPS_MMC_DELAY_FOR_SWITCH	1000U
 
 /* @} */
@@ -930,6 +950,9 @@ extern "C" {
 #define XSDPS_UHS_SPEED_MODE_SDR50	0x2U
 #define XSDPS_UHS_SPEED_MODE_SDR104	0x3U
 #define XSDPS_UHS_SPEED_MODE_DDR50	0x4U
+#define XSDPS_HIGH_SPEED_MODE		0x5U
+#define XSDPS_DEFAULT_SPEED_MODE	0x6U
+#define XSDPS_HS200_MODE			0x7U
 #define XSDPS_SWITCH_CMD_BLKCNT		1U
 #define XSDPS_SWITCH_CMD_BLKSIZE	64U
 #define XSDPS_SWITCH_CMD_HS_GET		0x00FFFFF0U
@@ -987,15 +1010,43 @@ extern "C" {
 #define XSDPS_SLOT_REM			0U
 #define XSDPS_SLOT_EMB			1U
 
-#if defined (__arm__) || defined (__aarch64__)
-#define SD_DLL_CTRL 			0x00000358U
-#define SD_ITAPDLY				0x00000314U
-#define SD_OTAPDLYSEL			0x00000318U
-#define SD0_DLL_RST				0x00000004U
-#define SD0_ITAPCHGWIN			0x00000200U
-#define SD0_ITAPDLYENA			0x00000100U
-#define SD0_OTAPDLYENA			0x00000040U
-#define SD0_OTAPDLYSEL_HS200	0x00000003U
+#if defined (ARMR5) || defined (__aarch64__)
+#define SD_DLL_CTRL 				0x00000358U
+#define SD_ITAPDLY					0x00000314U
+#define SD_OTAPDLY					0x00000318U
+#define SD0_DLL_RST					0x00000004U
+#define SD1_DLL_RST					0x00040000U
+#define SD0_ITAPCHGWIN				0x00000200U
+#define SD0_ITAPDLYENA				0x00000100U
+#define SD0_OTAPDLYENA				0x00000040U
+#define SD1_ITAPCHGWIN				0x02000000U
+#define SD1_ITAPDLYENA				0x01000000U
+#define SD1_OTAPDLYENA				0x00400000U
+
+#define SD0_OTAPDLYSEL_HS200_B0		0x00000003U
+#define SD0_OTAPDLYSEL_HS200_B2		0x00000002U
+#define SD0_ITAPDLYSEL_SD50			0x00000014U
+#define SD0_OTAPDLYSEL_SD50			0x00000003U
+#define SD0_ITAPDLYSEL_SD_DDR50		0x0000003DU
+#define SD0_ITAPDLYSEL_EMMC_DDR50	0x00000012U
+#define SD0_OTAPDLYSEL_SD_DDR50		0x00000004U
+#define SD0_OTAPDLYSEL_EMMC_DDR50	0x00000006U
+#define SD0_ITAPDLYSEL_HSD			0x00000015U
+#define SD0_OTAPDLYSEL_SD_HSD		0x00000005U
+#define SD0_OTAPDLYSEL_EMMC_HSD		0x00000006U
+
+#define SD1_OTAPDLYSEL_HS200_B0		0x00030000U
+#define SD1_OTAPDLYSEL_HS200_B2		0x00020000U
+#define SD1_ITAPDLYSEL_SD50			0x00140000U
+#define SD1_OTAPDLYSEL_SD50			0x00030000U
+#define SD1_ITAPDLYSEL_SD_DDR50		0x003D0000U
+#define SD1_ITAPDLYSEL_EMMC_DDR50	0x00120000U
+#define SD1_OTAPDLYSEL_SD_DDR50		0x00040000U
+#define SD1_OTAPDLYSEL_EMMC_DDR50	0x00060000U
+#define SD1_ITAPDLYSEL_HSD			0x00150000U
+#define SD1_OTAPDLYSEL_SD_HSD		0x00050000U
+#define SD1_OTAPDLYSEL_EMMC_HSD		0x00060000U
+
 #endif
 
 /**************************** Type Definitions *******************************/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps_options.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_options.c
index 8151eef1b..7dbc772f3 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps_options.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_options.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2013 - 2016 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -55,6 +55,14 @@
 *                       of SDR50, SDR104 and HS200.
 *       sk     02/16/16 Corrected the Tuning logic.
 *       sk     03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
+* 2.8   sk     04/20/16 Added new workaround for auto tuning.
+* 3.0   sk     07/07/16 Used usleep API for both arm and microblaze.
+*       sk     07/16/16 Added support for UHS modes.
+*       sk     07/16/16 Added Tap delays accordingly to different SD/eMMC
+*                       operating modes.
+* 3.1   mi     09/07/16 Removed compilation warnings with extra compiler flags.
+*       sk     11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+*       sk     11/16/16 Issue DLL reset at 31 iteration to load new zero value.
 *
 * </pre>
 *
@@ -62,24 +70,14 @@
 
 /***************************** Include Files *********************************/
 #include "xsdps.h"
-/*
- * The header sleep.h and API usleep() can only be used with an arm design.
- * MB_Sleep() is used for microblaze design.
- */
-#if defined (__arm__) || defined (__aarch64__)
-
 #include "sleep.h"
 
-#endif
-
-#ifdef __MICROBLAZE__
-
-#include "microblaze_sleep.h"
-
-#endif
-
 /************************** Constant Definitions *****************************/
-
+#define UHS_SDR12_SUPPORT	0x1U
+#define UHS_SDR25_SUPPORT	0x2U
+#define UHS_SDR50_SUPPORT	0x4U
+#define UHS_SDR104_SUPPORT	0x8U
+#define UHS_DDR50_SUPPORT	0x10U
 /**************************** Type Definitions *******************************/
 
 /***************** Macros (Inline Functions) Definitions *********************/
@@ -87,11 +85,13 @@
 /************************** Function Prototypes ******************************/
 s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt);
 void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff);
-s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode);
 static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr);
+#if defined (ARMR5) || defined (__aarch64__)
 s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode);
-#if defined (__arm__) || defined (__aarch64__)
+static void XSdPs_sdr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+static void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
 void XSdPs_SetTapDelay(XSdPs *InstancePtr);
+static void XSdPs_DllReset(XSdPs *InstancePtr);
 #endif
 
 /*****************************************************************************/
@@ -320,19 +320,8 @@ s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr)
 				XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
 	}
 
-#if defined (__arm__) || defined (__aarch64__)
-
 	usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
 
-#endif
-
-#ifdef __MICROBLAZE__
-
-	/* 2 msec delay */
-	MB_Sleep(2);
-
-#endif
-
 	StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
 					XSDPS_HOST_CTRL1_OFFSET);
 
@@ -463,7 +452,6 @@ s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr)
 	s32 Status;
 	u32 StatusReg;
 	u32 Arg;
-	u32 ClockReg;
 	u16 BlkCnt;
 	u16 BlkSize;
 	u8 ReadBuff[64];
@@ -610,25 +598,10 @@ s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr)
 			Status = XST_FAILURE;
 			goto RETURN_PATH;
 		}
-#if defined (__arm__) || defined (__aarch64__)
-		/* Program the Tap delays */
-		XSdPs_SetTapDelay(InstancePtr);
-#endif
 	}
 
-#if defined (__arm__) || defined (__aarch64__)
-
 	usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
 
-#endif
-
-#ifdef __MICROBLAZE__
-
-	/* 2 msec delay */
-	MB_Sleep(2);
-
-#endif
-
 	StatusReg = (s32)XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
 					XSDPS_HOST_CTRL1_OFFSET);
 	StatusReg |= XSDPS_HC_SPEED_MASK;
@@ -667,7 +640,6 @@ s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq)
 	u16 DivCnt;
 	u16 Divisor = 0U;
 	u16 ExtDivisor;
-	u16 ClkLoopCnt;
 	s32 Status;
 	u16 ReadReg;
 
@@ -682,6 +654,12 @@ s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq)
 			XSDPS_CLK_CTRL_OFFSET, ClockReg);
 
 	if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
+#if defined (ARMR5) || defined (__aarch64__)
+	if ((InstancePtr->Mode != XSDPS_DEFAULT_SPEED_MODE) &&
+			(InstancePtr->Mode != XSDPS_UHS_SPEED_MODE_SDR12))
+		/* Program the Tap delays */
+		XSdPs_SetTapDelay(InstancePtr);
+#endif
 		/* Calculate divisor */
 		for (DivCnt = 0x1U; DivCnt <= XSDPS_CC_EXT_MAX_DIV_CNT;DivCnt++) {
 			if (((InstancePtr->Config.InputClockHz) / DivCnt) <= SelFreq) {
@@ -890,6 +868,110 @@ s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff)
 
 }
 
+/*****************************************************************************/
+/**
+*
+* API to write EXT_CSD register of eMMC.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	Arg is the argument to be sent along with the command
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg)
+{
+	s32 Status;
+	u32 StatusReg;
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Check for transfer complete
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+			/*
+			 * Write to clear error bits
+			 */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+	/* Write to clear bit */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+#if defined (ARMR5) || defined (__aarch64__)
+/*****************************************************************************/
+/**
+*
+* API to Identify the supported UHS mode. This API will assign the
+* corresponding tap delay API to the Config_TapDelay pointer based on the
+* supported bus speed.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	ReadBuff contains the response for CMD6
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff)
+{
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	if (((ReadBuff[13] & UHS_SDR104_SUPPORT) != 0U) &&
+		(InstancePtr->Config.InputClockHz >= XSDPS_MMC_HS200_MAX_CLK)) {
+		InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR104;
+		InstancePtr->Config_TapDelay = XSdPs_sdr104_hs200_tapdelay;
+	}
+	else if (((ReadBuff[13] & UHS_SDR50_SUPPORT) != 0U) &&
+		(InstancePtr->Config.InputClockHz >= XSDPS_SD_SDR50_MAX_CLK)) {
+		InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR50;
+		InstancePtr->Config_TapDelay = XSdPs_sdr50_tapdelay;
+	}
+	else if (((ReadBuff[13] & UHS_DDR50_SUPPORT) != 0U) &&
+		(InstancePtr->Config.InputClockHz >= XSDPS_SD_DDR50_MAX_CLK)) {
+		InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_DDR50;
+		InstancePtr->Config_TapDelay = XSdPs_ddr50_tapdelay;
+	}
+	else if (((ReadBuff[13] & UHS_SDR25_SUPPORT) != 0U) &&
+		(InstancePtr->Config.InputClockHz >= XSDPS_SD_SDR25_MAX_CLK)) {
+		InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR25;
+		InstancePtr->Config_TapDelay = XSdPs_hsd_sdr25_tapdelay;
+	}
+	else
+		InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR12;
+}
 
 /*****************************************************************************/
 /**
@@ -1008,7 +1090,7 @@ s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode)
 	}
 
 	if((Mode == XSDPS_UHS_SPEED_MODE_SDR104) ||
-			(Mode == XSDPS_UHS_SPEED_MODE_DDR50)) {
+			(Mode == XSDPS_UHS_SPEED_MODE_SDR50)) {
 		/* Send tuning pattern */
 		Status = XSdPs_Execute_Tuning(InstancePtr);
 		if (Status != XST_SUCCESS) {
@@ -1022,22 +1104,18 @@ s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode)
 	RETURN_PATH:
 		return Status;
 }
+#endif
 
 static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr)
 {
 	s32 Status;
-	u32 StatusReg;
-	u32 Arg;
-	u16 BlkCnt;
 	u16 BlkSize;
-	s32 LoopCnt;
 	u16 CtrlReg;
 	u8 TuningCount;
 
 	Xil_AssertNonvoid(InstancePtr != NULL);
 	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
-	BlkCnt = XSDPS_TUNING_CMD_BLKCNT;
 	BlkSize = XSDPS_TUNING_CMD_BLKSIZE;
 	if(InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH)
 	{
@@ -1056,6 +1134,18 @@ static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr)
 	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
 				XSDPS_HOST_CTRL2_OFFSET, CtrlReg);
 
+	/*
+	 * workaround which can work for 1.0/2.0 silicon for auto tuning.
+	 * This can be revisited for 3.0 silicon if necessary.
+	 */
+	/* Wait for ~60 clock cycles to reset the tap values */
+	(void)usleep(1U);
+
+#if defined (ARMR5) || defined (__aarch64__)
+	/* Issue DLL Reset to load new SDHC tuned tap values */
+	XSdPs_DllReset(InstancePtr);
+#endif
+
 	for (TuningCount = 0U; TuningCount < MAX_TUNING_COUNT; TuningCount++) {
 
 		if (InstancePtr->CardType == XSDPS_CARD_SD) {
@@ -1073,6 +1163,13 @@ static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr)
 				XSDPS_HOST_CTRL2_OFFSET) & XSDPS_HC2_EXEC_TNG_MASK) == 0U) {
 			break;
 		}
+
+		if (TuningCount == 31) {
+#if defined (ARMR5) || defined (__aarch64__)
+			/* Issue DLL Reset to load new SDHC tuned tap values */
+			XSdPs_DllReset(InstancePtr);
+#endif
+		}
 	}
 
 	if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
@@ -1081,25 +1178,13 @@ static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr)
 		goto RETURN_PATH;
 	}
 
-	/*
-	 * As per controller erratum, program the "SDCLK Frequency
-	 * Select" of clock control register with a value, say
-	 * clock/2. Wait for the Internal clock stable and program
-	 * the desired frequency.
-	 */
-	CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
-				XSDPS_HOST_CTRL2_OFFSET);
-	if ((CtrlReg & XSDPS_HC2_SAMP_CLK_SEL_MASK) != 0U) {
-		Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed/2);
-		if (Status != XST_SUCCESS) {
-			goto RETURN_PATH ;
-		}
-		Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
-		if (Status != XST_SUCCESS) {
-			goto RETURN_PATH ;
-		}
+	/* Wait for ~12 clock cycles to synchronize the new tap values */
+	(void)usleep(1U);
 
-	}
+#if defined (ARMR5) || defined (__aarch64__)
+	/* Issue DLL Reset to load new SDHC tuned tap values */
+	XSdPs_DllReset(InstancePtr);
+#endif
 
 	Status = XST_SUCCESS;
 
@@ -1107,7 +1192,226 @@ static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr)
 
 }
 
-#if defined (__arm__) || defined (__aarch64__)
+#if defined (ARMR5) || defined (__aarch64__)
+/*****************************************************************************/
+/**
+*
+* API to set Tap Delay for SDR104 and HS200 modes
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XSdPs_sdr104_hs200_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
+{
+	u32 TapDelay;
+	(void) CardType;
+
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	if (DeviceId == 0U) {
+		/* Program the OTAPDLY */
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+		TapDelay |= SD0_OTAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+		if (Bank == 2)
+			TapDelay |= SD0_OTAPDLYSEL_HS200_B2;
+		else
+			TapDelay |= SD0_OTAPDLYSEL_HS200_B0;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+	} else {
+#endif
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+		TapDelay |= SD1_OTAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+		if (Bank == 2)
+			TapDelay |= SD1_OTAPDLYSEL_HS200_B2;
+		else
+			TapDelay |= SD1_OTAPDLYSEL_HS200_B0;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	}
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set Tap Delay for SDR50 mode
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XSdPs_sdr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
+{
+	u32 TapDelay;
+	(void) Bank;
+	(void) CardType;
+
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	if (DeviceId == 0U) {
+		/* Program the OTAPDLY */
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+		TapDelay |= SD0_OTAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+		TapDelay |= SD0_OTAPDLYSEL_SD50;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+	} else {
+#endif
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+		TapDelay |= SD1_OTAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+		TapDelay |= SD1_OTAPDLYSEL_SD50;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	}
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set Tap Delay for DDR50 mode
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
+{
+	u32 TapDelay;
+	(void) Bank;
+
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	if (DeviceId == 0U) {
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
+		TapDelay |= SD0_ITAPCHGWIN;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		/* Program the ITAPDLY */
+		TapDelay |= SD0_ITAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		if (CardType== XSDPS_CARD_SD)
+			TapDelay |= SD0_ITAPDLYSEL_SD_DDR50;
+		else
+			TapDelay |= SD0_ITAPDLYSEL_EMMC_DDR50;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		TapDelay &= ~SD0_ITAPCHGWIN;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		/* Program the OTAPDLY */
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+		TapDelay |= SD0_OTAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+		if (CardType == XSDPS_CARD_SD)
+			TapDelay |= SD0_OTAPDLYSEL_SD_DDR50;
+		else
+			TapDelay |= SD0_OTAPDLYSEL_EMMC_DDR50;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+	} else {
+#endif
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
+		TapDelay |= SD1_ITAPCHGWIN;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		/* Program the ITAPDLY */
+		TapDelay |= SD1_ITAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		if (CardType == XSDPS_CARD_SD)
+			TapDelay |= SD1_ITAPDLYSEL_SD_DDR50;
+		else
+			TapDelay |= SD1_ITAPDLYSEL_EMMC_DDR50;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		TapDelay &= ~SD1_ITAPCHGWIN;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		/* Program the OTAPDLY */
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+		TapDelay |= SD1_OTAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+		if (CardType == XSDPS_CARD_SD)
+			TapDelay |= SD1_OTAPDLYSEL_SD_DDR50;
+		else
+			TapDelay |= SD1_OTAPDLYSEL_EMMC_DDR50;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	}
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set Tap Delay for HSD and SDR25 mode
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
+{
+	u32 TapDelay;
+	(void) Bank;
+
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	if (DeviceId == 0U) {
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
+		TapDelay |= SD0_ITAPCHGWIN;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		/* Program the ITAPDLY */
+		TapDelay |= SD0_ITAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		TapDelay |= SD0_ITAPDLYSEL_HSD;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		TapDelay &= ~SD0_ITAPCHGWIN;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		/* Program the OTAPDLY */
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+		TapDelay |= SD0_OTAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+		if (CardType == XSDPS_CARD_SD)
+			TapDelay |= SD0_OTAPDLYSEL_SD_HSD;
+		else
+			TapDelay |= SD0_OTAPDLYSEL_EMMC_HSD;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+	} else {
+#endif
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
+		TapDelay |= SD1_ITAPCHGWIN;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		/* Program the ITAPDLY */
+		TapDelay |= SD1_ITAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		TapDelay |= SD1_ITAPDLYSEL_HSD;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		TapDelay &= ~SD1_ITAPCHGWIN;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		/* Program the OTAPDLY */
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+		TapDelay |= SD1_OTAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+		if (CardType == XSDPS_CARD_SD)
+			TapDelay |= SD1_OTAPDLYSEL_SD_HSD;
+		else
+			TapDelay |= SD1_OTAPDLYSEL_EMMC_HSD;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	}
+#endif
+}
+
 /*****************************************************************************/
 /**
 *
@@ -1123,30 +1427,91 @@ static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr)
 ******************************************************************************/
 void XSdPs_SetTapDelay(XSdPs *InstancePtr)
 {
-	u32 DllCtrl, TapDelay;
-	if (InstancePtr->Config.DeviceId == XPAR_XSDPS_0_DEVICE_ID) {
+	u32 DllCtrl, BankNum, DeviceId, CardType;
+
+	BankNum = InstancePtr->Config.BankNumber;
+	DeviceId = InstancePtr->Config.DeviceId ;
+	CardType = InstancePtr->CardType ;
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	if (DeviceId == 0U) {
 		DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL);
 		DllCtrl |= SD0_DLL_RST;
 		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
-		if(InstancePtr->BusSpeed == XSDPS_MMC_HS200_MAX_CLK) {
-			/* Program the ITAPDLY */
-			TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
-			TapDelay |= SD0_ITAPCHGWIN;
-			XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
-			TapDelay |= SD0_ITAPDLYENA;
-			XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
-			TapDelay &= ~SD0_ITAPCHGWIN;
-			XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
-			/* Program the OTAPDLY */
-			TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLYSEL);
-			TapDelay |= SD0_OTAPDLYENA;
-			XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLYSEL, TapDelay);
-			TapDelay |= SD0_OTAPDLYSEL_HS200;
-			XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLYSEL, TapDelay);
-		}
+		InstancePtr->Config_TapDelay(BankNum, DeviceId, CardType);
 		DllCtrl &= ~SD0_DLL_RST;
 		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+	} else {
+#endif
+		DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL);
+		DllCtrl |= SD1_DLL_RST;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+		InstancePtr->Config_TapDelay(BankNum, DeviceId, CardType);
+		DllCtrl &= ~SD1_DLL_RST;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	}
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* API to reset the DLL
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void XSdPs_DllReset(XSdPs *InstancePtr)
+{
+	u32 ClockReg, DllCtrl;
+
+	/* Disable clock */
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET);
+	ClockReg &= ~XSDPS_CC_SD_CLK_EN_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET, ClockReg);
+
+	/* Issue DLL Reset to load zero tap values */
+	DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL);
+	if (InstancePtr->Config.DeviceId == 0U) {
+		DllCtrl |= SD0_DLL_RST;
+	} else {
+		DllCtrl |= SD1_DLL_RST;
 	}
+	XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+
+	/* Wait for 2 micro seconds */
+	(void)usleep(2U);
+
+	/* Release the DLL out of reset */
+	DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL);
+	if (InstancePtr->Config.DeviceId == 0U) {
+		DllCtrl &= ~SD0_DLL_RST;
+	} else {
+		DllCtrl &= ~SD1_DLL_RST;
+	}
+	XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+
+	/* Wait for internal clock to stabilize */
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_CLK_CTRL_OFFSET);
+	while((ClockReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) {
+		ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_CLK_CTRL_OFFSET);
+	}
+
+	/* Enable SD clock */
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET,
+			ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
 }
 #endif
 /** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_sinit.c
index 59657a7b3..e0936b308 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps_sinit.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_sinit.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2013 - 2016 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/_exit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/_exit.c
deleted file mode 100644
index 0086c59b0..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/_exit.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-
-#include <unistd.h>
-#include "xil_types.h"
-
-/*
- * _exit - Does not return.
- *
- * If R5 application runs in lock-step mode, the comparators are enabled by
- * boot code after resetting the debug logic. The debugger does not have access
- * while the R5 application is being run to avoid any intervention. After the
- * application runs, the debug logic need to be taken out of reset for the
- * debugger to gain access. Therefore the debug logic is enabled and
- * comparators are disabled in case of R5 running in lock-step mode with
- * debug logic reset in JTAG boot mode.
- */
-
-#define RPU_GLBL_CNTL_REG	0xFF9A0000U
-#define RPU_ERR_INJ_REG		0xFF9A0020U
-#define RST_LPD_DBG_REG		0xFF5E0240U
-#define BOOT_MODE_USER_REG	0xFF5E0200U
-
-#define lock_step 			0x00000008U
-#define fault_log_enable	0x00000101U
-#define debug_reset 		0x00000032U
-#define jtag_boot			0x0000000FU
-__attribute__((weak)) void _exit (sint32 status)
-{
-
-	/*
-	 * Enables the debug logic and disable the comparators
-	 * when in JTAG boot mode and R5 is in lock-step mode
-	 * if the fault log is enabled
-	 */
-	u32 debug_reg, err_inj_reg;
-	if((Xil_In32(BOOT_MODE_USER_REG) & jtag_boot) == 0){
-		if((Xil_In32(RPU_GLBL_CNTL_REG) & lock_step) == 0){
-			if((Xil_In32(RPU_ERR_INJ_REG) & fault_log_enable) != 0) {
-				if((Xil_In32(RST_LPD_DBG_REG) & debug_reset) != 0) {
-					err_inj_reg = Xil_In32(RPU_ERR_INJ_REG);
-					err_inj_reg = err_inj_reg & (~fault_log_enable);
-					Xil_Out32(RPU_ERR_INJ_REG, err_inj_reg);
-
-					debug_reg = Xil_In32(RST_LPD_DBG_REG);
-					debug_reg = debug_reg & (~debug_reset);
-					Xil_Out32(RST_LPD_DBG_REG, debug_reg);
-				}
-			}
-		}
-	}
-
-  (void)status;
-  while (1)
-  {
-     __asm__("wfi");
-  }
-}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_io.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_io.h
deleted file mode 100644
index 18cdebf7a..000000000
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_io.h
+++ /dev/null
@@ -1,244 +0,0 @@
-/******************************************************************************
-*
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
-*
-* Permission is hereby granted, free of charge, to any person obtaining a copy
-* of this software and associated documentation files (the "Software"), to deal
-* in the Software without restriction, including without limitation the rights
-* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-* copies of the Software, and to permit persons to whom the Software is
-* furnished to do so, subject to the following conditions:
-*
-* The above copyright notice and this permission notice shall be included in
-* all copies or substantial portions of the Software.
-*
-* Use of the Software is limited solely to applications:
-* (a) running on a Xilinx device, or
-* (b) that interact with a Xilinx device through a bus or interconnect.
-*
-* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
-* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-* SOFTWARE.
-*
-* Except as contained in this notice, the name of the Xilinx shall not be used
-* in advertising or otherwise to promote the sale, use or other dealings in
-* this Software without prior written authorization from Xilinx.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xil_io.h
-*
-* This file contains the interface for the general IO component, which
-* encapsulates the Input/Output functions for processors that do not
-* require any special I/O handling.
-*
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver   Who      Date     Changes
-* ----- -------- -------- -----------------------------------------------
-* 5.00 	pkp  	 02/20/14 First release
-* </pre>
-******************************************************************************/
-
-#ifndef XIL_IO_H           /* prevent circular inclusions */
-#define XIL_IO_H           /* by using protection macros */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/***************************** Include Files *********************************/
-
-#include "xil_types.h"
-#include "xpseudo_asm.h"
-#include "xil_printf.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-#if defined __GNUC__
-#  define SYNCHRONIZE_IO	dmb()
-#  define INST_SYNC		isb()
-#  define DATA_SYNC		dsb()
-#else
-#  define SYNCHRONIZE_IO
-#  define INST_SYNC
-#  define DATA_SYNC
-#endif /* __GNUC__ */
-
-/*****************************************************************************/
-/**
-*
-* Perform an big-endian input operation for a 16-bit memory location
-* by reading from the specified address and returning the Value read from
-* that address.
-*
-* @param	Addr contains the address to perform the input operation at.
-*
-* @return	The Value read from the specified input address with the
-*		proper endianness. The return Value has the same endianness
-*		as that of the processor, i.e. if the processor is
-*		little-engian, the return Value is the byte-swapped Value read
-*		from the address.
-*
-* @note		None.
-*
-******************************************************************************/
-#define Xil_In16LE(Addr) Xil_In16((Addr))
-
-/*****************************************************************************/
-/**
-*
-* Perform a big-endian input operation for a 32-bit memory location
-* by reading from the specified address and returning the Value read from
-* that address.
-*
-* @param	Addr contains the address to perform the input operation at.
-*
-* @return	The Value read from the specified input address with the
-*		proper endianness. The return Value has the same endianness
-*		as that of the processor, i.e. if the processor is
-*		little-engian, the return Value is the byte-swapped Value read
-*		from the address.
-*
-*
-* @note		None.
-*
-******************************************************************************/
-#define Xil_In32LE(Addr) Xil_In32((Addr))
-
-/*****************************************************************************/
-/**
-*
-* Perform a big-endian output operation for a 16-bit memory location
-* by writing the specified Value to the specified address.
-*
-* @param	Addr contains the address to perform the output operation at.
-* @param	Value contains the Value to be output at the specified address.
-*		The Value has the same endianness as that of the processor.
-*		If the processor is little-endian, the byte-swapped Value is
-*		written to the address.
-*
-*
-* @return	None
-*
-* @note		None.
-*
-******************************************************************************/
-#define Xil_Out16LE(Addr, Value) Xil_Out16((Addr), (Value))
-
-/*****************************************************************************/
-/**
-*
-* Perform a big-endian output operation for a 32-bit memory location
-* by writing the specified Value to the specified address.
-*
-* @param	Addr contains the address to perform the output operation at.
-* @param	Value contains the Value to be output at the specified address.
-*		The Value has the same endianness as that of the processor.
-*		If the processor is little-endian, the byte-swapped Value is
-*		written to the address.
-*
-* @return	None
-*
-* @note		None.
-*
-******************************************************************************/
-#define Xil_Out32LE(Addr, Value) Xil_Out32((Addr), (Value))
-
-/*****************************************************************************/
-/**
-*
-* Convert a 32-bit number from host byte order to network byte order.
-*
-* @param	Data the 32-bit number to be converted.
-*
-* @return	The converted 32-bit number in network byte order.
-*
-* @note		None.
-*
-******************************************************************************/
-#define Xil_Htonl(Data) Xil_EndianSwap32((Data))
-
-/*****************************************************************************/
-/**
-*
-* Convert a 16-bit number from host byte order to network byte order.
-*
-* @param	Data the 16-bit number to be converted.
-*
-* @return	The converted 16-bit number in network byte order.
-*
-* @note		None.
-*
-******************************************************************************/
-#define Xil_Htons(Data) Xil_EndianSwap16((Data))
-
-/*****************************************************************************/
-/**
-*
-* Convert a 32-bit number from network byte order to host byte order.
-*
-* @param	Data the 32-bit number to be converted.
-*
-* @return	The converted 32-bit number in host byte order.
-*
-* @note		None.
-*
-******************************************************************************/
-#define Xil_Ntohl(Data) Xil_EndianSwap32((Data))
-
-/*****************************************************************************/
-/**
-*
-* Convert a 16-bit number from network byte order to host byte order.
-*
-* @param	Data the 16-bit number to be converted.
-*
-* @return	The converted 16-bit number in host byte order.
-*
-* @note		None.
-*
-******************************************************************************/
-#define Xil_Ntohs(Data) Xil_EndianSwap16((Data))
-
-/************************** Function Prototypes ******************************/
-
-/* The following functions allow the software to be transportable across
- * processors which may use memory mapped I/O or I/O which is mapped into a
- * seperate address space.
- */
-u8 Xil_In8(INTPTR Addr);
-u16 Xil_In16(INTPTR Addr);
-u32 Xil_In32(INTPTR Addr);
-u64 Xil_In64(INTPTR Addr);
-
-void Xil_Out8(INTPTR Addr, u8 Value);
-void Xil_Out16(INTPTR Addr, u16 Value);
-void Xil_Out32(INTPTR Addr, u32 Value);
-void Xil_Out64(INTPTR Addr, u64 Value);
-
-u16 Xil_In16BE(INTPTR Addr);
-u32 Xil_In32BE(INTPTR Addr);
-void Xil_Out16BE(INTPTR Addr, u16 Value);
-void Xil_Out32BE(INTPTR Addr, u32 Value);
-
-u16 Xil_EndianSwap16(u16 Data);
-u32 Xil_EndianSwap32(u32 Data);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/Makefile
index ca8621a76..ca8621a76 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/Makefile
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/Makefile
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/_exit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/_exit.c
new file mode 100644
index 000000000..cf598882b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/_exit.c
@@ -0,0 +1,44 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include <unistd.h>
+#include "xil_types.h"
+
+/* _exit - Simple implementation. Does not return.
+*/
+__attribute__((weak)) void _exit (sint32 status)
+{
+  (void)status;
+  while (1) {
+	;
+  }
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/_open.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/_open.c
index b2809c5d0..9b5a23adf 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/_open.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/_open.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -29,7 +29,7 @@
 * this Software without prior written authorization from Xilinx.
 *
 ******************************************************************************/
-
+#ifndef UNDEFINE_FILE_OPS
 #include <errno.h>
 #include "xil_types.h"
 
@@ -51,3 +51,4 @@ __attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode)
   errno = EIO;
   return (-1);
 }
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/_sbrk.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/_sbrk.c
index bcec069c8..2a069ec06 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/_sbrk.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/_sbrk.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/abort.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/abort.c
index 122c25bbd..e8988c048 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/abort.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/abort.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/asm_vectors.S b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/asm_vectors.S
index 138c22e89..2c6f117eb 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/asm_vectors.S
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/asm_vectors.S
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -41,6 +41,7 @@
 * Ver   Who     Date     Changes
 * ----- ------- -------- ---------------------------------------------------
 * 5.00  pkp	02/10/14 Initial version
+* 6.0   mus     27/07/16 Added UndefinedException handler
 * </pre>
 *
 * @note
@@ -90,8 +91,12 @@ FIQLoop:
 
 Undefined:					/* Undefined handler */
 	stmdb	sp!,{r0-r3,r12,lr}		/* state save from compiled code */
+	ldr     r0, =UndefinedExceptionAddr
+	sub     r1, lr, #4
+	str     r1, [r0]            		/* Store address of instruction causing undefined exception */
+
+	bl	UndefinedException		/* UndefinedException: call C function here */
 	ldmia	sp!,{r0-r3,r12,lr}		/* state restore from compiled code */
-	b	_prestart
 	movs	pc, lr
 
 SVCHandler:					/* SWI handler */
@@ -107,12 +112,18 @@ SVCHandler:					/* SWI handler */
 
 DataAbortHandler:				/* Data Abort handler */
 	stmdb	sp!,{r0-r3,r12,lr}		/* state save from compiled code */
+	ldr     r0, =DataAbortAddr
+	sub     r1, lr, #8
+	str     r1, [r0]            		/* Stores instruction causing data abort */
 	bl	DataAbortInterrupt		/*DataAbortInterrupt :call C function here */
 	ldmia	sp!,{r0-r3,r12,lr}		/* state restore from compiled code */
 	subs	pc, lr, #8			/* adjust return */
 
 PrefetchAbortHandler:				/* Prefetch Abort handler */
 	stmdb	sp!,{r0-r3,r12,lr}		/* state save from compiled code */
+	ldr     r0, =PrefetchAbortAddr
+	sub     r1, lr, #4
+	str     r1, [r0]            		/* Stores instruction causing prefetch abort */
 	bl	PrefetchAbortInterrupt		/* PrefetchAbortInterrupt: call C function here */
 	ldmia	sp!,{r0-r3,r12,lr}		/* state restore from compiled code */
 	subs	pc, lr, #4			/* adjust return */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/boot.S b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/boot.S
index 724f9616f..30b97cbfa 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/boot.S
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/boot.S
@@ -50,6 +50,8 @@
 *		      lock step mode
 * 5.04 pkp   03/24/16 Reset the dbg_lpd_reset before enabling the fault log
 *		      to avoid intervention for lock-step mode
+* 5.05 pkp   04/11/16 Enable the comparators for non-JTAG boot mode for
+*		      lock-step to avoid putting debug logic to reset
 * </pre>
 *
 * @note
@@ -85,6 +87,7 @@
 .set RPU_GLBL_CNTL,	0xFF9A0000
 .set RPU_ERR_INJ,	0xFF9A0020
 .set RST_LPD_DBG,	0xFF5E0240
+.set BOOT_MODE_USER,	0xFF5E0200
 .set fault_log_enable,	0x101
 
 .section .boot,"axS"
@@ -237,6 +240,11 @@ OKToRun:
 	ands	r1, r1, #0x8
 /* branch to initialization if split mode*/
 	bne 	init
+/* check for boot mode if in lock step, branch to init if JTAG boot mode*/
+	ldr	r0,=BOOT_MODE_USER
+	ldr 	r1, [r0]
+	ands	r1, r1, #0xF
+	beq 	init
 /* reset the debug logic */
 	ldr	r0,=RST_LPD_DBG
 	ldr	r1, [r0]
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/bspconfig.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/bspconfig.h
index 4dd178f04..8671e3fbe 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/bspconfig.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/bspconfig.h
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/changelog.txt b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/changelog.txt
index ad9c771e1..f663af134 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/changelog.txt
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/changelog.txt
@@ -321,4 +321,82 @@
  *		       the fault log to avoid intervention for lock-step mode and cortexr5/
  *		       _exit.c to enable the dbg_lpd_reset once the fault log is disabled
  *		       to fix CR#947335
+ * 5.5 pkp   04/11/16  Modified cortexr5/boot.S to enable comparators for non-JTAG bootmode
+ *		       in lock-step to avoid resetting the debug logic which restricts the
+ *		       access for debugger and removed enabling back of debug modules in
+ *		       cortexr5/_exit.c
+ * 5.5 pkp   04/13/16  Modified cortexa9/gcc/read.c to return correct number of bytes when
+ *		       read buffer is filled and removed the redundant NULL checking for
+ *		       buffer to simplify the code
+ * 5.5 pkp   04/13/16  Modified cortexa53/64bit/gcc/read.c and cortexa53/32bit/gcc/read.c
+ *		       to return correct number of bytes when read buffer is filled and
+ *		       removed the redundant NULL checking for buffer to simplify the code
+ * 5.5 pkp   04/13/16  Modified cortexr5/gcc/read.c to return correct number of bytes when
+ *		       read buffer is filled and removed the redundant NULL checking for
+ *		       buffer to simplify the code
+ * 5.5 pkp   04/13/16  Modified cortexa53/64bit/xpseudo_asm_gcc.h to add volatile to asm
+ *		       instruction macros to disable certain optimizations which may move
+ *		       code out of loops if optimizers believe that the code will always
+ *		       return the same result or discard asm statements if optimizers
+ *		       determine there is no need for the output variables
+ * 5.5 pkp   04/13/16  Modified cortexa53/64bit/xtime_l.c to add XTime_StartTimer which
+ *		       starts the timer if it is disabled and modified XTime_GetTime to
+ *		       enable the timer if it is not enabled. Also modified cortexa53/64bit/
+ *		       sleep.c and cortexa53/64bit/usleep.c to enable the timer if it is
+ *		       disabled and read the counter value directly from register instead
+ *		       of using XTime_GetTime for optimization
+ * 5.5 pkp   04/13/16  Modified cortexa53/32bit/xtime_l.c to add XTime_StartTimer which
+ *		       starts the timer if it is disabled and modified XTime_GetTime to
+ *		       enable the timer if it is not enabled. Also modified cortexa53/32bit/
+ *		       sleep.c and cortexa53/32bit/usleep.c to enable the timer if it is
+ *		       disabled and read the counter value directly from register instead
+ *		       of using XTime_GetTime for optimization
+ * 5.5 pkp   04/13/16  Modified cortexa53/32bit/xil_cache.c and cortexa53/64bit/xil_cache.c
+ *		       to update the Xil_DCacheInvalidate, Xil_DCacheInvalidateLine and
+ * 		       Xil_DCacheInvalidateRange functions description for proper
+ *		       explaination to fix CR#949801
+ * 5.5 asa   04/20/16  Added missing macros for hibernate and suspend in Microblaze BSP
+ *                     file mb_interface.h. This fixes the CR#949503.
+ * 5.5 asa   04/29/16  Fix for CR#951080. Updated cache APIs for HW designs where cache
+ *                     memory is not included for MicroBlaze.
+ * 5.5 pkp   05/06/16  Modified the cortexa9/xil_exception.h to update the macros
+ *		       Xil_EnableNestedInterrupts and Xil_DisableNestedInterrupts for fixing
+ *		       the issue of lr being corrupted to resolve CR#950468
+ * 5.5 pkp   05/06/16  Modified the cortexr5/xil_exception.h to update the macros
+ *		       Xil_EnableNestedInterrupts and Xil_DisableNestedInterrupts for fixing
+ *		       the issue of lr being corrupted to resolve CR#950468
+ * 6.0 kvn   05/31/16  Make Xil_AsserWait a global variable
+ * 6.0 pkp   06/27/16  Updated cortexr5/mpu.c to move the code related to Init_MPU to .boot
+ *		       section since it is part of boot process to fix CR#949555
+ *     hk    07/12/16  Correct masks for IOU SLCR GEM registers
+ * 6.0 pkp   07/25/16  Program the counter frequency in boot code for CortexA53
+ * 6.0 asa   08/03/16  Updated sleep_common function in microblaze_sleep.c to improve the
+ *                     the accuracy of MB sleep functionality. This fixes the CR#954191.
+ * 6.0 mus   08/03/16  Restructured the BSP to avoid code duplication across all BSPs.
+ *                     Source code directories specific to ARM processor's are moved to src/arm
+ *                     directory(i.e. src/cortexa53,src/cortexa9 and src/cortexr5 moved to src/arm/cortexa53,
+ *                     src/arm/cortexa9 and src/arm/cortexr5 respectively).Files xil_printf.c,xil_printf.h,
+ *                     print.c,xil_io.c and xil_io.h are consolidated across all BSPs into common file each and
+ *                     consolidated files are kept at src/common directory.Files putnum.c,vectors.c,vectors.h,
+ *                     xil_exception.c and xil_exception.h are consolidated across all ARM BSPs
+ *                     into common file each and consolidated files are kept at src/arm/common directory.
+ *                     GCC source files related to file  operations are consolidated and kept
+ *                     at src/arm/common/gcc directory.
+ *                     All io interfacing functions (i.e. All variants of xil_out, xil_in )
+ *                     are made as static inline and implementation is kept in consolidated common/xil_io.h,
+ *                     xil_io.h must be included as a header file to access io interfacing functions.
+ *                     Added undefined exception handler for A53 32 bit and R5 processor
+ * 6.0 mus   08/11/16  Updated xtime_l.c in R5 BSP to remove implementation of XTime_SetTime API, since
+ *                     TTC counter value register is read only.
+ * 6.0 asa   08/15/16  Modified the signatures for functions sleep and usleep. This fixes
+ *                     the CR#956899.
+ * 6.0 mus   08/18/16  Defined ARMA53_32 flag in cortexa53/32bit/xparameters_ps.h and ARMR5 flag
+ *                     in cortexr5/xparameters_ps.h
+ * 6.0 mus   08/18/16  Added support for the the Zynq 7000s devices
+ * 6.0 mus   08/18/16  Removed unused variables from xil_printf.c and xplatform_info.c
+ * 6.0 mus   08/19/16  Modified xil_io.h to remove __LITTLE_ENDIAN__ flag check for all ARM processors
+ * 6.1 mus   11/03/16  Added APIs handle_stdin_parameter and handle_stdout_parameter in standalone tcl.
+ *                     ::hsi::utils::handle_stdin and ::hsi::utils::handle_stdout are taken as a base for
+ *                     these APIs and modifications are done on top of it to handle stdout/stdin
+ *                     parameters for design which doesnt have UART.It fixes CR#953681
  *****************************************************************************************/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/close.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/close.c
index e42a1ff36..dbbe0d4fd 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/close.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/close.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -29,6 +29,7 @@
 * this Software without prior written authorization from Xilinx.
 *
 ******************************************************************************/
+#ifndef UNDEFINE_FILE_OPS
 #include "xil_types.h"
 #ifdef __cplusplus
 extern "C" {
@@ -45,3 +46,4 @@ __attribute__((weak)) s32 _close(s32 fd)
   (void)fd;
   return (0);
 }
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/config.make b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/config.make
index 2b7dbb6f7..2b7dbb6f7 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/config.make
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/config.make
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/cpu_init.S b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/cpu_init.S
index 40bbc2c7a..40bbc2c7a 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/cpu_init.S
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/cpu_init.S
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/errno.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/errno.c
index daaa1212d..df0218e86 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/errno.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/errno.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/fcntl.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/fcntl.c
index 4c5de40fd..e58221a14 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/fcntl.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/fcntl.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -37,7 +37,7 @@
  * fcntl -- Manipulate a file descriptor.
  *          We don't have a filesystem, so we do nothing.
  */
-__attribute__((weak)) s32 fcntl (s32 fd, s32 cmd, s32 arg)
+__attribute__((weak)) sint32 fcntl (sint32 fd, sint32 cmd, long arg)
 {
   (void)fd;
   (void)cmd;
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/fstat.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/fstat.c
index 6271cfa84..c5a31f31b 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/fstat.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/fstat.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/getpid.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/getpid.c
index c2a84cb7f..d02df5ce2 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/getpid.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/getpid.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/inbyte.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/inbyte.c
index a5a6448d4..a5a6448d4 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/inbyte.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/inbyte.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu0_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu0_cfg.h
index 9029bead8..9029bead8 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu0_cfg.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu0_cfg.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu1_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu1_cfg.h
index e2fa6d4aa..e2fa6d4aa 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu1_cfg.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu1_cfg.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu2_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu2_cfg.h
index 55ea2a7d3..55ea2a7d3 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu2_cfg.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu2_cfg.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu3_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu3_cfg.h
index 416314967..416314967 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu3_cfg.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu3_cfg.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu4_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu4_cfg.h
index 2df814419..2df814419 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu4_cfg.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu4_cfg.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu5_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu5_cfg.h
index 60811718d..60811718d 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu5_cfg.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu5_cfg.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_slcr.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_slcr.h
index b565b958a..b565b958a 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_slcr.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_slcr.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_slcr_secure.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_slcr_secure.h
index 6541a4f1d..6541a4f1d 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_slcr_secure.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_slcr_secure.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_xmpu_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_xmpu_cfg.h
index 75aef19f9..75aef19f9 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_xmpu_cfg.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_xmpu_cfg.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_xmpu_sink.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_xmpu_sink.h
index 39172f1f4..39172f1f4 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_xmpu_sink.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_xmpu_sink.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xiou_secure_slcr.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xiou_secure_slcr.h
index cb4ad4903..cb4ad4903 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xiou_secure_slcr.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xiou_secure_slcr.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xiou_slcr.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xiou_slcr.h
index d81d178d3..c53954c97 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xiou_slcr.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xiou_slcr.h
@@ -2769,85 +2769,85 @@ extern "C" {
 #define XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_MASK    0x00300000UL
 #define XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_DEFVAL  0x0UL
 
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT   18UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH   1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_MASK    0x00040000UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT   17UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH   1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_MASK    0x00020000UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL  0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT   16UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH   1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK    0x00010000UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT   15UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH   1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK    0x00008000UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT   13UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH   1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_MASK    0x00002000UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT   12UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH   1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_MASK    0x00001000UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL  0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT   11UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH   1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK    0x00000800UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT   10UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH   1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK    0x00000400UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT   8UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH   1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_MASK    0x00000100UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT   7UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH   1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_MASK    0x00000080UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL  0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT   6UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH   1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK    0x00000040UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT   5UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH   1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK    0x00000020UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT   3UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH   1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_MASK    0x00000008UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT   2UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH   1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_MASK    0x00000004UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL  0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT   1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH   1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK    0x00000002UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL  0x0UL
-
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT   0UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH   1UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK    0x00000001UL
-#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL  0x0UL
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT   18UL
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_FIFO_SEL_MASK    0x00040000UL
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT   17UL
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH   1UL
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_SGMII_MODE_MASK    0x00020000UL
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT   16UL
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK    0x00010000UL
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT   15UL
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK    0x00008000UL
+#define XIOU_SLCR_GEM3_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT   13UL
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_FIFO_SEL_MASK    0x00002000UL
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT   12UL
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH   1UL
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_SGMII_MODE_MASK    0x00001000UL
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT   11UL
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK    0x00000800UL
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT   10UL
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK    0x00000400UL
+#define XIOU_SLCR_GEM2_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT   8UL
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_FIFO_SEL_MASK    0x00000100UL
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT   7UL
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH   1UL
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_SGMII_MODE_MASK    0x00000080UL
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT   6UL
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK    0x00000040UL
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT   5UL
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK    0x00000020UL
+#define XIOU_SLCR_GEM1_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT   3UL
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_FIFO_SEL_MASK    0x00000008UL
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT   2UL
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH   1UL
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_SGMII_MODE_MASK    0x00000004UL
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT   1UL
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT   0UL
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK    0x00000001UL
+#define XIOU_SLCR_GEM0_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL  0x0UL
 
 /**
  * Register: XiouSlcrSdioClkCtrl
@@ -2881,15 +2881,15 @@ extern "C" {
 #define XIOU_SLCR_CTRL_REG_SD    ( ( XIOU_SLCR_BASEADDR ) + 0x00000310UL )
 #define XIOU_SLCR_CTRL_REG_SD_RSTVAL   0x00000000UL
 
-#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_SHIFT   15UL
-#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_WIDTH   1UL
-#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_MASK    0x00008000UL
-#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_DEFVAL  0x0UL
+#define XIOU_SLCR_CTRL_REG_SD1_XSDPS_EMMC_SEL_SHIFT      15UL
+#define XIOU_SLCR_CTRL_REG_SD1_XSDPS_EMMC_SEL_WIDTH   1UL
+#define XIOU_SLCR_CTRL_REG_SD1_XSDPS_EMMC_SEL_MASK    0x00008000UL
+#define XIOU_SLCR_CTRL_REG_SD1_XSDPS_EMMC_SEL_DEFVAL  0x0UL
 
-#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_SHIFT   0UL
-#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_WIDTH   1UL
-#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_MASK    0x00000001UL
-#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_DEFVAL  0x0UL
+#define XIOU_SLCR_CTRL_REG_SD0_XSDPS_EMMC_SEL_SHIFT      0UL
+#define XIOU_SLCR_CTRL_REG_SD0_XSDPS_EMMC_SEL_WIDTH   1UL
+#define XIOU_SLCR_CTRL_REG_SD0_XSDPS_EMMC_SEL_MASK    0x00000001UL
+#define XIOU_SLCR_CTRL_REG_SD0_XSDPS_EMMC_SEL_DEFVAL  0x0UL
 
 /**
  * Register: XiouSlcrSdItapdly
@@ -2897,35 +2897,35 @@ extern "C" {
 #define XIOU_SLCR_SD_ITAPDLY    ( ( XIOU_SLCR_BASEADDR ) + 0x00000314UL )
 #define XIOU_SLCR_SD_ITAPDLY_RSTVAL   0x00000000UL
 
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_SHIFT   25UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_WIDTH   1UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_MASK    0x02000000UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_DEFVAL  0x0UL
+#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPCHGWIN_SHIFT      25UL
+#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPCHGWIN_WIDTH   1UL
+#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPCHGWIN_MASK    0x02000000UL
+#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPCHGWIN_DEFVAL  0x0UL
 
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_SHIFT   24UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_WIDTH   1UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_MASK    0x01000000UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_DEFVAL  0x0UL
+#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPDLYENA_SHIFT   24UL
+#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPDLYENA_WIDTH   1UL
+#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPDLYENA_MASK    0x01000000UL
+#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPDLYENA_DEFVAL  0x0UL
 
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_SHIFT   16UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_WIDTH   8UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_MASK    0x00ff0000UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_DEFVAL  0x0UL
+#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPDLYSEL_SHIFT   16UL
+#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPDLYSEL_WIDTH   8UL
+#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPDLYSEL_MASK    0x00ff0000UL
+#define XIOU_SLCR_SD1_ITAPDLY_XSDPS_ITAPDLYSEL_DEFVAL  0x0UL
 
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_SHIFT   9UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_WIDTH   1UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_MASK    0x00000200UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_DEFVAL  0x0UL
+#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPCHGWIN_SHIFT   9UL
+#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPCHGWIN_WIDTH   1UL
+#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPCHGWIN_MASK    0x00000200UL
+#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPCHGWIN_DEFVAL  0x0UL
 
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_SHIFT   8UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_WIDTH   1UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_MASK    0x00000100UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_DEFVAL  0x0UL
+#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPDLYENA_SHIFT   8UL
+#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPDLYENA_WIDTH   1UL
+#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPDLYENA_MASK    0x00000100UL
+#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPDLYENA_DEFVAL  0x0UL
 
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_SHIFT   0UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_WIDTH   8UL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_MASK    0x000000ffUL
-#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_DEFVAL  0x0UL
+#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPDLYSEL_SHIFT   0UL
+#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPDLYSEL_WIDTH   8UL
+#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPDLYSEL_MASK    0x000000ffUL
+#define XIOU_SLCR_SD0_ITAPDLY_XSDPS_ITAPDLYSEL_DEFVAL  0x0UL
 
 /**
  * Register: XiouSlcrSdOtapdlysel
@@ -2933,25 +2933,25 @@ extern "C" {
 #define XIOU_SLCR_SD_OTAPDLYSEL    ( ( XIOU_SLCR_BASEADDR ) + 0x00000318UL )
 #define XIOU_SLCR_SD_OTAPDLYSEL_RSTVAL   0x00000000UL
 
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_SHIFT   22UL
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_WIDTH   1UL
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_MASK    0x00400000UL
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_DEFVAL  0x0UL
+#define XIOU_SLCR_SD1_OTAPDLYSEL_XSDPS_OTAPDLYENA_SHIFT   22UL
+#define XIOU_SLCR_SD1_OTAPDLYSEL_XSDPS_OTAPDLYENA_WIDTH   1UL
+#define XIOU_SLCR_SD1_OTAPDLYSEL_XSDPS_OTAPDLYENA_MASK    0x00400000UL
+#define XIOU_SLCR_SD1_OTAPDLYSEL_XSDPS_OTAPDLYENA_DEFVAL  0x0UL
 
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_SHIFT   16UL
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_WIDTH   6UL
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_MASK    0x003f0000UL
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_DEFVAL  0x0UL
+#define XIOU_SLCR_SD1_OTAPDLYSEL_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD1_OTAPDLYSEL_XSDPS_WIDTH   6UL
+#define XIOU_SLCR_SD1_OTAPDLYSEL_XSDPS_MASK    0x003f0000UL
+#define XIOU_SLCR_SD1_OTAPDLYSEL_XSDPS_DEFVAL  0x0UL
 
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_SHIFT   6UL
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_WIDTH   1UL
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_MASK    0x00000040UL
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_DEFVAL  0x0UL
+#define XIOU_SLCR_SD0_OTAPDLYSEL_XSDPS_OTAPDLYENA_SHIFT      6UL
+#define XIOU_SLCR_SD0_OTAPDLYSEL_XSDPS_OTAPDLYENA_WIDTH   1UL
+#define XIOU_SLCR_SD0_OTAPDLYSEL_XSDPS_OTAPDLYENA_MASK    0x00000040UL
+#define XIOU_SLCR_SD0_OTAPDLYSEL_XSDPS_OTAPDLYENA_DEFVAL  0x0UL
 
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_SHIFT   0UL
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_WIDTH   6UL
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_MASK    0x0000003fUL
-#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_DEFVAL  0x0UL
+#define XIOU_SLCR_SD0_OTAPDLYSEL_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD0_OTAPDLYSEL_XSDPS_WIDTH   6UL
+#define XIOU_SLCR_SD0_OTAPDLYSEL_XSDPS_MASK    0x0000003fUL
+#define XIOU_SLCR_SD0_OTAPDLYSEL_XSDPS_DEFVAL  0x0UL
 
 /**
  * Register: XiouSlcrSdCfgReg1
@@ -2959,35 +2959,35 @@ extern "C" {
 #define XIOU_SLCR_SD_CFG_REG1    ( ( XIOU_SLCR_BASEADDR ) + 0x0000031CUL )
 #define XIOU_SLCR_SD_CFG_REG1_RSTVAL   0x32403240UL
 
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_SHIFT   23UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_WIDTH   8UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_MASK    0x7f800000UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_DEFVAL  0x64UL
+#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_BASECLK_SHIFT   23UL
+#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_BASECLK_WIDTH   8UL
+#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_BASECLK_MASK    0x7f800000UL
+#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_BASECLK_DEFVAL  0x64UL
 
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_SHIFT   17UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_WIDTH   6UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_MASK    0x007e0000UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_DEFVAL  0x20UL
+#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_TUNIGCOUNT_SHIFT   17UL
+#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_TUNIGCOUNT_WIDTH   6UL
+#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_TUNIGCOUNT_MASK    0x007e0000UL
+#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_TUNIGCOUNT_DEFVAL  0x20UL
 
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_SHIFT   16UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_MASK    0x00010000UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_DEFVAL  0x0UL
+#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_ASYNCWKPENA_SHIFT   16UL
+#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_ASYNCWKPENA_WIDTH   1UL
+#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_ASYNCWKPENA_MASK    0x00010000UL
+#define XIOU_SLCR_SD1_CFG_REG1_XSDPS_ASYNCWKPENA_DEFVAL  0x0UL
 
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_SHIFT   7UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_WIDTH   8UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_MASK    0x00007f80UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_DEFVAL  0x64UL
+#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_BASECLK_SHIFT   7UL
+#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_BASECLK_WIDTH   8UL
+#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_BASECLK_MASK    0x00007f80UL
+#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_BASECLK_DEFVAL  0x64UL
 
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_SHIFT   1UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_WIDTH   6UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_MASK    0x0000007eUL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_DEFVAL  0x20UL
+#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_TUNIGCOUNT_SHIFT   1UL
+#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_TUNIGCOUNT_WIDTH   6UL
+#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_TUNIGCOUNT_MASK    0x0000007eUL
+#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_TUNIGCOUNT_DEFVAL  0x20UL
 
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_SHIFT   0UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_MASK    0x00000001UL
-#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_DEFVAL  0x0UL
+#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_ASYNCWKPENA_SHIFT   0UL
+#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_ASYNCWKPENA_WIDTH   1UL
+#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_ASYNCWKPENA_MASK    0x00000001UL
+#define XIOU_SLCR_SD0_CFG_REG1_XSDPS_ASYNCWKPENA_DEFVAL  0x0UL
 
 /**
  * Register: XiouSlcrSdCfgReg2
@@ -2995,125 +2995,125 @@ extern "C" {
 #define XIOU_SLCR_SD_CFG_REG2    ( ( XIOU_SLCR_BASEADDR ) + 0x00000320UL )
 #define XIOU_SLCR_SD_CFG_REG2_RSTVAL   0x0ffc0ffcUL
 
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_SHIFT   28UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_WIDTH   2UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_MASK    0x30000000UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_DEFVAL  0x0UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_SHIFT   27UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_MASK    0x08000000UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_SHIFT   26UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_MASK    0x04000000UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_SHIFT   25UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_MASK    0x02000000UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_SHIFT   24UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_MASK    0x01000000UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_SHIFT   23UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_MASK    0x00800000UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_SHIFT   22UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_MASK    0x00400000UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_SHIFT   21UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_MASK    0x00200000UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_SHIFT   20UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_MASK    0x00100000UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_SHIFT   19UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_MASK    0x00080000UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_SHIFT   18UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_MASK    0x00040000UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_SHIFT   16UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_WIDTH   2UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_MASK    0x00030000UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_DEFVAL  0x0UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_SHIFT   12UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_WIDTH   2UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_MASK    0x00003000UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_DEFVAL  0x0UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_SHIFT   11UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_MASK    0x00000800UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_SHIFT   10UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_MASK    0x00000400UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_SHIFT   9UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_MASK    0x00000200UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_SHIFT   8UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_MASK    0x00000100UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_SHIFT   7UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_MASK    0x00000080UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_SHIFT   6UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_MASK    0x00000040UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_SHIFT   5UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_MASK    0x00000020UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_SHIFT   4UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_MASK    0x00000010UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_SHIFT   3UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_MASK    0x00000008UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_SHIFT   2UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_MASK    0x00000004UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_SHIFT   0UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_WIDTH   2UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_MASK    0x00000003UL
-#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_DEFVAL  0x0UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SLOTTYPE_SHIFT   28UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SLOTTYPE_WIDTH   2UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SLOTTYPE_MASK    0x30000000UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SLOTTYPE_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_ASYCINTR_SHIFT   27UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_ASYCINTR_WIDTH   1UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_ASYCINTR_MASK    0x08000000UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_ASYCINTR_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_64BIT_SHIFT   26UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_64BIT_WIDTH   1UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_64BIT_MASK    0x04000000UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_64BIT_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_1P8V_SHIFT   25UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_1P8V_WIDTH   1UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_1P8V_MASK    0x02000000UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_1P8V_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_3P0V_SHIFT   24UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_3P0V_WIDTH   1UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_3P0V_MASK    0x01000000UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_3P0V_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_3P3V_SHIFT   23UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_3P3V_WIDTH   1UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_3P3V_MASK    0x00800000UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_3P3V_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SUSPRES_SHIFT   22UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SUSPRES_WIDTH   1UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SUSPRES_MASK    0x00400000UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SUSPRES_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SDMA_SHIFT   21UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SDMA_WIDTH   1UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SDMA_MASK    0x00200000UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_SDMA_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_HIGHSPEED_SHIFT   20UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_HIGHSPEED_WIDTH   1UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_HIGHSPEED_MASK    0x00100000UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_HIGHSPEED_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_ADMA2_SHIFT   19UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_ADMA2_WIDTH   1UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_ADMA2_MASK    0x00080000UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_ADMA2_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_8BIT_SHIFT   18UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_8BIT_WIDTH   1UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_8BIT_MASK    0x00040000UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_8BIT_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_MAXBLK_SHIFT   16UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_MAXBLK_WIDTH   2UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_MAXBLK_MASK    0x00030000UL
+#define XIOU_SLCR_SD1_CFG_REG2_XSDPS_MAXBLK_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SLOTTYPE_SHIFT   12UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SLOTTYPE_WIDTH   2UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SLOTTYPE_MASK    0x00003000UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SLOTTYPE_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_ASYCINTR_SHIFT   11UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_ASYCINTR_WIDTH   1UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_ASYCINTR_MASK    0x00000800UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_ASYCINTR_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_64BIT_SHIFT   10UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_64BIT_WIDTH   1UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_64BIT_MASK    0x00000400UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_64BIT_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_1P8V_SHIFT   9UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_1P8V_WIDTH   1UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_1P8V_MASK    0x00000200UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_1P8V_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_3P0V_SHIFT   8UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_3P0V_WIDTH   1UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_3P0V_MASK    0x00000100UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_3P0V_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_3P3V_SHIFT   7UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_3P3V_WIDTH   1UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_3P3V_MASK    0x00000080UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_3P3V_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SUSPRES_SHIFT   6UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SUSPRES_WIDTH   1UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SUSPRES_MASK    0x00000040UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SUSPRES_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SDMA_SHIFT   5UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SDMA_WIDTH   1UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SDMA_MASK    0x00000020UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_SDMA_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_HIGHSPEED_SHIFT   4UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_HIGHSPEED_WIDTH   1UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_HIGHSPEED_MASK    0x00000010UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_HIGHSPEED_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_ADMA2_SHIFT   3UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_ADMA2_WIDTH   1UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_ADMA2_MASK    0x00000008UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_ADMA2_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_8BIT_SHIFT   2UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_8BIT_WIDTH   1UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_8BIT_MASK    0x00000004UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_8BIT_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_MAXBLK_SHIFT   0UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_MAXBLK_WIDTH   2UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_MAXBLK_MASK    0x00000003UL
+#define XIOU_SLCR_SD0_CFG_REG2_XSDPS_MAXBLK_DEFVAL  0x0UL
 
 /**
  * Register: XiouSlcrSdCfgReg3
@@ -3121,85 +3121,85 @@ extern "C" {
 #define XIOU_SLCR_SD_CFG_REG3    ( ( XIOU_SLCR_BASEADDR ) + 0x00000324UL )
 #define XIOU_SLCR_SD_CFG_REG3_RSTVAL   0x06070607UL
 
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_SHIFT   26UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_MASK    0x04000000UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_SHIFT   22UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_WIDTH   4UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_MASK    0x03c00000UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_DEFVAL  0x8UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_SHIFT   21UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_MASK    0x00200000UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_DEFVAL  0x0UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_SHIFT   20UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_MASK    0x00100000UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_DEFVAL  0x0UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_SHIFT   19UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_MASK    0x00080000UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_DEFVAL  0x0UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_SHIFT   18UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_MASK    0x00040000UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_SHIFT   17UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_MASK    0x00020000UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_SHIFT   16UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_MASK    0x00010000UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_SHIFT   10UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_MASK    0x00000400UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_SHIFT   6UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_WIDTH   4UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_MASK    0x000003c0UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_DEFVAL  0x8UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_SHIFT   5UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_MASK    0x00000020UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_DEFVAL  0x0UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_SHIFT   4UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_MASK    0x00000010UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_DEFVAL  0x0UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_SHIFT   3UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_MASK    0x00000008UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_DEFVAL  0x0UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_SHIFT   2UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_MASK    0x00000004UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_SHIFT   1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_MASK    0x00000002UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_DEFVAL  0x1UL
-
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_SHIFT   0UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_WIDTH   1UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_MASK    0x00000001UL
-#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_DEFVAL  0x1UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_TUNINGSDR50_SHIFT   26UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_TUNINGSDR50_WIDTH   1UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_TUNINGSDR50_MASK    0x04000000UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_TUNINGSDR50_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_RETUNETMR_SHIFT   22UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_RETUNETMR_WIDTH   4UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_RETUNETMR_MASK    0x03c00000UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_RETUNETMR_DEFVAL  0x8UL
+
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_DDRIVER_SHIFT   21UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_DDRIVER_WIDTH   1UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_DDRIVER_MASK    0x00200000UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_DDRIVER_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_CDRIVER_SHIFT   20UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_CDRIVER_WIDTH   1UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_CDRIVER_MASK    0x00100000UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_CDRIVER_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_ADRIVER_SHIFT   19UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_ADRIVER_WIDTH   1UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_ADRIVER_MASK    0x00080000UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_ADRIVER_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_DDR50_SHIFT   18UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_DDR50_WIDTH   1UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_DDR50_MASK    0x00040000UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_DDR50_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_SDR104_SHIFT   17UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_SDR104_WIDTH   1UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_SDR104_MASK    0x00020000UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_SDR104_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_SDR50_SHIFT   16UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_SDR50_WIDTH   1UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_SDR50_MASK    0x00010000UL
+#define XIOU_SLCR_SD1_CFG_REG3_XSDPS_SDR50_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_TUNINGSDR50_SHIFT   10UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_TUNINGSDR50_WIDTH   1UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_TUNINGSDR50_MASK    0x00000400UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_TUNINGSDR50_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_RETUNETMR_SHIFT   6UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_RETUNETMR_WIDTH   4UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_RETUNETMR_MASK    0x000003c0UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_RETUNETMR_DEFVAL  0x8UL
+
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_DDRIVER_SHIFT   5UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_DDRIVER_WIDTH   1UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_DDRIVER_MASK    0x00000020UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_DDRIVER_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_CDRIVER_SHIFT   4UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_CDRIVER_WIDTH   1UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_CDRIVER_MASK    0x00000010UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_CDRIVER_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_ADRIVER_SHIFT   3UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_ADRIVER_WIDTH   1UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_ADRIVER_MASK    0x00000008UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_ADRIVER_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_DDR50_SHIFT   2UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_DDR50_WIDTH   1UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_DDR50_MASK    0x00000004UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_DDR50_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_SDR104_SHIFT   1UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_SDR104_WIDTH   1UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_SDR104_MASK    0x00000002UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_SDR104_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_SDR50_SHIFT   0UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_SDR50_WIDTH   1UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_SDR50_MASK    0x00000001UL
+#define XIOU_SLCR_SD0_CFG_REG3_XSDPS_SDR50_DEFVAL  0x1UL
 
 /**
  * Register: XiouSlcrSdInitpreset
@@ -3207,15 +3207,15 @@ extern "C" {
 #define XIOU_SLCR_SD_INITPRESET    ( ( XIOU_SLCR_BASEADDR ) + 0x00000328UL )
 #define XIOU_SLCR_SD_INITPRESET_RSTVAL   0x01000100UL
 
-#define XIOU_SLCR_SD_INITPRESET_XSDPS_SHIFT   16UL
-#define XIOU_SLCR_SD_INITPRESET_XSDPS_WIDTH   13UL
-#define XIOU_SLCR_SD_INITPRESET_XSDPS_MASK    0x1fff0000UL
-#define XIOU_SLCR_SD_INITPRESET_XSDPS_DEFVAL  0x100UL
+#define XIOU_SLCR_SD1_INITPRESET_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD1_INITPRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD1_INITPRESET_XSDPS_MASK    0x1fff0000UL
+#define XIOU_SLCR_SD1_INITPRESET_XSDPS_DEFVAL  0x100UL
 
-#define XIOU_SLCR_SD_INITPRESET_XSDPS_SHIFT   0UL
-#define XIOU_SLCR_SD_INITPRESET_XSDPS_WIDTH   13UL
-#define XIOU_SLCR_SD_INITPRESET_XSDPS_MASK    0x00001fffUL
-#define XIOU_SLCR_SD_INITPRESET_XSDPS_DEFVAL  0x100UL
+#define XIOU_SLCR_SD0_INITPRESET_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD0_INITPRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD0_INITPRESET_XSDPS_MASK    0x00001fffUL
+#define XIOU_SLCR_SD0_INITPRESET_XSDPS_DEFVAL  0x100UL
 
 /**
  * Register: XiouSlcrSdDsppreset
@@ -3223,15 +3223,15 @@ extern "C" {
 #define XIOU_SLCR_SD_DSPPRESET    ( ( XIOU_SLCR_BASEADDR ) + 0x0000032CUL )
 #define XIOU_SLCR_SD_DSPPRESET_RSTVAL   0x00040004UL
 
-#define XIOU_SLCR_SD_DSPPRESET_XSDPS_SHIFT   16UL
-#define XIOU_SLCR_SD_DSPPRESET_XSDPS_WIDTH   13UL
-#define XIOU_SLCR_SD_DSPPRESET_XSDPS_MASK    0x1fff0000UL
-#define XIOU_SLCR_SD_DSPPRESET_XSDPS_DEFVAL  0x4UL
+#define XIOU_SLCR_SD1_DSPPRESET_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD1_DSPPRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD1_DSPPRESET_XSDPS_MASK    0x1fff0000UL
+#define XIOU_SLCR_SD1_DSPPRESET_XSDPS_DEFVAL  0x4UL
 
-#define XIOU_SLCR_SD_DSPPRESET_XSDPS_SHIFT   0UL
-#define XIOU_SLCR_SD_DSPPRESET_XSDPS_WIDTH   13UL
-#define XIOU_SLCR_SD_DSPPRESET_XSDPS_MASK    0x00001fffUL
-#define XIOU_SLCR_SD_DSPPRESET_XSDPS_DEFVAL  0x4UL
+#define XIOU_SLCR_SD0_DSPPRESET_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD0_DSPPRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD0_DSPPRESET_XSDPS_MASK    0x00001fffUL
+#define XIOU_SLCR_SD0_DSPPRESET_XSDPS_DEFVAL  0x4UL
 
 /**
  * Register: XiouSlcrSdHspdpreset
@@ -3239,15 +3239,15 @@ extern "C" {
 #define XIOU_SLCR_SD_HSPDPRESET    ( ( XIOU_SLCR_BASEADDR ) + 0x00000330UL )
 #define XIOU_SLCR_SD_HSPDPRESET_RSTVAL   0x00020002UL
 
-#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_SHIFT   16UL
-#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_WIDTH   13UL
-#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_MASK    0x1fff0000UL
-#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_DEFVAL  0x2UL
+#define XIOU_SLCR_SD1_HSPDPRESET_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD1_HSPDPRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD1_HSPDPRESET_XSDPS_MASK    0x1fff0000UL
+#define XIOU_SLCR_SD1_HSPDPRESET_XSDPS_DEFVAL  0x2UL
 
-#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_SHIFT   0UL
-#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_WIDTH   13UL
-#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_MASK    0x00001fffUL
-#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_DEFVAL  0x2UL
+#define XIOU_SLCR_SD0_HSPDPRESET_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD0_HSPDPRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD0_HSPDPRESET_XSDPS_MASK    0x00001fffUL
+#define XIOU_SLCR_SD0_HSPDPRESET_XSDPS_DEFVAL  0x2UL
 
 /**
  * Register: XiouSlcrSdSdr12preset
@@ -3255,15 +3255,15 @@ extern "C" {
 #define XIOU_SLCR_SD_SDR12PRESET    ( ( XIOU_SLCR_BASEADDR ) + 0x00000334UL )
 #define XIOU_SLCR_SD_SDR12PRESET_RSTVAL   0x00040004UL
 
-#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_SHIFT   16UL
-#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_WIDTH   13UL
-#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_MASK    0x1fff0000UL
-#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_DEFVAL  0x4UL
+#define XIOU_SLCR_SD1_SDR12PRESET_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD1_SDR12PRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD1_SDR12PRESET_XSDPS_MASK    0x1fff0000UL
+#define XIOU_SLCR_SD1_SDR12PRESET_XSDPS_DEFVAL  0x4UL
 
-#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_SHIFT   0UL
-#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_WIDTH   13UL
-#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_MASK    0x00001fffUL
-#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_DEFVAL  0x4UL
+#define XIOU_SLCR_SD0_SDR12PRESET_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD0_SDR12PRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD0_SDR12PRESET_XSDPS_MASK    0x00001fffUL
+#define XIOU_SLCR_SD0_SDR12PRESET_XSDPS_DEFVAL  0x4UL
 
 /**
  * Register: XiouSlcrSdSdr25preset
@@ -3271,15 +3271,15 @@ extern "C" {
 #define XIOU_SLCR_SD_SDR25PRESET    ( ( XIOU_SLCR_BASEADDR ) + 0x00000338UL )
 #define XIOU_SLCR_SD_SDR25PRESET_RSTVAL   0x00020002UL
 
-#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_SHIFT   16UL
-#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_WIDTH   13UL
-#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_MASK    0x1fff0000UL
-#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_DEFVAL  0x2UL
+#define XIOU_SLCR_SD1_SDR25PRESET_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD1_SDR25PRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD1_SDR25PRESET_XSDPS_MASK    0x1fff0000UL
+#define XIOU_SLCR_SD1_SDR25PRESET_XSDPS_DEFVAL  0x2UL
 
-#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_SHIFT   0UL
-#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_WIDTH   13UL
-#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_MASK    0x00001fffUL
-#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_DEFVAL  0x2UL
+#define XIOU_SLCR_SD0_SDR25PRESET_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD0_SDR25PRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD0_SDR25PRESET_XSDPS_MASK    0x00001fffUL
+#define XIOU_SLCR_SD0_SDR25PRESET_XSDPS_DEFVAL  0x2UL
 
 /**
  * Register: XiouSlcrSdSdr50prset
@@ -3287,15 +3287,15 @@ extern "C" {
 #define XIOU_SLCR_SD_SDR50PRSET    ( ( XIOU_SLCR_BASEADDR ) + 0x0000033CUL )
 #define XIOU_SLCR_SD_SDR50PRSET_RSTVAL   0x00010001UL
 
-#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_SHIFT   16UL
-#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_WIDTH   13UL
-#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_MASK    0x1fff0000UL
-#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_DEFVAL  0x1UL
+#define XIOU_SLCR_SD1_SDR50PRSET_XSDPS_SDR50PRESET_SHIFT   16UL
+#define XIOU_SLCR_SD1_SDR50PRSET_XSDPS_SDR50PRESET_WIDTH   13UL
+#define XIOU_SLCR_SD1_SDR50PRSET_XSDPS_SDR50PRESET_MASK    0x1fff0000UL
+#define XIOU_SLCR_SD1_SDR50PRSET_XSDPS_SDR50PRESET_DEFVAL  0x1UL
 
-#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_SHIFT   0UL
-#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_WIDTH   13UL
-#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_MASK    0x00001fffUL
-#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_DEFVAL  0x1UL
+#define XIOU_SLCR_SD0_SDR50PRSET_XSDPS_SDR50PRESET_SHIFT   0UL
+#define XIOU_SLCR_SD0_SDR50PRSET_XSDPS_SDR50PRESET_WIDTH   13UL
+#define XIOU_SLCR_SD0_SDR50PRSET_XSDPS_SDR50PRESET_MASK    0x00001fffUL
+#define XIOU_SLCR_SD0_SDR50PRSET_XSDPS_SDR50PRESET_DEFVAL  0x1UL
 
 /**
  * Register: XiouSlcrSdSdr104prst
@@ -3303,15 +3303,15 @@ extern "C" {
 #define XIOU_SLCR_SD_SDR104PRST    ( ( XIOU_SLCR_BASEADDR ) + 0x00000340UL )
 #define XIOU_SLCR_SD_SDR104PRST_RSTVAL   0x00000000UL
 
-#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_SHIFT   16UL
-#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_WIDTH   13UL
-#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_MASK    0x1fff0000UL
-#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_DEFVAL  0x0UL
+#define XIOU_SLCR_SD1_SDR104PRST_XSDPS_SDR104PRESET_SHIFT   16UL
+#define XIOU_SLCR_SD1_SDR104PRST_XSDPS_SDR104PRESET_WIDTH   13UL
+#define XIOU_SLCR_SD1_SDR104PRST_XSDPS_SDR104PRESET_MASK    0x1fff0000UL
+#define XIOU_SLCR_SD1_SDR104PRST_XSDPS_SDR104PRESET_DEFVAL  0x0UL
 
-#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_SHIFT   0UL
-#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_WIDTH   13UL
-#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_MASK    0x00001fffUL
-#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_DEFVAL  0x0UL
+#define XIOU_SLCR_SD0_SDR104PRST_XSDPS_SDR104PRESET_SHIFT   0UL
+#define XIOU_SLCR_SD0_SDR104PRST_XSDPS_SDR104PRESET_WIDTH   13UL
+#define XIOU_SLCR_SD0_SDR104PRST_XSDPS_SDR104PRESET_MASK    0x00001fffUL
+#define XIOU_SLCR_SD0_SDR104PRST_XSDPS_SDR104PRESET_DEFVAL  0x0UL
 
 /**
  * Register: XiouSlcrSdDdr50preset
@@ -3319,15 +3319,15 @@ extern "C" {
 #define XIOU_SLCR_SD_DDR50PRESET    ( ( XIOU_SLCR_BASEADDR ) + 0x00000344UL )
 #define XIOU_SLCR_SD_DDR50PRESET_RSTVAL   0x00020002UL
 
-#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_SHIFT   16UL
-#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_WIDTH   13UL
-#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_MASK    0x1fff0000UL
-#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_DEFVAL  0x2UL
+#define XIOU_SLCR_SD1_DDR50PRESET_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD1_DDR50PRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD1_DDR50PRESET_XSDPS_MASK    0x1fff0000UL
+#define XIOU_SLCR_SD1_DDR50PRESET_XSDPS_DEFVAL  0x2UL
 
-#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_SHIFT   0UL
-#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_WIDTH   13UL
-#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_MASK    0x00001fffUL
-#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_DEFVAL  0x2UL
+#define XIOU_SLCR_SD0_DDR50PRESET_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD0_DDR50PRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD0_DDR50PRESET_XSDPS_MASK    0x00001fffUL
+#define XIOU_SLCR_SD0_DDR50PRESET_XSDPS_DEFVAL  0x2UL
 
 /**
  * Register: XiouSlcrSdMaxcur1p8
@@ -3335,15 +3335,15 @@ extern "C" {
 #define XIOU_SLCR_SD_MAXCUR1P8    ( ( XIOU_SLCR_BASEADDR ) + 0x0000034CUL )
 #define XIOU_SLCR_SD_MAXCUR1P8_RSTVAL   0x00000000UL
 
-#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_SHIFT   16UL
-#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_WIDTH   8UL
-#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_MASK    0x00ff0000UL
-#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_DEFVAL  0x0UL
+#define XIOU_SLCR_SD1_MAXCUR1P8_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD1_MAXCUR1P8_XSDPS_WIDTH   8UL
+#define XIOU_SLCR_SD1_MAXCUR1P8_XSDPS_MASK    0x00ff0000UL
+#define XIOU_SLCR_SD1_MAXCUR1P8_XSDPS_DEFVAL  0x0UL
 
-#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_SHIFT   0UL
-#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_WIDTH   8UL
-#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_MASK    0x000000ffUL
-#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_DEFVAL  0x0UL
+#define XIOU_SLCR_SD0_MAXCUR1P8_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD0_MAXCUR1P8_XSDPS_WIDTH   8UL
+#define XIOU_SLCR_SD0_MAXCUR1P8_XSDPS_MASK    0x000000ffUL
+#define XIOU_SLCR_SD0_MAXCUR1P8_XSDPS_DEFVAL  0x0UL
 
 /**
  * Register: XiouSlcrSdMaxcur3p0
@@ -3351,15 +3351,15 @@ extern "C" {
 #define XIOU_SLCR_SD_MAXCUR3P0    ( ( XIOU_SLCR_BASEADDR ) + 0x00000350UL )
 #define XIOU_SLCR_SD_MAXCUR3P0_RSTVAL   0x00000000UL
 
-#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_SHIFT   16UL
-#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_WIDTH   8UL
-#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_MASK    0x00ff0000UL
-#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_DEFVAL  0x0UL
+#define XIOU_SLCR_SD1_MAXCUR3P0_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD1_MAXCUR3P0_XSDPS_WIDTH   8UL
+#define XIOU_SLCR_SD1_MAXCUR3P0_XSDPS_MASK    0x00ff0000UL
+#define XIOU_SLCR_SD1_MAXCUR3P0_XSDPS_DEFVAL  0x0UL
 
-#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_SHIFT   0UL
-#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_WIDTH   8UL
-#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_MASK    0x000000ffUL
-#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_DEFVAL  0x0UL
+#define XIOU_SLCR_SD0_MAXCUR3P0_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD0_MAXCUR3P0_XSDPS_WIDTH   8UL
+#define XIOU_SLCR_SD0_MAXCUR3P0_XSDPS_MASK    0x000000ffUL
+#define XIOU_SLCR_SD0_MAXCUR3P0_XSDPS_DEFVAL  0x0UL
 
 /**
  * Register: XiouSlcrSdMaxcur3p3
@@ -3367,15 +3367,15 @@ extern "C" {
 #define XIOU_SLCR_SD_MAXCUR3P3    ( ( XIOU_SLCR_BASEADDR ) + 0x00000354UL )
 #define XIOU_SLCR_SD_MAXCUR3P3_RSTVAL   0x00000000UL
 
-#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_SHIFT   16UL
-#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_WIDTH   8UL
-#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_MASK    0x00ff0000UL
-#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_DEFVAL  0x0UL
+#define XIOU_SLCR_SD1_MAXCUR3P3_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD1_MAXCUR3P3_XSDPS_WIDTH   8UL
+#define XIOU_SLCR_SD1_MAXCUR3P3_XSDPS_MASK    0x00ff0000UL
+#define XIOU_SLCR_SD1_MAXCUR3P3_XSDPS_DEFVAL  0x0UL
 
-#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_SHIFT   0UL
-#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_WIDTH   8UL
-#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_MASK    0x000000ffUL
-#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_DEFVAL  0x0UL
+#define XIOU_SLCR_SD0_MAXCUR3P3_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD0_MAXCUR3P3_XSDPS_WIDTH   8UL
+#define XIOU_SLCR_SD0_MAXCUR3P3_XSDPS_MASK    0x000000ffUL
+#define XIOU_SLCR_SD0_MAXCUR3P3_XSDPS_DEFVAL  0x0UL
 
 /**
  * Register: XiouSlcrSdDllCtrl
@@ -3383,35 +3383,35 @@ extern "C" {
 #define XIOU_SLCR_SD_DLL_CTRL    ( ( XIOU_SLCR_BASEADDR ) + 0x00000358UL )
 #define XIOU_SLCR_SD_DLL_CTRL_RSTVAL   0x00000000UL
 
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_SHIFT   18UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_WIDTH   1UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_MASK    0x00040000UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_DEFVAL  0x0UL
+#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_RST_SHIFT   18UL
+#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_RST_WIDTH   1UL
+#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_RST_MASK    0x00040000UL
+#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_RST_DEFVAL  0x0UL
 
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_SHIFT   17UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_WIDTH   1UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_MASK    0x00020000UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_DEFVAL  0x0UL
+#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_TESTMODE_SHIFT   17UL
+#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_TESTMODE_WIDTH   1UL
+#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_TESTMODE_MASK    0x00020000UL
+#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_TESTMODE_DEFVAL  0x0UL
 
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_SHIFT   16UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_WIDTH   1UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_MASK    0x00010000UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_DEFVAL  0x0UL
+#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_LOCK_SHIFT   16UL
+#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_LOCK_WIDTH   1UL
+#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_LOCK_MASK    0x00010000UL
+#define XIOU_SLCR_SD1_DLL_CTRL_XSDPS_LOCK_DEFVAL  0x0UL
 
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_SHIFT   2UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_WIDTH   1UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_MASK    0x00000004UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_DEFVAL  0x0UL
+#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_RST_SHIFT   2UL
+#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_RST_WIDTH   1UL
+#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_RST_MASK    0x00000004UL
+#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_RST_DEFVAL  0x0UL
 
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_SHIFT   1UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_WIDTH   1UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_MASK    0x00000002UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_DEFVAL  0x0UL
+#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_TESTMODE_SHIFT   1UL
+#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_TESTMODE_WIDTH   1UL
+#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_TESTMODE_MASK    0x00000002UL
+#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_TESTMODE_DEFVAL  0x0UL
 
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_SHIFT   0UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_WIDTH   1UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_MASK    0x00000001UL
-#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_DEFVAL  0x0UL
+#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_LOCK_SHIFT   0UL
+#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_LOCK_WIDTH   1UL
+#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_LOCK_MASK    0x00000001UL
+#define XIOU_SLCR_SD0_DLL_CTRL_XSDPS_LOCK_DEFVAL  0x0UL
 
 /**
  * Register: XiouSlcrSdCdnCtrl
@@ -3419,15 +3419,15 @@ extern "C" {
 #define XIOU_SLCR_SD_CDN_CTRL    ( ( XIOU_SLCR_BASEADDR ) + 0x0000035CUL )
 #define XIOU_SLCR_SD_CDN_CTRL_RSTVAL   0x00000000UL
 
-#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_SHIFT   16UL
-#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_WIDTH   1UL
-#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_MASK    0x00010000UL
-#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_DEFVAL  0x0UL
+#define XIOU_SLCR_SD1_CDN_CTRL_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD1_CDN_CTRL_XSDPS_WIDTH   1UL
+#define XIOU_SLCR_SD1_CDN_CTRL_XSDPS_MASK    0x00010000UL
+#define XIOU_SLCR_SD1_CDN_CTRL_XSDPS_DEFVAL  0x0UL
 
-#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_SHIFT   0UL
-#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_WIDTH   1UL
-#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_MASK    0x00000001UL
-#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_DEFVAL  0x0UL
+#define XIOU_SLCR_SD0_CDN_CTRL_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD0_CDN_CTRL_XSDPS_WIDTH   1UL
+#define XIOU_SLCR_SD0_CDN_CTRL_XSDPS_MASK    0x00000001UL
+#define XIOU_SLCR_SD0_CDN_CTRL_XSDPS_DEFVAL  0x0UL
 
 /**
  * Register: XiouSlcrGemCtrl
@@ -3435,25 +3435,25 @@ extern "C" {
 #define XIOU_SLCR_GEM_CTRL    ( ( XIOU_SLCR_BASEADDR ) + 0x00000360UL )
 #define XIOU_SLCR_GEM_CTRL_RSTVAL   0x00000000UL
 
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_SHIFT   6UL
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_WIDTH   2UL
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_MASK    0x000000c0UL
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_DEFVAL  0x0UL
+#define XIOU_SLCR_GEM3_CTRL_XEMACPS_SGMII_SD_SHIFT   6UL
+#define XIOU_SLCR_GEM3_CTRL_XEMACPS_SGMII_SD_WIDTH   2UL
+#define XIOU_SLCR_GEM3_CTRL_XEMACPS_SGMII_SD_MASK    0x000000c0UL
+#define XIOU_SLCR_GEM3_CTRL_XEMACPS_SGMII_SD_DEFVAL  0x0UL
 
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_SHIFT   4UL
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_WIDTH   2UL
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_MASK    0x00000030UL
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_DEFVAL  0x0UL
+#define XIOU_SLCR_GEM2_CTRL_XEMACPS_SGMII_SD_SHIFT   4UL
+#define XIOU_SLCR_GEM2_CTRL_XEMACPS_SGMII_SD_WIDTH   2UL
+#define XIOU_SLCR_GEM2_CTRL_XEMACPS_SGMII_SD_MASK    0x00000030UL
+#define XIOU_SLCR_GEM2_CTRL_XEMACPS_SGMII_SD_DEFVAL  0x0UL
 
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_SHIFT   2UL
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_WIDTH   2UL
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_MASK    0x0000000cUL
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_DEFVAL  0x0UL
+#define XIOU_SLCR_GEM1_CTRL_XEMACPS_SGMII_SD_SHIFT   2UL
+#define XIOU_SLCR_GEM1_CTRL_XEMACPS_SGMII_SD_WIDTH   2UL
+#define XIOU_SLCR_GEM1_CTRL_XEMACPS_SGMII_SD_MASK    0x0000000cUL
+#define XIOU_SLCR_GEM1_CTRL_XEMACPS_SGMII_SD_DEFVAL  0x0UL
 
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_SHIFT   0UL
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_WIDTH   2UL
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_MASK    0x00000003UL
-#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_DEFVAL  0x0UL
+#define XIOU_SLCR_GEM0_CTRL_XEMACPS_SGMII_SD_SHIFT   0UL
+#define XIOU_SLCR_GEM0_CTRL_XEMACPS_SGMII_SD_WIDTH   2UL
+#define XIOU_SLCR_GEM0_CTRL_XEMACPS_SGMII_SD_MASK    0x00000003UL
+#define XIOU_SLCR_GEM0_CTRL_XEMACPS_SGMII_SD_DEFVAL  0x0UL
 
 /**
  * Register: XiouSlcrTtcApbClk
@@ -3518,35 +3518,35 @@ extern "C" {
 #define XIOU_SLCR_COHERENT_CTRL_XNANDPS8_AXI_COH_MASK    0x0f000000UL
 #define XIOU_SLCR_COHERENT_CTRL_XNANDPS8_AXI_COH_DEFVAL  0x0UL
 
-#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_SHIFT   20UL
-#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_WIDTH   4UL
-#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_MASK    0x00f00000UL
-#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_DEFVAL  0x0UL
+#define XIOU_SLCR_COHERENT_CTRL_XSDPS1_AXI_COH_SHIFT   20UL
+#define XIOU_SLCR_COHERENT_CTRL_XSDPS1_AXI_COH_WIDTH   4UL
+#define XIOU_SLCR_COHERENT_CTRL_XSDPS1_AXI_COH_MASK    0x00f00000UL
+#define XIOU_SLCR_COHERENT_CTRL_XSDPS1_AXI_COH_DEFVAL  0x0UL
 
-#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_SHIFT   16UL
-#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_WIDTH   4UL
-#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_MASK    0x000f0000UL
-#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_DEFVAL  0x0UL
+#define XIOU_SLCR_COHERENT_CTRL_XSDPS0_AXI_COH_SHIFT   16UL
+#define XIOU_SLCR_COHERENT_CTRL_XSDPS0_AXI_COH_WIDTH   4UL
+#define XIOU_SLCR_COHERENT_CTRL_XSDPS0_AXI_COH_MASK    0x000f0000UL
+#define XIOU_SLCR_COHERENT_CTRL_XSDPS0_AXI_COH_DEFVAL  0x0UL
 
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_SHIFT   12UL
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_WIDTH   4UL
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_MASK    0x0000f000UL
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_DEFVAL  0x0UL
+#define XIOU_SLCR_COHERENT_CTRL_GEM3_AXI_COH_SHIFT   12UL
+#define XIOU_SLCR_COHERENT_CTRL_GEM3_AXI_COH_WIDTH   4UL
+#define XIOU_SLCR_COHERENT_CTRL_GEM3_AXI_COH_MASK    0x0000f000UL
+#define XIOU_SLCR_COHERENT_CTRL_GEM3_AXI_COH_DEFVAL  0x0UL
 
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_SHIFT   8UL
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_WIDTH   4UL
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_MASK    0x00000f00UL
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_DEFVAL  0x0UL
+#define XIOU_SLCR_COHERENT_CTRL_GEM2_AXI_COH_SHIFT   8UL
+#define XIOU_SLCR_COHERENT_CTRL_GEM2_AXI_COH_WIDTH   4UL
+#define XIOU_SLCR_COHERENT_CTRL_GEM2_AXI_COH_MASK    0x00000f00UL
+#define XIOU_SLCR_COHERENT_CTRL_GEM2_AXI_COH_DEFVAL  0x0UL
 
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_SHIFT   4UL
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_WIDTH   4UL
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_MASK    0x000000f0UL
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_DEFVAL  0x0UL
+#define XIOU_SLCR_COHERENT_CTRL_GEM1_AXI_COH_SHIFT   4UL
+#define XIOU_SLCR_COHERENT_CTRL_GEM1_AXI_COH_WIDTH   4UL
+#define XIOU_SLCR_COHERENT_CTRL_GEM1_AXI_COH_MASK    0x000000f0UL
+#define XIOU_SLCR_COHERENT_CTRL_GEM1_AXI_COH_DEFVAL  0x0UL
 
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_SHIFT   0UL
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_WIDTH   4UL
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_MASK    0x0000000fUL
-#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_DEFVAL  0x0UL
+#define XIOU_SLCR_COHERENT_CTRL_GEM0_AXI_COH_SHIFT   0UL
+#define XIOU_SLCR_COHERENT_CTRL_GEM0_AXI_COH_WIDTH   4UL
+#define XIOU_SLCR_COHERENT_CTRL_GEM0_AXI_COH_MASK    0x0000000fUL
+#define XIOU_SLCR_COHERENT_CTRL_GEM0_AXI_COH_DEFVAL  0x0UL
 
 /**
  * Register: XiouSlcrVideoPssClkSel
@@ -3580,221 +3580,221 @@ extern "C" {
 #define XIOU_SLCR_INTERCONNECT_ROUTE_QSPI_MASK    0x00000040UL
 #define XIOU_SLCR_INTERCONNECT_ROUTE_QSPI_DEFVAL  0x0UL
 
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_SHIFT   5UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_WIDTH   1UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_MASK    0x00000020UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_DEFVAL  0x0UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS1_SHIFT   5UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS1_WIDTH   1UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS1_MASK    0x00000020UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS1_DEFVAL  0x0UL
 
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_SHIFT   4UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_WIDTH   1UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_MASK    0x00000010UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_DEFVAL  0x0UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS0_SHIFT   4UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS0_WIDTH   1UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS0_MASK    0x00000010UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS0_DEFVAL  0x0UL
 
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_SHIFT   3UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_WIDTH   1UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_MASK    0x00000008UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_DEFVAL  0x0UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM3_SHIFT   3UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM3_WIDTH   1UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM3_MASK    0x00000008UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM3_DEFVAL  0x0UL
 
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_SHIFT   2UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_WIDTH   1UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_MASK    0x00000004UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_DEFVAL  0x0UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM2_SHIFT   2UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM2_WIDTH   1UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM2_MASK    0x00000004UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM2_DEFVAL  0x0UL
 
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_SHIFT   1UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_WIDTH   1UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_MASK    0x00000002UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_DEFVAL  0x0UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM1_SHIFT   1UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM1_WIDTH   1UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM1_MASK    0x00000002UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM1_DEFVAL  0x0UL
 
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_SHIFT   0UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_WIDTH   1UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_MASK    0x00000001UL
-#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_DEFVAL  0x0UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM0_SHIFT   0UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM0_WIDTH   1UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM0_MASK    0x00000001UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_GEM0_DEFVAL  0x0UL
 
-/**
- * Register: XiouSlcrRamXemacps
+/**
+ * Register: XiouSlcrRamGem0
  */
-#define XIOU_SLCR_RAM_XEMACPS    ( ( XIOU_SLCR_BASEADDR ) + 0x00000500UL )
-#define XIOU_SLCR_RAM_XEMACPS_RSTVAL   0x00005b5bUL
-
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_SHIFT   14UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_WIDTH   1UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_MASK    0x00004000UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_DEFVAL  0x1UL
+#define XIOU_SLCR_RAM_GEM0    ( ( XIOU_SLCR_BASEADDR ) + 0x00000500UL )
+#define XIOU_SLCR_RAM_GEM0_RSTVAL   0x00005b5bUL
+
+#define XIOU_SLCR_RAM_GEM0_EMASA1_SHIFT   14UL
+#define XIOU_SLCR_RAM_GEM0_EMASA1_WIDTH   1UL
+#define XIOU_SLCR_RAM_GEM0_EMASA1_MASK    0x00004000UL
+#define XIOU_SLCR_RAM_GEM0_EMASA1_DEFVAL  0x1UL
 
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_SHIFT   11UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_WIDTH   3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_MASK    0x00003800UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_DEFVAL  0x3UL
+#define XIOU_SLCR_RAM_GEM0_EMAB1_SHIFT   11UL
+#define XIOU_SLCR_RAM_GEM0_EMAB1_WIDTH   3UL
+#define XIOU_SLCR_RAM_GEM0_EMAB1_MASK    0x00003800UL
+#define XIOU_SLCR_RAM_GEM0_EMAB1_DEFVAL  0x3UL
 
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_SHIFT   8UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_WIDTH   3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_MASK    0x00000700UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_DEFVAL  0x3UL
+#define XIOU_SLCR_RAM_GEM0_EMAA1_SHIFT   8UL
+#define XIOU_SLCR_RAM_GEM0_EMAA1_WIDTH   3UL
+#define XIOU_SLCR_RAM_GEM0_EMAA1_MASK    0x00000700UL
+#define XIOU_SLCR_RAM_GEM0_EMAA1_DEFVAL  0x3UL
 
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_SHIFT   6UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_WIDTH   1UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_MASK    0x00000040UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_DEFVAL  0x1UL
+#define XIOU_SLCR_RAM_GEM0_EMASA0_SHIFT   6UL
+#define XIOU_SLCR_RAM_GEM0_EMASA0_WIDTH   1UL
+#define XIOU_SLCR_RAM_GEM0_EMASA0_MASK    0x00000040UL
+#define XIOU_SLCR_RAM_GEM0_EMASA0_DEFVAL  0x1UL
 
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_SHIFT   3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_WIDTH   3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_MASK    0x00000038UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_DEFVAL  0x3UL
+#define XIOU_SLCR_RAM_GEM0_EMAB0_SHIFT   3UL
+#define XIOU_SLCR_RAM_GEM0_EMAB0_WIDTH   3UL
+#define XIOU_SLCR_RAM_GEM0_EMAB0_MASK    0x00000038UL
+#define XIOU_SLCR_RAM_GEM0_EMAB0_DEFVAL  0x3UL
 
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_SHIFT   0UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_WIDTH   3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_MASK    0x00000007UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_DEFVAL  0x3UL
+#define XIOU_SLCR_RAM_GEM0_EMAA0_SHIFT   0UL
+#define XIOU_SLCR_RAM_GEM0_EMAA0_WIDTH   3UL
+#define XIOU_SLCR_RAM_GEM0_EMAA0_MASK    0x00000007UL
+#define XIOU_SLCR_RAM_GEM0_EMAA0_DEFVAL  0x3UL
 
-/**
- * Register: XiouSlcrRamXemacps
+/**
+ * Register: XiouSlcrRamgem1
  */
-#define XIOU_SLCR_RAM_XEMACPS    ( ( XIOU_SLCR_BASEADDR ) + 0x00000504UL )
-#define XIOU_SLCR_RAM_XEMACPS_RSTVAL   0x00005b5bUL
-
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_SHIFT   14UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_WIDTH   1UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_MASK    0x00004000UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_DEFVAL  0x1UL
+#define XIOU_SLCR_RAM_GEM1    ( ( XIOU_SLCR_BASEADDR ) + 0x00000504UL )
+#define XIOU_SLCR_RAM_GEM1_RSTVAL   0x00005b5bUL
+
+#define XIOU_SLCR_RAM_GEM1_EMASA1_SHIFT   14UL
+#define XIOU_SLCR_RAM_GEM1_EMASA1_WIDTH   1UL
+#define XIOU_SLCR_RAM_GEM1_EMASA1_MASK    0x00004000UL
+#define XIOU_SLCR_RAM_GEM1_EMASA1_DEFVAL  0x1UL
 
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_SHIFT   11UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_WIDTH   3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_MASK    0x00003800UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_DEFVAL  0x3UL
+#define XIOU_SLCR_RAM_GEM1_EMAB1_SHIFT   11UL
+#define XIOU_SLCR_RAM_GEM1_EMAB1_WIDTH   3UL
+#define XIOU_SLCR_RAM_GEM1_EMAB1_MASK    0x00003800UL
+#define XIOU_SLCR_RAM_GEM1_EMAB1_DEFVAL  0x3UL
 
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_SHIFT   8UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_WIDTH   3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_MASK    0x00000700UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_DEFVAL  0x3UL
+#define XIOU_SLCR_RAM_GEM1_EMAA1_SHIFT   8UL
+#define XIOU_SLCR_RAM_GEM1_EMAA1_WIDTH   3UL
+#define XIOU_SLCR_RAM_GEM1_EMAA1_MASK    0x00000700UL
+#define XIOU_SLCR_RAM_GEM1_EMAA1_DEFVAL  0x3UL
 
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_SHIFT   6UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_WIDTH   1UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_MASK    0x00000040UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_DEFVAL  0x1UL
+#define XIOU_SLCR_RAM_GEM1_EMASA0_SHIFT   6UL
+#define XIOU_SLCR_RAM_GEM1_EMASA0_WIDTH   1UL
+#define XIOU_SLCR_RAM_GEM1_EMASA0_MASK    0x00000040UL
+#define XIOU_SLCR_RAM_GEM1_EMASA0_DEFVAL  0x1UL
 
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_SHIFT   3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_WIDTH   3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_MASK    0x00000038UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_DEFVAL  0x3UL
+#define XIOU_SLCR_RAM_GEM1_EMAB0_SHIFT   3UL
+#define XIOU_SLCR_RAM_GEM1_EMAB0_WIDTH   3UL
+#define XIOU_SLCR_RAM_GEM1_EMAB0_MASK    0x00000038UL
+#define XIOU_SLCR_RAM_GEM1_EMAB0_DEFVAL  0x3UL
 
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_SHIFT   0UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_WIDTH   3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_MASK    0x00000007UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_DEFVAL  0x3UL
+#define XIOU_SLCR_RAM_GEM1_EMAA0_SHIFT   0UL
+#define XIOU_SLCR_RAM_GEM1_EMAA0_WIDTH   3UL
+#define XIOU_SLCR_RAM_GEM1_EMAA0_MASK    0x00000007UL
+#define XIOU_SLCR_RAM_GEM1_EMAA0_DEFVAL  0x3UL
 
 /**
- * Register: XiouSlcrRamXemacps
+ * Register: XiouSlcrRamGem2
  */
-#define XIOU_SLCR_RAM_XEMACPS    ( ( XIOU_SLCR_BASEADDR ) + 0x00000508UL )
-#define XIOU_SLCR_RAM_XEMACPS_RSTVAL   0x00005b5bUL
+#define XIOU_SLCR_RAM_GEM2    ( ( XIOU_SLCR_BASEADDR ) + 0x00000508UL )
+#define XIOU_SLCR_RAM_GEM2_RSTVAL   0x00005b5bUL
 
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_SHIFT   14UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_WIDTH   1UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_MASK    0x00004000UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_DEFVAL  0x1UL
+#define XIOU_SLCR_RAM_GEM2_EMASA1_SHIFT   14UL
+#define XIOU_SLCR_RAM_GEM2_EMASA1_WIDTH   1UL
+#define XIOU_SLCR_RAM_GEM2_EMASA1_MASK    0x00004000UL
+#define XIOU_SLCR_RAM_GEM2_EMASA1_DEFVAL  0x1UL
 
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_SHIFT   11UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_WIDTH   3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_MASK    0x00003800UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_DEFVAL  0x3UL
+#define XIOU_SLCR_RAM_GEM2_EMAB1_SHIFT   11UL
+#define XIOU_SLCR_RAM_GEM2_EMAB1_WIDTH   3UL
+#define XIOU_SLCR_RAM_GEM2_EMAB1_MASK    0x00003800UL
+#define XIOU_SLCR_RAM_GEM2_EMAB1_DEFVAL  0x3UL
 
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_SHIFT   8UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_WIDTH   3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_MASK    0x00000700UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_DEFVAL  0x3UL
+#define XIOU_SLCR_RAM_GEM2_EMAA1_SHIFT   8UL
+#define XIOU_SLCR_RAM_GEM2_EMAA1_WIDTH   3UL
+#define XIOU_SLCR_RAM_GEM2_EMAA1_MASK    0x00000700UL
+#define XIOU_SLCR_RAM_GEM2_EMAA1_DEFVAL  0x3UL
 
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_SHIFT   6UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_WIDTH   1UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_MASK    0x00000040UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_DEFVAL  0x1UL
+#define XIOU_SLCR_RAM_GEM2_EMASA0_SHIFT   6UL
+#define XIOU_SLCR_RAM_GEM2_EMASA0_WIDTH   1UL
+#define XIOU_SLCR_RAM_GEM2_EMASA0_MASK    0x00000040UL
+#define XIOU_SLCR_RAM_GEM2_EMASA0_DEFVAL  0x1UL
 
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_SHIFT   3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_WIDTH   3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_MASK    0x00000038UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_DEFVAL  0x3UL
+#define XIOU_SLCR_RAM_GEM2_EMAB0_SHIFT   3UL
+#define XIOU_SLCR_RAM_GEM2_EMAB0_WIDTH   3UL
+#define XIOU_SLCR_RAM_GEM2_EMAB0_MASK    0x00000038UL
+#define XIOU_SLCR_RAM_GEM2_EMAB0_DEFVAL  0x3UL
 
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_SHIFT   0UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_WIDTH   3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_MASK    0x00000007UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_DEFVAL  0x3UL
+#define XIOU_SLCR_RAM_GEM2_EMAA0_SHIFT   0UL
+#define XIOU_SLCR_RAM_GEM2_EMAA0_WIDTH   3UL
+#define XIOU_SLCR_RAM_GEM2_EMAA0_MASK    0x00000007UL
+#define XIOU_SLCR_RAM_GEM2_EMAA0_DEFVAL  0x3UL
 
 /**
- * Register: XiouSlcrRamXemacps
+ * Register: XiouSlcrRamGem3
  */
-#define XIOU_SLCR_RAM_XEMACPS    ( ( XIOU_SLCR_BASEADDR ) + 0x0000050CUL )
-#define XIOU_SLCR_RAM_XEMACPS_RSTVAL   0x00005b5bUL
+#define XIOU_SLCR_RAM_GEM3    ( ( XIOU_SLCR_BASEADDR ) + 0x0000050CUL )
+#define XIOU_SLCR_RAM_GEM3_RSTVAL   0x00005b5bUL
 
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_SHIFT   14UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_WIDTH   1UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_MASK    0x00004000UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA1_DEFVAL  0x1UL
+#define XIOU_SLCR_RAM_GEM3_EMASA1_SHIFT   14UL
+#define XIOU_SLCR_RAM_GEM3_EMASA1_WIDTH   1UL
+#define XIOU_SLCR_RAM_GEM3_EMASA1_MASK    0x00004000UL
+#define XIOU_SLCR_RAM_GEM3_EMASA1_DEFVAL  0x1UL
 
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_SHIFT   11UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_WIDTH   3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_MASK    0x00003800UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB1_DEFVAL  0x3UL
+#define XIOU_SLCR_RAM_GEM3_EMAB1_SHIFT   11UL
+#define XIOU_SLCR_RAM_GEM3_EMAB1_WIDTH   3UL
+#define XIOU_SLCR_RAM_GEM3_EMAB1_MASK    0x00003800UL
+#define XIOU_SLCR_RAM_GEM3_EMAB1_DEFVAL  0x3UL
 
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_SHIFT   8UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_WIDTH   3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_MASK    0x00000700UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA1_DEFVAL  0x3UL
+#define XIOU_SLCR_RAM_GEM3_EMAA1_SHIFT   8UL
+#define XIOU_SLCR_RAM_GEM3_EMAA1_WIDTH   3UL
+#define XIOU_SLCR_RAM_GEM3_EMAA1_MASK    0x00000700UL
+#define XIOU_SLCR_RAM_GEM3_EMAA1_DEFVAL  0x3UL
 
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_SHIFT   6UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_WIDTH   1UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_MASK    0x00000040UL
-#define XIOU_SLCR_RAM_XEMACPS_EMASA0_DEFVAL  0x1UL
+#define XIOU_SLCR_RAM_GEM3_EMASA0_SHIFT   6UL
+#define XIOU_SLCR_RAM_GEM3_EMASA0_WIDTH   1UL
+#define XIOU_SLCR_RAM_GEM3_EMASA0_MASK    0x00000040UL
+#define XIOU_SLCR_RAM_GEM3_EMASA0_DEFVAL  0x1UL
 
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_SHIFT   3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_WIDTH   3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_MASK    0x00000038UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAB0_DEFVAL  0x3UL
+#define XIOU_SLCR_RAM_GEM3_EMAB0_SHIFT   3UL
+#define XIOU_SLCR_RAM_GEM3_EMAB0_WIDTH   3UL
+#define XIOU_SLCR_RAM_GEM3_EMAB0_MASK    0x00000038UL
+#define XIOU_SLCR_RAM_GEM3_EMAB0_DEFVAL  0x3UL
 
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_SHIFT   0UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_WIDTH   3UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_MASK    0x00000007UL
-#define XIOU_SLCR_RAM_XEMACPS_EMAA0_DEFVAL  0x3UL
+#define XIOU_SLCR_RAM_GEM3_EMAA0_SHIFT   0UL
+#define XIOU_SLCR_RAM_GEM3_EMAA0_WIDTH   3UL
+#define XIOU_SLCR_RAM_GEM3_EMAA0_MASK    0x00000007UL
+#define XIOU_SLCR_RAM_GEM3_EMAA0_DEFVAL  0x3UL
 
 /**
- * Register: XiouSlcrRamXsdps
+ * Register: XiouSlcrRamXsdps0
  */
-#define XIOU_SLCR_RAM_XSDPS    ( ( XIOU_SLCR_BASEADDR ) + 0x00000510UL )
-#define XIOU_SLCR_RAM_XSDPS_RSTVAL   0x0000005bUL
+#define XIOU_SLCR_RAM_XSDPS0    ( ( XIOU_SLCR_BASEADDR ) + 0x00000510UL )
+#define XIOU_SLCR_RAM_XSDPS0_RSTVAL   0x0000005bUL
 
-#define XIOU_SLCR_RAM_XSDPS_EMASA0_SHIFT   6UL
-#define XIOU_SLCR_RAM_XSDPS_EMASA0_WIDTH   1UL
-#define XIOU_SLCR_RAM_XSDPS_EMASA0_MASK    0x00000040UL
-#define XIOU_SLCR_RAM_XSDPS_EMASA0_DEFVAL  0x1UL
+#define XIOU_SLCR_RAM_XSDPS0_EMASA0_SHIFT   6UL
+#define XIOU_SLCR_RAM_XSDPS0_EMASA0_WIDTH   1UL
+#define XIOU_SLCR_RAM_XSDPS0_EMASA0_MASK    0x00000040UL
+#define XIOU_SLCR_RAM_XSDPS0_EMASA0_DEFVAL  0x1UL
 
-#define XIOU_SLCR_RAM_XSDPS_EMAB0_SHIFT   3UL
-#define XIOU_SLCR_RAM_XSDPS_EMAB0_WIDTH   3UL
-#define XIOU_SLCR_RAM_XSDPS_EMAB0_MASK    0x00000038UL
-#define XIOU_SLCR_RAM_XSDPS_EMAB0_DEFVAL  0x3UL
+#define XIOU_SLCR_RAM_XSDPS0_EMAB0_SHIFT   3UL
+#define XIOU_SLCR_RAM_XSDPS0_EMAB0_WIDTH   3UL
+#define XIOU_SLCR_RAM_XSDPS0_EMAB0_MASK    0x00000038UL
+#define XIOU_SLCR_RAM_XSDPS0_EMAB0_DEFVAL  0x3UL
 
-#define XIOU_SLCR_RAM_XSDPS_EMAA0_SHIFT   0UL
-#define XIOU_SLCR_RAM_XSDPS_EMAA0_WIDTH   3UL
-#define XIOU_SLCR_RAM_XSDPS_EMAA0_MASK    0x00000007UL
-#define XIOU_SLCR_RAM_XSDPS_EMAA0_DEFVAL  0x3UL
+#define XIOU_SLCR_RAM_XSDPS0_EMAA0_SHIFT   0UL
+#define XIOU_SLCR_RAM_XSDPS0_EMAA0_WIDTH   3UL
+#define XIOU_SLCR_RAM_XSDPS0_EMAA0_MASK    0x00000007UL
+#define XIOU_SLCR_RAM_XSDPS0_EMAA0_DEFVAL  0x3UL
 
 /**
- * Register: XiouSlcrRamXsdps
+ * Register: XiouSlcrRamXsdps1
  */
-#define XIOU_SLCR_RAM_XSDPS    ( ( XIOU_SLCR_BASEADDR ) + 0x00000514UL )
-#define XIOU_SLCR_RAM_XSDPS_RSTVAL   0x0000005bUL
+#define XIOU_SLCR_RAM_XSDPS1    ( ( XIOU_SLCR_BASEADDR ) + 0x00000514UL )
+#define XIOU_SLCR_RAM_XSDPS1_RSTVAL   0x0000005bUL
 
-#define XIOU_SLCR_RAM_XSDPS_EMASA0_SHIFT   6UL
-#define XIOU_SLCR_RAM_XSDPS_EMASA0_WIDTH   1UL
-#define XIOU_SLCR_RAM_XSDPS_EMASA0_MASK    0x00000040UL
-#define XIOU_SLCR_RAM_XSDPS_EMASA0_DEFVAL  0x1UL
+#define XIOU_SLCR_RAM_XSDPS1_EMASA0_SHIFT   6UL
+#define XIOU_SLCR_RAM_XSDPS1_EMASA0_WIDTH   1UL
+#define XIOU_SLCR_RAM_XSDPS1_EMASA0_MASK    0x00000040UL
+#define XIOU_SLCR_RAM_XSDPS1_EMASA0_DEFVAL  0x1UL
 
-#define XIOU_SLCR_RAM_XSDPS_EMAB0_SHIFT   3UL
-#define XIOU_SLCR_RAM_XSDPS_EMAB0_WIDTH   3UL
-#define XIOU_SLCR_RAM_XSDPS_EMAB0_MASK    0x00000038UL
-#define XIOU_SLCR_RAM_XSDPS_EMAB0_DEFVAL  0x3UL
+#define XIOU_SLCR_RAM_XSDPS1_EMAB0_SHIFT   3UL
+#define XIOU_SLCR_RAM_XSDPS1_EMAB0_WIDTH   3UL
+#define XIOU_SLCR_RAM_XSDPS1_EMAB0_MASK    0x00000038UL
+#define XIOU_SLCR_RAM_XSDPS1_EMAB0_DEFVAL  0x3UL
 
-#define XIOU_SLCR_RAM_XSDPS_EMAA0_SHIFT   0UL
-#define XIOU_SLCR_RAM_XSDPS_EMAA0_WIDTH   3UL
-#define XIOU_SLCR_RAM_XSDPS_EMAA0_MASK    0x00000007UL
-#define XIOU_SLCR_RAM_XSDPS_EMAA0_DEFVAL  0x3UL
+#define XIOU_SLCR_RAM_XSDPS1_EMAA0_SHIFT   0UL
+#define XIOU_SLCR_RAM_XSDPS1_EMAA0_WIDTH   3UL
+#define XIOU_SLCR_RAM_XSDPS1_EMAA0_MASK    0x00000007UL
+#define XIOU_SLCR_RAM_XSDPS1_EMAA0_DEFVAL  0x3UL
 
 /**
  * Register: XiouSlcrRamCan0
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_slcr.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_slcr.h
index cc05672e4..cc05672e4 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_slcr.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_slcr.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_slcr_secure.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_slcr_secure.h
index aff3bf2fa..aff3bf2fa 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_slcr_secure.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_slcr_secure.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_xppu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_xppu.h
index a5145eac7..a5145eac7 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_xppu.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_xppu.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_xppu_sink.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_xppu_sink.h
index 95f7e20a2..95f7e20a2 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_xppu_sink.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_xppu_sink.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xocm_xmpu_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xocm_xmpu_cfg.h
index 5e3631f3e..5e3631f3e 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xocm_xmpu_cfg.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xocm_xmpu_cfg.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/isatty.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/isatty.c
index 242d8faf3..f14251511 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/isatty.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/isatty.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/kill.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/kill.c
index 1c67ace57..fc2f89d6c 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/kill.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/kill.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -35,7 +35,7 @@
 
 #ifdef __cplusplus
 extern "C" {
-	__attribute__((weak)) s32 _kill(s32 pid, s32 sig);
+	__attribute__((weak)) int _kill(pid_t pid, int sig);
 }
 #endif
 
@@ -43,7 +43,7 @@ extern "C" {
  * kill -- go out via exit...
  */
 
-__attribute__((weak)) s32 kill(s32 pid, s32 sig)
+__attribute__((weak)) int kill(pid_t pid, int sig)
 {
   if(pid == 1) {
     _exit(sig);
@@ -51,7 +51,7 @@ __attribute__((weak)) s32 kill(s32 pid, s32 sig)
   return 0;
 }
 
-__attribute__((weak)) s32 _kill(s32 pid, s32 sig)
+__attribute__((weak)) int _kill(pid_t pid, int sig)
 {
   if(pid == 1) {
     _exit(sig);
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/lseek.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/lseek.c
index 5cd5a2dd1..106c45c89 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/lseek.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/lseek.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/mpu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/mpu.c
index bf5ddeefe..55cdd4992 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/mpu.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/mpu.c
@@ -42,6 +42,8 @@
 * ----- ---- -------- ---------------------------------------------------
 * 5.00 	pkp  02/20/14 First release
 * 5.04	pkp  12/18/15 Updated MPU initialization as per the proper address map
+* 6.00  pkp  06/27/16 moving the Init_MPU code to .boot section since it is a
+*                     part of processor boot process
 * </pre>
 *
 * @note
@@ -100,9 +102,9 @@ static const struct {
 };
 
 /************************** Function Prototypes ******************************/
-void Init_MPU(void);
-static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib);
-static void Xil_DisableMPURegions(void);
+void Init_MPU(void) __attribute__((__section__(".boot")));
+static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib) __attribute__((__section__(".boot")));
+static void Xil_DisableMPURegions(void) __attribute__((__section__(".boot")));
 
 /*****************************************************************************
 *
@@ -280,4 +282,4 @@ static void Xil_DisableMPURegions(void)
 		isb();
 	}
 
-}
-\ No newline at end of file
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/open.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/open.c
index c32530bab..4b51839fd 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/open.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/open.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -29,11 +29,7 @@
 * this Software without prior written authorization from Xilinx.
 *
 ******************************************************************************/
-
-/* Use toolchain function for openamp applications*/
-
 #ifndef UNDEFINE_FILE_OPS
-
 #include <errno.h>
 #include "xil_types.h"
 
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/outbyte.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/outbyte.c
index 3c6430886..3c6430886 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/outbyte.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/outbyte.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/print.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/print.c
index 31d7b1989..74d70ee4a 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/print.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/print.c
@@ -24,7 +24,7 @@ void print(const char8 *ptr)
 #ifdef STDOUT_BASEADDRESS
   while (*ptr != (char8)0) {
     outbyte (*ptr);
-	*ptr++;
+	ptr++;
   }
 #else
 (void)ptr;
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/putnum.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/putnum.c
index 86d3a74e8..aaf9edee7 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/putnum.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/putnum.c
@@ -27,7 +27,7 @@ void putnum(u32 num);
 void putnum(u32 num)
 {
   char8  buf[9];
-  u32   cnt;
+  s32  cnt;
   s32 i;
   char8  *ptr;
   u32  digit;
@@ -36,7 +36,7 @@ void putnum(u32 num)
   }
 
   ptr = buf;
-  for (cnt = 7U ; cnt >= 0U ; cnt--) {
+  for (cnt = 7 ; cnt >= 0 ; cnt--) {
     digit = (num >> (cnt * 4U)) & 0x0000000fU;
 
     if ((digit <= 9U) && (ptr != NULL)) {
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/read.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/read.c
index 90fb25029..7f7b7d261 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/read.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/read.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -29,15 +29,12 @@
 * this Software without prior written authorization from Xilinx.
 *
 ******************************************************************************/
-/* Use toolchain function for openamp applications*/
-
-#ifndef UNDEFINE_FILE_OPS
 
 /* read.c -- read bytes from a input device.
  */
-
-#include "xparameters.h"
+#ifndef UNDEFINE_FILE_OPS
 #include "xil_printf.h"
+#include "xparameters.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -54,25 +51,21 @@ read (s32 fd, char8* buf, s32 nbytes)
 {
 #ifdef STDIN_BASEADDRESS
   s32 i;
+  s32 numbytes = 0;
   char8* LocalBuf = buf;
 
   (void)fd;
-  for (i = 0; i < nbytes; i++) {
-	if(LocalBuf != NULL) {
-		LocalBuf += i;
-	}
-	if(LocalBuf != NULL) {
-	    *LocalBuf = inbyte();
-	    if ((*LocalBuf == '\n' )|| (*LocalBuf == '\r')) {
-	        break;
+  if(LocalBuf != NULL) {
+	for (i = 0; i < nbytes; i++) {
+		numbytes++;
+		*(LocalBuf + i) = inbyte();
+		if ((*(LocalBuf + i) == '\n' )|| (*(LocalBuf + i) == '\r')) {
+			break;
 		}
 	}
-	if(LocalBuf != NULL) {
-	LocalBuf -= i;
-	}
   }
 
-  return (i + 1);
+  return numbytes;
 #else
   (void)fd;
   (void)buf;
@@ -86,25 +79,21 @@ _read (s32 fd, char8* buf, s32 nbytes)
 {
 #ifdef STDIN_BASEADDRESS
   s32 i;
+  s32 numbytes = 0;
   char8* LocalBuf = buf;
 
   (void)fd;
-  for (i = 0; i < nbytes; i++) {
-	if(LocalBuf != NULL) {
-		LocalBuf += i;
-	}
-	if(LocalBuf != NULL) {
-	    *LocalBuf = inbyte();
-	    if ((*LocalBuf == '\n' )|| (*LocalBuf == '\r')) {
-	        break;
+  if(LocalBuf != NULL) {
+	for (i = 0; i < nbytes; i++) {
+		numbytes++;
+		*(LocalBuf + i) = inbyte();
+		if ((*(LocalBuf + i) == '\n' )|| (*(LocalBuf + i) == '\r')) {
+			break;
 		}
 	}
-	if(LocalBuf != NULL) {
-	LocalBuf -= i;
-	}
   }
 
-  return (i + 1);
+  return numbytes;
 #else
   (void)fd;
   (void)buf;
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/sbrk.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sbrk.c
index 7f94fabb4..64d5156af 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/sbrk.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sbrk.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/sleep.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sleep.c
index 508b30f61..74c7ec215 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/sleep.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sleep.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -49,6 +49,7 @@
 *						  disabling the interrupt
 * 5.04	pkp		 03/11/16 Compare the counter value to previously read value
 *						  to detect the overflow for TTC3
+* 6.0   asa      08/15/16 Updated the sleep signature. Fix for CR#956899.
 * </pre>
 *
 ******************************************************************************/
@@ -79,7 +80,7 @@
 *
 ****************************************************************************/
 
-s32 sleep(u32 seconds)
+unsigned sleep(unsigned int seconds)
 {
 #ifdef SLEEP_TIMER_BASEADDR
 	u64 tEnd;
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/sleep.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sleep.h
index 9b49173c6..27add6605 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/sleep.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sleep.h
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -29,18 +29,19 @@
 * this Software without prior written authorization from Xilinx.
 *
 ******************************************************************************/
+
 #ifndef SLEEP_H
 #define SLEEP_H
 
+#include "xil_types.h"
+#include "xil_io.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include "xil_types.h"
-#include "xil_io.h"
-
-s32 usleep(u32 useconds);
-s32 sleep(u32 seconds);
+int usleep(unsigned long useconds);
+unsigned sleep(unsigned int seconds);
 
 #ifdef __cplusplus
 }
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/uart.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/uart.c
index bff3ed24f..bff3ed24f 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/uart.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/uart.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/unlink.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/unlink.c
index 0c9f0f78e..84e44a47c 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/unlink.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/unlink.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/usleep.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/usleep.c
index afc9414bb..ff01dfd73 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/usleep.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/usleep.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -50,6 +50,7 @@
 *						  disabling the interrupt
 * 5.04	pkp		 03/11/16 Compare the counter value to previously read value
 *						  to detect the overflow for TTC3
+* 6.0   asa      08/15/16 Updated the usleep signature. Fix for CR#956899.
 * </pre>
 *
 ******************************************************************************/
@@ -83,7 +84,7 @@
 *
 ****************************************************************************/
 
-s32 usleep(u32 useconds)
+int usleep(unsigned long useconds)
 {
 
 #ifdef SLEEP_TIMER_BASEADDR
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/vectors.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/vectors.c
index 73162672f..0a3616328 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/vectors.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/vectors.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2016 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -33,14 +33,17 @@
 /**
 * @file vectors.c
 *
-* This file contains the C level vectors for the ARM Cortex R5 core.
+* This file contains the C level vectors for the ARM Cortex A9 core.
 *
 * <pre>
 * MODIFICATION HISTORY:
 *
 * Ver   Who  Date     Changes
 * ----- ---- -------- ---------------------------------------------------
-* 5.00 	pkp  02/20/14 First release
+* 1.00a ecm  10/20/09 Initial version, moved over from bsp area
+* 6.0   mus  27/07/16 Consolidated vectors for a53,a9 and r5 processor
+*                     and added UndefinedException for a53 32 bit and r5
+*                     processor
 * </pre>
 *
 * @note
@@ -71,7 +74,6 @@ extern XExc_VectorTableEntry XExc_VectorTable[];
 /************************** Function Prototypes ******************************/
 
 
-
 /*****************************************************************************/
 /**
 *
@@ -110,6 +112,26 @@ void IRQInterrupt(void)
 					XIL_EXCEPTION_ID_IRQ_INT].Data);
 }
 
+#if !defined (__aarch64__)
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the Undefined exception called from the
+* vectors.s file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void UndefinedException(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_UNDEFINED_INT].Handler(XExc_VectorTable[
+					XIL_EXCEPTION_ID_UNDEFINED_INT].Data);
+}
+
 /*****************************************************************************/
 /**
 *
@@ -166,3 +188,44 @@ void PrefetchAbortInterrupt(void)
 	XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Handler(
 		XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Data);
 }
+#else
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the Synchronous Interrupt called from the vectors.s
+* file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void SynchronousInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_SYNC_INT].Handler(XExc_VectorTable[
+					XIL_EXCEPTION_ID_SYNC_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the SError Interrupt called from the
+* vectors.s file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void SErrorInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Handler(
+		XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Data);
+}
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/vectors.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/vectors.h
index ad4d8ece3..bb599b560 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/vectors.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/vectors.h
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2016 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -33,14 +33,15 @@
 /**
 * @file vectors.h
 *
-* This file contains the C level vector prototypes for the ARM Cortex R5 core.
+* This file contains the C level vector prototypes for the ARM Cortex A9 core.
 *
 * <pre>
 * MODIFICATION HISTORY:
 *
 * Ver   Who  Date     Changes
 * ----- ---- -------- ---------------------------------------------------
-* 5.00 	pkp  02/20/14 First release
+* 1.00a ecm  10/20/10 Initial version, moved over from bsp area
+* 6.0   mus  07/27/16 Consolidated vectors for a9,a53 and r5 processors
 * </pre>
 *
 * @note
@@ -49,8 +50,8 @@
 *
 ******************************************************************************/
 
-#ifndef VECTORS_H_
-#define VECTORS_H_
+#ifndef _VECTORS_H_
+#define _VECTORS_H_
 
 /***************************** Include Files *********************************/
 
@@ -67,12 +68,18 @@ extern "C" {
 /************************** Constant Definitions *****************************/
 
 /************************** Function Prototypes ******************************/
+
 void FIQInterrupt(void);
 void IRQInterrupt(void);
+#if !defined (__aarch64__)
 void SWInterrupt(void);
 void DataAbortInterrupt(void);
 void PrefetchAbortInterrupt(void);
-
+void UndefinedException(void);
+#else
+void SynchronousInterrupt(void);
+void SErrorInterrupt(void);
+#endif
 
 #ifdef __cplusplus
 }
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/write.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/write.c
index 4ae96c29f..aaa879e73 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/write.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/write.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -30,19 +30,15 @@
 *
 ******************************************************************************/
 
-/* Use toolchain function for openamp applications*/
-
-#ifndef UNDEFINE_FILE_OPS
-
 /* write.c -- write bytes to an output device.
  */
-
-#include "xparameters.h"
+#ifndef UNDEFINE_FILE_OPS
 #include "xil_printf.h"
+#include "xparameters.h"
 
 #ifdef __cplusplus
 extern "C" {
-	__attribute__((weak)) s32 _write (s32 fd, char8* buf, s32 nbytes);
+	__attribute__((weak)) sint32 _write (sint32 fd, char8* buf, sint32 nbytes);
 }
 #endif
 
@@ -51,8 +47,8 @@ extern "C" {
  *          stdout and stderr are the same. Since we have no filesystem,
  *          open will only return an error.
  */
-__attribute__((weak)) s32
-write (s32 fd, char8* buf, s32 nbytes)
+__attribute__((weak)) sint32
+write (sint32 fd, char8* buf, sint32 nbytes)
 
 {
 #ifdef STDOUT_BASEADDRESS
@@ -83,8 +79,8 @@ write (s32 fd, char8* buf, s32 nbytes)
 #endif
 }
 
-__attribute__((weak)) s32
-_write (s32 fd, char8* buf, s32 nbytes)
+__attribute__((weak)) sint32
+_write (sint32 fd, char8* buf, sint32 nbytes)
 {
 #ifdef STDOUT_BASEADDRESS
   s32 i;
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xbasic_types.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xbasic_types.h
index 787212ca7..787212ca7 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xbasic_types.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xbasic_types.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xdebug.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xdebug.h
index 650946bd0..650946bd0 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xdebug.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xdebug.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xenv.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xenv.h
index 3d97bebd4..3d97bebd4 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xenv.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xenv.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xenv_standalone.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xenv_standalone.h
index f18601874..f18601874 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xenv_standalone.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xenv_standalone.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil-crt0.S b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil-crt0.S
index cca2f0d69..6715a6ce5 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil-crt0.S
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil-crt0.S
@@ -70,11 +70,30 @@
 .Lstack:
 	.long	__stack
 
+.set RPU_0_PWRCTL,	0xFF9A0108
+.set RPU_1_PWRCTL,	0xFF9A0208
+.set MPIDR_AFF0,	0xFF
+.set PWRCTL_MASK,	0x1
 
 	.globl	_startup
 
 _startup:
 	bl      __cpu_init		/* Initialize the CPU first (BSP provides this) */
+	mrc	p15, 0, r0,  c0,  c0, 5	/* Read MPIDR register */
+	ands	r0, r0, #MPIDR_AFF0	/* Get affinity level 0 */
+	bne	core1
+	ldr	r10, =RPU_0_PWRCTL	/* Load PWRCTRL address for core 0 */
+	b	test_boot_status
+
+core1:
+	ldr	r10, =RPU_1_PWRCTL	/* Load PWRCTRL address for core 1 */
+
+test_boot_status:
+	ldr	r11, [r10]		/* Read PWRCTRL register */
+	ands	r11, r11, #PWRCTL_MASK	/* Extract and test core's PWRCTRL */
+
+	/* if warm reset, skip the clearing of BSS and SBSS */
+	bne	.Lenclbss
 
 	mov	r0, #0
 
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_assert.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_assert.c
index 42db07deb..3087fe80f 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_assert.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_assert.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -42,6 +42,7 @@
 * Ver   Who    Date   Changes
 * ----- ---- -------- -------------------------------------------------------
 * 1.00a hbm  07/14/09 Initial release
+* 6.0   kvn  05/31/16 Make Xil_AsserWait a global variable
 * </pre>
 *
 ******************************************************************************/
@@ -71,7 +72,7 @@ u32 Xil_AssertStatus;
  * such that it does not wait infinitely. Use the debugger to disable the
  * waiting during testing of asserts.
  */
-/*s32 Xil_AssertWait = 1*/
+s32 Xil_AssertWait = 1;
 
 /* The callback function to be invoked when an assert is taken */
 static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL;
@@ -95,7 +96,6 @@ static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL;
 ******************************************************************************/
 void Xil_Assert(const char8 *File, s32 Line)
 {
-	s32 Xil_AssertWait = 1;
 	/* if the callback has been set then invoke it */
 	if (Xil_AssertCallbackRoutine != 0) {
 		(*Xil_AssertCallbackRoutine)(File, Line);
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_assert.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_assert.h
index 7034bc9ad..1e3c17b50 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_assert.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_assert.h
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -42,6 +42,7 @@
 * Ver   Who    Date   Changes
 * ----- ---- -------- -------------------------------------------------------
 * 1.00a hbm  07/14/09 First release
+* 6.0   kvn  05/31/16 Make Xil_AsserWait a global variable
 * </pre>
 *
 ******************************************************************************/
@@ -66,6 +67,7 @@ extern "C" {
 #define XNULL NULL
 
 extern u32 Xil_AssertStatus;
+extern s32 Xil_AssertWait;
 extern void Xil_Assert(const char8 *File, s32 Line);
 void XNullHandler(void *NullParameter);
 
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_cache.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_cache.c
index 2ba080dff..2ba080dff 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_cache.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_cache.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_cache.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_cache.h
index 581db3f16..581db3f16 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_cache.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_cache.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_cache_vxworks.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_cache_vxworks.h
index 6e8cfa75f..6e8cfa75f 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_cache_vxworks.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_cache_vxworks.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_exception.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_exception.c
index f41976eec..66f722d92 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_exception.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_exception.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2015 - 2016 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -34,7 +34,7 @@
 *
 * @file xil_exception.c
 *
-* This file contains low-level driver functions for the Cortex R5 exception
+* This file contains low-level driver functions for the Cortex A53,A9,R5 exception
 * Handler.
 *
 * <pre>
@@ -42,8 +42,10 @@
 *
 * Ver   Who      Date     Changes
 * ----- -------- -------- -----------------------------------------------
-* 5.00 	pkp  	 02/20/14 First release
-*
+* 5.2	pkp  	 28/05/15 First release
+* 6.0   mus      27/07/16 Consolidated exceptions for a53,a9 and r5
+*                         processors and added Xil_UndefinedExceptionHandler
+*                         for a53 32 bit and r5 as well.
 * </pre>
 *
 *****************************************************************************/
@@ -72,16 +74,34 @@ static void Xil_ExceptionNullHandler(void *Data);
 /*
  * Exception vector table to store handlers for each exception vector.
  */
+#if defined (__aarch64__)
+XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] =
+{
+        {Xil_ExceptionNullHandler, NULL},
+        {Xil_SyncAbortHandler, NULL},
+        {Xil_ExceptionNullHandler, NULL},
+        {Xil_ExceptionNullHandler, NULL},
+        {Xil_SErrorAbortHandler, NULL},
+
+};
+#else
 XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] =
 {
 	{Xil_ExceptionNullHandler, NULL},
-	{Xil_ExceptionNullHandler, NULL},
+	{Xil_UndefinedExceptionHandler, NULL},
 	{Xil_ExceptionNullHandler, NULL},
 	{Xil_PrefetchAbortHandler, NULL},
 	{Xil_DataAbortHandler, NULL},
 	{Xil_ExceptionNullHandler, NULL},
 	{Xil_ExceptionNullHandler, NULL},
 };
+#endif
+#if !defined (__aarch64__)
+u32 DataAbortAddr;       /* Address of instruction causing data abort */
+u32 PrefetchAbortAddr;   /* Address of instruction causing prefetch abort */
+u32 UndefinedExceptionAddr;   /* Address of instruction causing Undefined
+							     exception */
+#endif
 
 /*****************************************************************************/
 
@@ -109,9 +129,12 @@ DieLoop: goto DieLoop;
 /****************************************************************************/
 /**
 * The function is a common API used to initialize exception handlers across all
-* processors supported. For ARM CortexR5, the exception handlers are being
+* processors supported. For ARM CortexA53,R5,A9, the exception handlers are being
 * initialized statically and hence this function does not do anything.
-*
+* However, it is still present to avoid any compilation issues in case an
+* application uses this API and also to take care of backward compatibility
+* issues (in earlier versions of BSPs, this API was being used to initialize
+* exception handlers).
 *
 * @param	None.
 *
@@ -174,12 +197,55 @@ void Xil_ExceptionRemoveHandler(u32 Exception_id)
 				       Xil_ExceptionNullHandler,
 				       NULL);
 }
+
+#if defined (__aarch64__)
+/*****************************************************************************/
+/**
+*
+* Default Synchronous abort handler which prints a debug message on console if
+* Debug flag is enabled
+*
+* @param        None
+*
+* @return       None.
+*
+* @note         None.
+*
+****************************************************************************/
+
+void Xil_SyncAbortHandler(void *CallBackRef){
+	xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n");
+	while(1) {
+		;
+	}
+}
+
 /*****************************************************************************/
 /**
 *
-* Default Data abort handler which prints a debug message on console if
+* Default SError abort handler which prints a debug message on console if
 * Debug flag is enabled
 *
+* @param        None
+*
+* @return       None.
+*
+* @note         None.
+*
+****************************************************************************/
+void Xil_SErrorAbortHandler(void *CallBackRef){
+	xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n");
+	while(1) {
+		;
+	}
+}
+#else
+/*****************************************************************************/
+/**
+*
+* Default Data abort handler which prints data fault status register through
+* which information about data fault can be acquired
+*
 * @param	None
 *
 * @return	None.
@@ -189,8 +255,21 @@ void Xil_ExceptionRemoveHandler(u32 Exception_id)
 ****************************************************************************/
 
 void Xil_DataAbortHandler(void *CallBackRef){
+#ifdef DEBUG
+	u32 FaultStatus;
 
-	xdbg_printf(XDBG_DEBUG_ERROR, "Data abort \n");
+        xdbg_printf(XDBG_DEBUG_ERROR, "Data abort \n");
+        #ifdef __GNUC__
+	FaultStatus = mfcp(XREG_CP15_DATA_FAULT_STATUS);
+	    #elif defined (__ICCARM__)
+	        mfcp(XREG_CP15_DATA_FAULT_STATUS,FaultStatus);
+	    #else
+	        { volatile register u32 Reg __asm(XREG_CP15_DATA_FAULT_STATUS);
+	        FaultStatus = Reg; }
+	    #endif
+	xdbg_printf(XDBG_DEBUG_GENERAL, "Data abort with Data Fault Status Register  %x\n",FaultStatus);
+	xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instrcution causing Data abort %x\n",DataAbortAddr);
+#endif
 	while(1) {
 		;
 	}
@@ -199,8 +278,8 @@ void Xil_DataAbortHandler(void *CallBackRef){
 /*****************************************************************************/
 /**
 *
-* Default Prefetch abort handler which printsa debug message on console if
-* Debug flag is enabled
+* Default Prefetch abort handler which prints prefetch fault status register through
+* which information about instruction prefetch fault can be acquired
 *
 * @param	None
 *
@@ -210,9 +289,43 @@ void Xil_DataAbortHandler(void *CallBackRef){
 *
 ****************************************************************************/
 void Xil_PrefetchAbortHandler(void *CallBackRef){
+#ifdef DEBUG
+	u32 FaultStatus;
+
+    xdbg_printf(XDBG_DEBUG_ERROR, "Prefetch abort \n");
+        #ifdef __GNUC__
+	FaultStatus = mfcp(XREG_CP15_INST_FAULT_STATUS);
+	    #elif defined (__ICCARM__)
+			mfcp(XREG_CP15_INST_FAULT_STATUS,FaultStatus);
+	    #else
+			{ volatile register u32 Reg __asm(XREG_CP15_INST_FAULT_STATUS);
+			FaultStatus = Reg; }
+		#endif
+	xdbg_printf(XDBG_DEBUG_GENERAL, "Prefetch abort with Instruction Fault Status Register  %x\n",FaultStatus);
+	xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instrcution causing Prefetch abort %x\n",PrefetchAbortAddr);
+#endif
+	while(1) {
+		;
+	}
+}
+/*****************************************************************************/
+/**
+*
+* Default undefined exception handler which prints address of the undefined
+* instruction if debug prints are enabled
+*
+* @param	None
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_UndefinedExceptionHandler(void *CallBackRef){
 
-	xdbg_printf(XDBG_DEBUG_ERROR, "Prefetch abort \n");
+	xdbg_printf(XDBG_DEBUG_GENERAL, "Address of the undefined instruction %x\n",UndefinedExceptionAddr);
 	while(1) {
 		;
 	}
 }
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_exception.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_exception.h
index 9d903175c..434ef2a6a 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_exception.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_exception.h
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2015 - 2016 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -34,7 +34,7 @@
 *
 * @file xil_exception.h
 *
-* This header file contains ARM Cortex R5 specific exception related APIs.
+* This header file contains ARM Cortex A53,A9,R5 specific exception related APIs.
 * For exception related functions that can be used across all Xilinx supported
 * processors, please use xil_exception.h.
 *
@@ -43,7 +43,8 @@
 *
 * Ver   Who      Date     Changes
 * ----- -------- -------- -----------------------------------------------
-* 5.00 	pkp  02/20/14 First release
+* 5.2	pkp  	 28/05/15 First release
+* 6.0   mus      27/07/16 Consolidated file for a53,a9 and r5 processors
 * </pre>
 *
 ******************************************************************************/
@@ -67,6 +68,13 @@ extern "C" {
 #define XIL_EXCEPTION_ALL	(XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
 
 #define XIL_EXCEPTION_ID_FIRST			0U
+#if defined (__aarch64__)
+#define XIL_EXCEPTION_ID_SYNC_INT		1U
+#define XIL_EXCEPTION_ID_IRQ_INT		2U
+#define XIL_EXCEPTION_ID_FIQ_INT		3U
+#define XIL_EXCEPTION_ID_SERROR_ABORT_INT		4U
+#define XIL_EXCEPTION_ID_LAST			5U
+#else
 #define XIL_EXCEPTION_ID_RESET			0U
 #define XIL_EXCEPTION_ID_UNDEFINED_INT		1U
 #define XIL_EXCEPTION_ID_SWI_INT		2U
@@ -75,6 +83,7 @@ extern "C" {
 #define XIL_EXCEPTION_ID_IRQ_INT		5U
 #define XIL_EXCEPTION_ID_FIQ_INT		6U
 #define XIL_EXCEPTION_ID_LAST			6U
+#endif
 
 /*
  * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
@@ -103,10 +112,16 @@ typedef void (*Xil_InterruptHandler)(void *data);
 *		C-Style signature: void Xil_ExceptionEnableMask(Mask)
 *
 ******************************************************************************/
+#if defined (__GNUC__) || defined (__ICCARM__)
 #define Xil_ExceptionEnableMask(Mask)	\
 		mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))
-
-
+#else
+#define Xil_ExceptionEnableMask(Mask)	\
+		{								\
+		  register u32 Reg __asm("cpsr"); \
+		  mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \
+		}
+#endif
 /****************************************************************************/
 /**
 * Enable the IRQ exception.
@@ -131,9 +146,16 @@ typedef void (*Xil_InterruptHandler)(void *data);
 *		C-Style signature: Xil_ExceptionDisableMask(Mask)
 *
 ******************************************************************************/
+#if defined (__GNUC__) || defined (__ICCARM__)
 #define Xil_ExceptionDisableMask(Mask)	\
 		mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL))
-
+#else
+#define Xil_ExceptionDisableMask(Mask)	\
+		{									\
+		  register u32 Reg __asm("cpsr"); \
+		  mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \
+		}
+#endif
 /****************************************************************************/
 /**
 * Disable the IRQ exception.
@@ -146,6 +168,7 @@ typedef void (*Xil_InterruptHandler)(void *data);
 #define Xil_ExceptionDisable() \
 		Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
 
+#if !defined (__aarch64__) && !defined (ARMA53_32)
 /****************************************************************************/
 /**
 * Enable nested interrupts by clearing the I and F bits it CPSR
@@ -166,6 +189,7 @@ typedef void (*Xil_InterruptHandler)(void *data);
 *			eventual crash (all the stack space getting consumed).
 ******************************************************************************/
 #define Xil_EnableNestedInterrupts() \
+		__asm__ __volatile__ ("stmfd   sp!, {lr}"); \
 		__asm__ __volatile__ ("mrs     lr, spsr");  \
 		__asm__ __volatile__ ("stmfd   sp!, {lr}"); \
 		__asm__ __volatile__ ("msr     cpsr_c, #0x1F"); \
@@ -190,8 +214,10 @@ typedef void (*Xil_InterruptHandler)(void *data);
 		__asm__ __volatile__ ("ldmfd   sp!, {lr}");   \
 		__asm__ __volatile__ ("msr     cpsr_c, #0x92"); \
 		__asm__ __volatile__ ("ldmfd   sp!, {lr}"); \
-		__asm__ __volatile__ ("msr     spsr_cxsf, lr");
+		__asm__ __volatile__ ("msr     spsr_cxsf, lr"); \
+		__asm__ __volatile__ ("ldmfd   sp!, {lr}"); \
 
+#endif
 /************************** Variable Definitions ****************************/
 
 /************************** Function Prototypes *****************************/
@@ -203,10 +229,14 @@ extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
 extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
 
 extern void Xil_ExceptionInit(void);
-
+#if defined (__aarch64__)
+void Xil_SyncAbortHandler(void *CallBackRef);
+void Xil_SErrorAbortHandler(void *CallBackRef);
+#else
 extern void Xil_DataAbortHandler(void *CallBackRef);
-
 extern void Xil_PrefetchAbortHandler(void *CallBackRef);
+extern void Xil_UndefinedExceptionHandler(void *CallBackRef);
+#endif
 
 #ifdef __cplusplus
 }
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_hal.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_hal.h
index d4434d07f..d4434d07f 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_hal.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_hal.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_io.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_io.c
new file mode 100644
index 000000000..31de05581
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_io.c
@@ -0,0 +1,107 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_io.c
+*
+* Contains I/O functions for memory-mapped or non-memory-mapped I/O
+* architectures.  These functions encapsulate Cortex A53 architecture-specific
+* I/O requirements.
+*
+* @note
+*
+* This file contains architecture-dependent code.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 05/29/14 First release
+* </pre>
+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+#include "xil_io.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/*****************************************************************************/
+/**
+*
+* Perform a 16-bit endian converion.
+*
+* @param	Data contains the value to be converted.
+*
+* @return	converted value.
+*
+* @note		None.
+*
+******************************************************************************/
+u16 Xil_EndianSwap16(u16 Data)
+{
+	return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U));
+}
+
+/*****************************************************************************/
+/**
+*
+* Perform a 32-bit endian converion.
+*
+* @param	Data contains the value to be converted.
+*
+* @return	converted value.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 Xil_EndianSwap32(u32 Data)
+{
+	u16 LoWord;
+	u16 HiWord;
+
+	/* get each of the half words from the 32 bit word */
+
+	LoWord = (u16) (Data & 0x0000FFFFU);
+	HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U);
+
+	/* byte swap each of the 16 bit half words */
+
+	LoWord = (((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U));
+	HiWord = (((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U));
+
+	/* swap the half words before returning the value */
+
+	return ((((u32)LoWord) << (u32)16U) | (u32)HiWord);
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_io.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_io.h
index 90fd22559..06d89dcc3 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_io.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_io.h
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -32,40 +32,69 @@
 /*****************************************************************************/
 /**
 *
-* @file xil_io.c
+* @file xil_io.h
 *
-* Contains I/O functions for memory-mapped or non-memory-mapped I/O
-* architectures.  These functions encapsulate Cortex R5 architecture-specific
-* I/O requirements.
+* This file contains the interface for the general IO component, which
+* encapsulates the Input/Output functions for processors that do not
+* require any special I/O handling.
 *
-* @note
-*
-* This file contains architecture-dependent code.
 *
 * <pre>
 * MODIFICATION HISTORY:
 *
 * Ver   Who      Date     Changes
 * ----- -------- -------- -----------------------------------------------
-* 5.00 	pkp  	 02/20/14 First release
+* 5.00 	pkp  	 05/29/14 First release
+* 6.00  mus      08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for
+*                         ARM processors
 * </pre>
 ******************************************************************************/
 
+#ifndef XIL_IO_H           /* prevent circular inclusions */
+#define XIL_IO_H           /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
 
 /***************************** Include Files *********************************/
-#include "xil_io.h"
+
 #include "xil_types.h"
-#include "xil_assert.h"
-#include "xpseudo_asm.h"
-#include "xreg_cortexr5.h"
+#include "xil_printf.h"
 
-/************************** Constant Definitions *****************************/
+#if defined (__MICROBLAZE__)
+#include "mb_interface.h"
+#else
+#include "xpseudo_asm.h"
+#endif
 
-/**************************** Type Definitions *******************************/
+/************************** Function Prototypes ******************************/
+u16 Xil_EndianSwap16(u16 Data);
+u32 Xil_EndianSwap32(u32 Data);
 
 /***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
+#if defined __GNUC__
+#if defined (__MICROBLAZE__)
+#  define INST_SYNC		mbar(0)
+#  define DATA_SYNC		mbar(1)
+# else
+#  define SYNCHRONIZE_IO	dmb()
+#  define INST_SYNC		isb()
+#  define DATA_SYNC		dsb()
+# endif
+#else
+# define SYNCHRONIZE_IO
+# define INST_SYNC
+# define DATA_SYNC
+# define INST_SYNC
+# define DATA_SYNC
+#endif
+
+#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__)
+#define INLINE inline
+#else
+#define INLINE __inline
+#endif
 
 /*****************************************************************************/
 /**
@@ -81,7 +110,7 @@
 * @note		None.
 *
 ******************************************************************************/
-u8 Xil_In8(INTPTR Addr)
+static INLINE u8 Xil_In8(UINTPTR Addr)
 {
 	return *(volatile u8 *) Addr;
 }
@@ -100,7 +129,7 @@ u8 Xil_In8(INTPTR Addr)
 * @note		None.
 *
 ******************************************************************************/
-u16 Xil_In16(INTPTR Addr)
+static INLINE u16 Xil_In16(UINTPTR Addr)
 {
 	return *(volatile u16 *) Addr;
 }
@@ -119,7 +148,7 @@ u16 Xil_In16(INTPTR Addr)
 * @note		None.
 *
 ******************************************************************************/
-u32 Xil_In32(INTPTR Addr)
+static INLINE u32 Xil_In32(UINTPTR Addr)
 {
 	return *(volatile u32 *) Addr;
 }
@@ -127,10 +156,10 @@ u32 Xil_In32(INTPTR Addr)
 /*****************************************************************************/
 /**
 *
-* Performs an output operation for an 8-bit memory location by writing the
+* Performs an input operation for a 64-bit memory location by reading the
 * specified Value to the the specified address.
 *
-* @param	Addr contains the address to perform the output operation
+* @param	OutAddress contains the address to perform the output operation
 *		at.
 * @param	Value contains the Value to be output at the specified address.
 *
@@ -139,16 +168,15 @@ u32 Xil_In32(INTPTR Addr)
 * @note		None.
 *
 ******************************************************************************/
-void Xil_Out8(INTPTR Addr, u8 Value)
+static INLINE u64 Xil_In64(UINTPTR Addr)
 {
-	volatile u8 *LocalAddr = (u8 *)Addr;
-	*LocalAddr = Value;
+	return *(volatile u64 *) Addr;
 }
 
 /*****************************************************************************/
 /**
 *
-* Performs an output operation for a 16-bit memory location by writing the
+* Performs an output operation for an 8-bit memory location by writing the
 * specified Value to the the specified address.
 *
 * @param	Addr contains the address to perform the output operation
@@ -160,16 +188,16 @@ void Xil_Out8(INTPTR Addr, u8 Value)
 * @note		None.
 *
 ******************************************************************************/
-void Xil_Out16(INTPTR Addr, u16 Value)
+static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
 {
-	volatile u16 *LocalAddr = (u16 *)Addr;
+	volatile u8 *LocalAddr = (volatile u8 *)Addr;
 	*LocalAddr = Value;
 }
 
 /*****************************************************************************/
 /**
 *
-* Performs an output operation for a 32-bit memory location by writing the
+* Performs an output operation for a 16-bit memory location by writing the
 * specified Value to the the specified address.
 *
 * @param	Addr contains the address to perform the output operation
@@ -181,15 +209,16 @@ void Xil_Out16(INTPTR Addr, u16 Value)
 * @note		None.
 *
 ******************************************************************************/
-void Xil_Out32(INTPTR Addr, u32 Value)
+static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
 {
-	volatile u32 *LocalAddr = (u32 *)Addr;
+	volatile u16 *LocalAddr = (volatile u16 *)Addr;
 	*LocalAddr = Value;
 }
+
 /*****************************************************************************/
 /**
 *
-* Performs an output operation for a 64-bit memory location by writing the
+* Performs an output operation for a 32-bit memory location by writing the
 * specified Value to the the specified address.
 *
 * @param	Addr contains the address to perform the output operation
@@ -201,16 +230,16 @@ void Xil_Out32(INTPTR Addr, u32 Value)
 * @note		None.
 *
 ******************************************************************************/
-void Xil_Out64(INTPTR Addr, u64 Value)
+static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
 {
-	volatile u64 *LocalAddr = (u64 *)Addr;
+	volatile u32 *LocalAddr = (volatile u32 *)Addr;
 	*LocalAddr = Value;
 }
 
 /*****************************************************************************/
 /**
 *
-* Performs an input operation for a 64-bit memory location by reading the
+* Performs an output operation for a 64-bit memory location by writing the
 * specified Value to the the specified address.
 *
 * @param	Addr contains the address to perform the output operation
@@ -222,159 +251,101 @@ void Xil_Out64(INTPTR Addr, u64 Value)
 * @note		None.
 *
 ******************************************************************************/
-u64 Xil_In64(INTPTR Addr)
-{
-	return *(volatile u64 *) Addr;
-}
-/*****************************************************************************/
-/**
-*
-* Performs an input operation for a 16-bit memory location by reading from the
-* specified address and returning the byte-swapped Value read from that
-* address.
-*
-* @param	Addr contains the address to perform the input operation
-*		at.
-*
-* @return	The byte-swapped Value read from the specified input address.
-*
-* @note		None.
-*
-******************************************************************************/
-u16 Xil_In16BE(INTPTR Addr)
+static INLINE void Xil_Out64(UINTPTR Addr, u64 Value)
 {
-	u16 temp;
-	u16 result;
-
-	temp = Xil_In16(Addr);
-
-	result = Xil_EndianSwap16(temp);
-
-	return result;
+	volatile u64 *LocalAddr = (volatile u64 *)Addr;
+	*LocalAddr = Value;
 }
 
-/*****************************************************************************/
-/**
-*
-* Performs an input operation for a 32-bit memory location by reading from the
-* specified address and returning the byte-swapped Value read from that
-* address.
-*
-* @param	Addr contains the address to perform the input operation
-*		at.
-*
-* @return	The byte-swapped Value read from the specified input address.
-*
-* @note		None.
-*
-******************************************************************************/
-u32 Xil_In32BE(INTPTR Addr)
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+# define Xil_In16LE	Xil_In16
+# define Xil_In32LE	Xil_In32
+# define Xil_Out16LE	Xil_Out16
+# define Xil_Out32LE	Xil_Out32
+# define Xil_Htons	Xil_EndianSwap16
+# define Xil_Htonl	Xil_EndianSwap32
+# define Xil_Ntohs	Xil_EndianSwap16
+# define Xil_Ntohl	Xil_EndianSwap32
+# else
+# define Xil_In16BE	Xil_In16
+# define Xil_In32BE	Xil_In32
+# define Xil_Out16BE	Xil_Out16
+# define Xil_Out32BE	Xil_Out32
+# define Xil_Htons(Data) (Data)
+# define Xil_Htonl(Data) (Data)
+# define Xil_Ntohs(Data) (Data)
+# define Xil_Ntohl(Data) (Data)
+#endif
+#else
+# define Xil_In16LE	Xil_In16
+# define Xil_In32LE	Xil_In32
+# define Xil_Out16LE	Xil_Out16
+# define Xil_Out32LE	Xil_Out32
+# define Xil_Htons	Xil_EndianSwap16
+# define Xil_Htonl	Xil_EndianSwap32
+# define Xil_Ntohs	Xil_EndianSwap16
+# define Xil_Ntohl	Xil_EndianSwap32
+#endif
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE u16 Xil_In16BE(UINTPTR Addr)
+#else
+static INLINE u16 Xil_In16LE(UINTPTR Addr)
+#endif
+#else
+static INLINE u16 Xil_In16BE(UINTPTR Addr)
+#endif
 {
-	u32 temp;
-	u32 result;
-
-	temp = Xil_In32(Addr);
-
-	result = Xil_EndianSwap32(temp);
-
-	return result;
+	u16 value = Xil_In16(Addr);
+	return Xil_EndianSwap16(value);
 }
 
-/*****************************************************************************/
-/**
-*
-* Performs an output operation for a 16-bit memory location by writing the
-* specified Value to the the specified address. The Value is byte-swapped
-* before being written.
-*
-* @param	OutAddress contains the address to perform the output operation
-*		at.
-* @param	Value contains the Value to be output at the specified address.
-*
-* @return	None.
-*
-* @note		None.
-*
-******************************************************************************/
-void Xil_Out16BE(INTPTR Addr, u16 Value)
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE u32 Xil_In32BE(UINTPTR Addr)
+#else
+static INLINE u32 Xil_In32LE(UINTPTR Addr)
+#endif
+#else
+static INLINE u32 Xil_In32BE(UINTPTR Addr)
+#endif
 {
-	u16 temp;
-
-	temp = Xil_EndianSwap16(Value);
-
-    Xil_Out16(Addr, temp);
+	u16 value = Xil_In32(Addr);
+	return Xil_EndianSwap32(value);
 }
 
-/*****************************************************************************/
-/**
-*
-* Performs an output operation for a 32-bit memory location by writing the
-* specified Value to the the specified address. The Value is byte-swapped
-* before being written.
-*
-* @param	OutAddress contains the address to perform the output operation
-*		at.
-* @param	Value contains the Value to be output at the specified address.
-*
-* @return	None.
-*
-* @note		None.
-*
-******************************************************************************/
-void Xil_Out32BE(INTPTR Addr, u32 Value)
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
+#else
+static INLINE void Xil_Out16LE(UINTPTR Addr, u16 Value)
+#endif
+#else
+static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
+#endif
 {
-	u32 temp;
-
-	temp = Xil_EndianSwap32(Value);
-
-    Xil_Out32(Addr, temp);
+	Value = Xil_EndianSwap16(Value);
+	Xil_Out16(Addr, Value);
 }
 
-/*****************************************************************************/
-/**
-*
-* Perform a 16-bit endian converion.
-*
-* @param	Data contains the value to be converted.
-*
-* @return	converted value.
-*
-* @note		None.
-*
-******************************************************************************/
-u16 Xil_EndianSwap16(u16 Data)
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
+#else
+static INLINE void Xil_Out32LE(UINTPTR Addr, u32 Value)
+#endif
+#else
+static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
+#endif
 {
-	return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U));
+	Value = Xil_EndianSwap32(Value);
+	Xil_Out32(Addr, Value);
 }
 
-/*****************************************************************************/
-/**
-*
-* Perform a 32-bit endian converion.
-*
-* @param	Data contains the value to be converted.
-*
-* @return	converted value.
-*
-* @note		None.
-*
-******************************************************************************/
-u32 Xil_EndianSwap32(u32 Data)
-{
-	u16 LoWord;
-	u16 HiWord;
-
-	/* get each of the half words from the 32 bit word */
-
-	LoWord = (u16) (Data & 0x0000FFFFU);
-	HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U);
-
-	/* byte swap each of the 16 bit half words */
-
-	LoWord = (((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U));
-	HiWord = (((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U));
-
-	/* swap the half words before returning the value */
-
-	return ((((u32)LoWord) << 16U) | (u32)HiWord);
+#ifdef __cplusplus
 }
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_macroback.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_macroback.h
index ebafde87d..ebafde87d 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_macroback.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_macroback.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_mmu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_mmu.h
index 8e43e8227..8e43e8227 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_mmu.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_mmu.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_mpu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_mpu.c
index 7c028c515..7c028c515 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_mpu.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_mpu.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_mpu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_mpu.h
index a55be916e..a55be916e 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_mpu.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_mpu.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_printf.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_printf.c
index 0f0db4fc9..9dffed148 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_printf.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_printf.c
@@ -93,7 +93,6 @@ static void outs(const charptr lp, struct params_s *par)
 
 static void outnum( const s32 n, const s32 base, struct params_s *par)
 {
-    charptr cp;
     s32 negative;
 	s32 i;
     char8 outbuf[32];
@@ -141,7 +140,61 @@ static void outnum( const s32 n, const s32 base, struct params_s *par)
 }
     padding( par->left_flag, par);
 }
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine moves a 64-bit number to the output  */
+/* buffer as directed by the padding and positioning */
+/* flags. 											 */
+/*                                                   */
+#if defined (__aarch64__)
+static void outnum1( const s64 n, const s32 base, params_t *par)
+{
+    s32 negative;
+	s32 i;
+    char8 outbuf[64];
+    const char8 digits[] = "0123456789ABCDEF";
+    u64 num;
+    for(i = 0; i<64; i++) {
+	outbuf[i] = '0';
+    }
 
+    /* Check if number is negative                   */
+    if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) {
+        negative = 1;
+		num =(-(n));
+    }
+    else{
+        num = (n);
+        negative = 0;
+    }
+
+    /* Build number (backwards) in outbuf            */
+    i = 0;
+    do {
+		outbuf[i] = digits[(num % base)];
+		i++;
+		num /= base;
+    } while (num > 0);
+
+    if (negative != 0) {
+		outbuf[i] = '-';
+		i++;
+	}
+
+    outbuf[i] = 0;
+    i--;
+
+    /* Move the converted number to the buffer and   */
+    /* add in the padding where needed.              */
+    par->len = (s32)strlen(outbuf);
+    padding( !(par->left_flag), par);
+    while (&outbuf[i] >= outbuf) {
+	outbyte( outbuf[i] );
+		i--;
+}
+    padding( par->left_flag, par);
+}
+#endif
 /*---------------------------------------------------*/
 /*                                                   */
 /* This routine gets a number from the format        */
@@ -189,7 +242,9 @@ static s32 getnum( charptr* linep)
 void xil_printf( const char8 *ctrl1, ...)
 {
 	s32 Check;
+#if defined (__aarch64__)
     s32 long_flag;
+#endif
     s32 dot_flag;
 
     params_t par;
@@ -214,7 +269,9 @@ void xil_printf( const char8 *ctrl1, ...)
 
         /* initialize all the flags for this format.   */
         dot_flag = 0;
+#if defined (__aarch64__)
 		long_flag = 0;
+#endif
         par.unsigned_flag = 0;
 		par.left_flag = 0;
 		par.do_padding = 0;
@@ -272,7 +329,9 @@ void xil_printf( const char8 *ctrl1, ...)
                 break;
 
             case 'l':
+            #if defined (__aarch64__)
                 long_flag = 1;
+            #endif
                 Check = 0;
                 break;
 
@@ -281,19 +340,38 @@ void xil_printf( const char8 *ctrl1, ...)
                 /* fall through */
             case 'i':
             case 'd':
-                if ((long_flag != 0) || (ch == 'D')) {
-                    outnum( va_arg(argp, s32), 10L, &par);
+                #if defined (__aarch64__)
+                if (long_flag != 0){
+			        outnum1((s64)va_arg(argp, s64), 10L, &par);
                 }
                 else {
                     outnum( va_arg(argp, s32), 10L, &par);
                 }
+                #else
+                    outnum( va_arg(argp, s32), 10L, &par);
+                #endif
 				Check = 1;
                 break;
             case 'p':
+                #if defined (__aarch64__)
+                par.unsigned_flag = 1;
+			    outnum1((s64)va_arg(argp, s64), 16L, &par);
+			    Check = 1;
+                break;
+                #endif
             case 'X':
             case 'x':
                 par.unsigned_flag = 1;
+                #if defined (__aarch64__)
+                if (long_flag != 0) {
+				    outnum1((s64)va_arg(argp, s64), 16L, &par);
+				}
+				else {
+				    outnum((s32)va_arg(argp, s32), 16L, &par);
+                }
+                #else
                 outnum((s32)va_arg(argp, s32), 16L, &par);
+                #endif
                 Check = 1;
                 break;
 
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_printf.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_printf.h
index 2be5c5734..2be5c5734 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_printf.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_printf.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testcache.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testcache.c
index a2c4b0bbf..a2c4b0bbf 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testcache.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testcache.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testcache.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testcache.h
index b3c416cd0..b3c416cd0 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testcache.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testcache.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testio.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testio.c
index a68d7652f..a68d7652f 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testio.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testio.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testio.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testio.h
index fba0c1060..fba0c1060 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testio.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testio.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testmem.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testmem.c
index 19a3b6608..19a3b6608 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testmem.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testmem.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testmem.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testmem.h
index 4cbfd878b..4cbfd878b 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testmem.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testmem.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_types.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_types.h
index e8b78b7c6..e8b78b7c6 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_types.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_types.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xparameters_ps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xparameters_ps.h
index 91d6b6408..2f527c90a 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xparameters_ps.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xparameters_ps.h
@@ -42,6 +42,7 @@
 * Ver   Who     Date     Changes
 * ----- ------- -------- ---------------------------------------------------
 * 5.00  pkp  	02/29/14 Initial version
+* 6.0   mus     08/18/16 Defined ARMR5 flag
 * </pre>
 *
 * @note
@@ -53,6 +54,10 @@
 #ifndef XPARAMETERS_PS_H_
 #define XPARAMETERS_PS_H_
 
+#ifndef ARMR5
+#define ARMR5 ARMR5
+#endif
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -89,10 +94,9 @@ extern "C" {
 #define XPAR_XSDIOPS_0_INTR		XPS_SDIO0_INT_ID
 #define XPAR_XQSPIPS_0_INTR		XPS_QSPI_INT_ID
 #define XPAR_XSDIOPS_1_INTR		XPS_SDIO1_INT_ID
-#define XPAR_XWDTPS_0_INTR		XPS_WDT_INT_ID
+#define XPAR_XWDTPS_0_INTR		XPS_LPD_SWDT_INT_ID
+#define XPAR_XWDTPS_1_INTR		XPS_FPD_SWDT_INT_ID
 #define XPAR_XDCFG_0_INTR		XPS_DVC_INT_ID
-#define XPAR_SCUTIMER_INTR		XPS_SCU_TMR_INT_ID
-#define XPAR_SCUWDT_INTR		XPS_SCU_WDT_INT_ID
 #define XPAR_XTTCPS_0_INTR		XPS_TTC0_0_INT_ID
 #define XPAR_XTTCPS_1_INTR		XPS_TTC0_1_INT_ID
 #define XPAR_XTTCPS_2_INTR		XPS_TTC0_2_INT_ID
@@ -105,15 +109,6 @@ extern "C" {
 #define XPAR_XTTCPS_9_INTR		XPS_TTC3_0_INT_ID
 #define XPAR_XTTCPS_10_INTR		XPS_TTC3_1_INT_ID
 #define XPAR_XTTCPS_11_INTR		XPS_TTC3_2_INT_ID
-#define XPAR_XDMAPS_0_FAULT_INTR	XPS_DMA0_ABORT_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_0	XPS_DMA0_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_1	XPS_DMA1_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_2	XPS_DMA2_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_3	XPS_DMA3_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_4	XPS_DMA4_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_5	XPS_DMA5_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_6	XPS_DMA6_INT_ID
-#define XPAR_XDMAPS_0_DONE_INTR_7	XPS_DMA7_INT_ID
 #define XPAR_XNANDPS8_0_INTR        	XPS_NAND_INT_ID
 #define XPAR_XADMAPS_0_INTR 		XPS_ADMA_CH0_INT_ID
 #define XPAR_XADMAPS_1_INTR 		XPS_ADMA_CH1_INT_ID
@@ -166,28 +161,22 @@ extern "C" {
 
 
 /* Shared Peripheral Interrupts (SPI) */
-
-/* FIXME */
-/*#define XPS_FPGA0_INT_ID		100U */
-#define XPS_FPGA1_INT_ID		62U
-#define XPS_FPGA2_INT_ID		63U
-#define XPS_FPGA3_INT_ID		64U
-#define XPS_FPGA4_INT_ID		65U
-#define XPS_FPGA5_INT_ID		66U
-#define XPS_FPGA6_INT_ID		67U
-#define XPS_FPGA7_INT_ID		68U
-#define XPS_DMA4_INT_ID			72U
-#define XPS_DMA5_INT_ID			73U
-#define XPS_DMA6_INT_ID			74U
-#define XPS_DMA7_INT_ID			75U
-#define XPS_FPGA8_INT_ID		84U
-#define XPS_FPGA9_INT_ID		85U
-#define XPS_FPGA10_INT_ID		86U
-#define XPS_FPGA11_INT_ID		87U
-#define XPS_FPGA12_INT_ID		88U
-#define XPS_FPGA13_INT_ID		89U
-#define XPS_FPGA14_INT_ID		90U
-#define XPS_FPGA15_INT_ID		91U
+#define XPS_FPGA0_INT_ID		121U
+#define XPS_FPGA1_INT_ID		122U
+#define XPS_FPGA2_INT_ID		123U
+#define XPS_FPGA3_INT_ID		124U
+#define XPS_FPGA4_INT_ID		125U
+#define XPS_FPGA5_INT_ID		126U
+#define XPS_FPGA6_INT_ID		127U
+#define XPS_FPGA7_INT_ID		128U
+#define XPS_FPGA8_INT_ID		136U
+#define XPS_FPGA9_INT_ID		137U
+#define XPS_FPGA10_INT_ID		138U
+#define XPS_FPGA11_INT_ID		139U
+#define XPS_FPGA12_INT_ID		140U
+#define XPS_FPGA13_INT_ID		141U
+#define XPS_FPGA14_INT_ID		142U
+#define XPS_FPGA15_INT_ID		143U
 
 /* Updated Interrupt-IDs */
 #define XPS_OCMINTR_INT_ID		(10U + 32U)
@@ -204,7 +193,8 @@ extern "C" {
 #define XPS_CAN1_INT_ID			(24U + 32U)
 #define	XPS_RTC_ALARM_INT_ID 	(26U + 32U)
 #define	XPS_RTC_SEC_INT_ID	 	(27U + 32U)
-#define XPS_WDT_INT_ID			(52U + 32U)
+#define XPS_LPD_SWDT_INT_ID		(52U + 32U)
+#define XPS_FPD_SWDT_INT_ID		(113U + 32U)
 #define XPS_TTC0_0_INT_ID		(36U + 32U)
 #define XPS_TTC0_1_INT_ID		(37U + 32U)
 #define XPS_TTC0_2_INT_ID 		(38U + 32U)
@@ -257,33 +247,6 @@ extern "C" {
 #define XPS_APM5_INT_ID		(123U + 32U)
 
 /* REDEFINES for TEST APP */
-/* Definitions for UART */
-#define XPAR_PS7_UART_0_INTR		XPS_UART0_INT_ID
-#define XPAR_PS7_UART_1_INTR		XPS_UART1_INT_ID
-#define XPAR_PS7_USB_0_INTR		XPS_USB0_INT_ID
-#define XPAR_PS7_USB_1_INTR		XPS_USB1_INT_ID
-#define XPAR_PS7_I2C_0_INTR		XPS_I2C0_INT_ID
-#define XPAR_PS7_I2C_1_INTR		XPS_I2C1_INT_ID
-#define XPAR_PS7_SPI_0_INTR		XPS_SPI0_INT_ID
-#define XPAR_PS7_SPI_1_INTR		XPS_SPI1_INT_ID
-#define XPAR_PS7_CAN_0_INTR		XPS_CAN0_INT_ID
-#define XPAR_PS7_CAN_1_INTR		XPS_CAN1_INT_ID
-#define XPAR_PS7_GPIO_0_INTR		XPS_GPIO_INT_ID
-#define XPAR_PS7_ETHERNET_0_INTR	XPS_GEM0_INT_ID
-#define XPAR_PS7_ETHERNET_0_WAKE_INTR	XPS_GEM0_WAKE_INT_ID
-#define XPAR_PS7_ETHERNET_1_INTR	XPS_GEM1_INT_ID
-#define XPAR_PS7_ETHERNET_1_WAKE_INTR	XPS_GEM1_WAKE_INT_ID
-#define XPAR_PS7_ETHERNET_2_INTR	XPS_GEM2_INT_ID
-#define XPAR_PS7_ETHERNET_2_WAKE_INTR	XPS_GEM2_WAKE_INT_ID
-#define XPAR_PS7_ETHERNET_3_INTR	XPS_GEM3_INT_ID
-#define XPAR_PS7_ETHERNET_3_WAKE_INTR	XPS_GEM3_WAKE_INT_ID
-
-#define XPAR_PS7_QSPI_0_INTR		XPS_QSPI_INT_ID
-#define XPAR_PS7_WDT_0_INTR		XPS_WDT_INT_ID
-#define XPAR_PS7_SCUWDT_0_INTR		XPS_SCU_WDT_INT_ID
-#define XPAR_PS7_SCUTIMER_0_INTR	XPS_SCU_TMR_INT_ID
-#define XPAR_PS7_XADC_0_INTR		XPS_SYSMON_INT_ID
-
 #define XPAR_PSU_UART_0_INTR        XPS_UART0_INT_ID
 #define XPAR_PSU_UART_1_INTR        XPS_UART1_INT_ID
 #define XPAR_PSU_USB_0_INTR     XPS_USB0_INT_ID
@@ -304,9 +267,8 @@ extern "C" {
 #define XPAR_PSU_ETHERNET_3_INTR    XPS_GEM3_INT_ID
 #define XPAR_PSU_ETHERNET_3_WAKE_INTR   XPS_GEM3_WAKE_INT_ID
 #define XPAR_PSU_QSPI_0_INTR        XPS_QSPI_INT_ID
-#define XPAR_PSU_WDT_0_INTR     XPS_WDT_INT_ID
-#define XPAR_PSU_SCUWDT_0_INTR      XPS_SCU_WDT_INT_ID
-#define XPAR_PSU_SCUTIMER_0_INTR    XPS_SCU_TMR_INT_ID
+#define XPAR_PSU_WDT_0_INTR    		XPS_LPD_SWDT_INT_ID
+#define XPAR_PSU_WDT_1_INTR     	XPS_FPD_SWDT_INT_ID
 #define XPAR_PSU_XADC_0_INTR        XPS_SYSMON_INT_ID
 #define XPAR_PSU_TTC_0_INTR         XPS_TTC0_0_INT_ID
 #define XPAR_PSU_TTC_1_INTR         XPS_TTC0_1_INT_ID
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xplatform_info.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xplatform_info.c
index fea992e40..9d4560a98 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xplatform_info.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xplatform_info.c
@@ -44,6 +44,7 @@
 * 5.00  pkp  12/15/14 Initial release
 * 5.04  pkp  01/12/16 Added platform information support for Cortex-A53 32bit
 *					  mode
+* 6.00  mus  17/08/16 Removed unused variable from XGetPlatform_Info
 * </pre>
 *
 ******************************************************************************/
@@ -51,6 +52,7 @@
 /***************************** Include Files *********************************/
 
 #include "xil_types.h"
+#include "xil_io.h"
 #include "xplatform_info.h"
 
 /************************** Constant Definitions *****************************/
@@ -78,7 +80,7 @@
 ******************************************************************************/
 u32 XGetPlatform_Info()
 {
-	u32 reg;
+
 #if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
 	return XPLAT_ZYNQ_ULTRA_MP;
 #elif (__microblaze__)
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xplatform_info.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xplatform_info.h
index 7028a83af..7028a83af 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xplatform_info.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xplatform_info.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpm_counter.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpm_counter.c
index 0851408cc..0851408cc 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpm_counter.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpm_counter.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpm_counter.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpm_counter.h
index 5679d4bb5..5679d4bb5 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpm_counter.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpm_counter.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpseudo_asm.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpseudo_asm.h
index aff19d5a9..aff19d5a9 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpseudo_asm.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpseudo_asm.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpseudo_asm_gcc.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpseudo_asm_gcc.h
index 2b382acb8..b475c90e7 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpseudo_asm_gcc.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpseudo_asm_gcc.h
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -42,7 +42,8 @@
 *
 * Ver   Who      Date     Changes
 * ----- -------- -------- -----------------------------------------------
-* 5.00 	pkp  	 05/29/14 First release
+* 5.00 	pkp		 05/21/14 First release
+* 6.0   mus      07/27/16 Consolidated file for a53,a9 and r5 processors
 * </pre>
 *
 ******************************************************************************/
@@ -53,6 +54,7 @@
 /***************************** Include Files ********************************/
 
 #include "xil_types.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif /* __cplusplus */
@@ -67,6 +69,59 @@ extern "C" {
 #define stringify(s)	tostring(s)
 #define tostring(s)	#s
 
+#if defined (__aarch64__)
+/* pseudo assembler instructions */
+#define mfcpsr()	({u32 rval; \
+			   asm volatile("mrs %0,  DAIF" : "=r" (rval));\
+			  rval;\
+			 })
+
+#define mtcpsr(v) __asm__ __volatile__ ("msr DAIF, %0" : : "r" (v))
+
+#define cpsiei()	//__asm__ __volatile__("cpsie	i\n")
+#define cpsidi()	//__asm__ __volatile__("cpsid	i\n")
+
+#define cpsief()	//__asm__ __volatile__("cpsie	f\n")
+#define cpsidf()	//__asm__ __volatile__("cpsid	f\n")
+
+
+
+#define mtgpr(rn, v)	/*__asm__ __volatile__(\
+			  "mov r" stringify(rn) ", %0 \n"\
+			  : : "r" (v)\
+			)*/
+
+#define mfgpr(rn)	/*({u32 rval; \
+			  __asm__ __volatile__(\
+			    "mov %0,r" stringify(rn) "\n"\
+			    : "=r" (rval)\
+			  );\
+			  rval;\
+			 })*/
+
+/* memory synchronization operations */
+
+/* Instruction Synchronization Barrier */
+#define isb() __asm__ __volatile__ ("isb sy")
+
+/* Data Synchronization Barrier */
+#define dsb() __asm__ __volatile__("dsb sy")
+
+/* Data Memory Barrier */
+#define dmb() __asm__ __volatile__("dmb sy")
+
+
+/* Memory Operations */
+#define ldr(adr)	({u64 rval; \
+			  __asm__ __volatile__(\
+			    "ldr	%0,[%1]"\
+			    : "=r" (rval) : "r" (adr)\
+			  );\
+			  rval;\
+			 })
+
+#else
+
 /* pseudo assembler instructions */
 #define mfcpsr()	({u32 rval; \
 			  __asm__ __volatile__(\
@@ -123,6 +178,8 @@ extern "C" {
 			  rval;\
 			 })
 
+#endif
+
 #define ldrb(adr)	({u8 rval; \
 			  __asm__ __volatile__(\
 			    "ldrb	%0,[%1]"\
@@ -150,6 +207,22 @@ extern "C" {
 			  rval;\
 			 })
 
+#if defined (__aarch64__)
+#define mtcpdc(reg,val)	__asm__ __volatile__("dc " #reg ",%0"  : : "r" (val))
+#define mtcpic(reg,val)	__asm__ __volatile__("ic " #reg ",%0"  : : "r" (val))
+
+#define mtcpicall(reg)	__asm__ __volatile__("ic " #reg)
+#define mtcptlbi(reg)	__asm__ __volatile__("tlbi " #reg)
+#define mtcpat(reg,val)	__asm__ __volatile__("at " #reg ",%0"  : : "r" (val))
+/* CP15 operations */
+#define mfcp(reg)	({u64 rval;\
+			__asm__ __volatile__("mrs	%0, " #reg : "=r" (rval));\
+			rval;\
+			})
+
+#define mtcp(reg,val)	__asm__ __volatile__("msr " #reg ",%0"  : : "r" (val))
+
+#else
 /* CP15 operations */
 #define mtcp(rn, v)	__asm__ __volatile__(\
 			 "mcr " rn "\n"\
@@ -163,6 +236,7 @@ extern "C" {
 			 );\
 			 rval;\
 			 })
+#endif
 
 /************************** Variable Definitions ****************************/
 
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xreg_cortexr5.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xreg_cortexr5.h
index 9d28c0acb..9d28c0acb 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xreg_cortexr5.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xreg_cortexr5.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xstatus.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xstatus.h
index ba5f96b20..4873e85eb 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xstatus.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xstatus.h
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -303,6 +303,8 @@ extern "C" {
 #define XST_SPI_RECEIVE_NOT_EMPTY   1161	/* device received data in slave mode */
 
 #define XST_SPI_COMMAND_ERROR       1162	/* unrecognised command - qspi only */
+#define XST_SPI_POLL_DONE           1163        /* controller completed polling the
+						   device for status */
 
 /********************** OPB Arbiter statuses 1176 - 1200 *********************/
 
@@ -416,7 +418,7 @@ extern "C" {
 
 /**************************** Type Definitions *******************************/
 
-typedef int XStatus;
+typedef s32 XStatus;
 
 /***************** Macros (Inline Functions) Definitions *********************/
 
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xtime_l.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xtime_l.c
index a17ee404b..a9db4df7f 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xtime_l.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xtime_l.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -52,6 +52,9 @@
 *						are modified to read and write TTC counter value
 *						respectively
 * 5.04	pkp
+* 6.0   mus    08/11/16  Removed implementation of XTime_SetTime API, since
+*                        TTC counter value register is read only.
+*
 * </pre>
 *
 * @note		None.
@@ -63,6 +66,7 @@
 #include "xpseudo_asm.h"
 #include "xil_assert.h"
 #include "xil_io.h"
+#include "xdebug.h"
 
 /***************** Macros (Inline Functions) Definitions *********************/
 
@@ -148,24 +152,9 @@ void XTime_StartTimer(void)
 ****************************************************************************/
 void XTime_SetTime(XTime Xtime_Global)
 {
-	u32 TimerCntrl;
-	/* Disable the timer to configure */
-	TimerCntrl = Xil_In32(SLEEP_TIMER_BASEADDR +
-							SLEEP_TIMER_CNTR_CNTRL_OFFSET);
-	TimerCntrl = TimerCntrl | SLEEP_TIMER_COUNTER_CONTROL_DIS_MASK;
-	Xil_Out32(SLEEP_TIMER_BASEADDR + SLEEP_TIMER_CNTR_CNTRL_OFFSET,
-				TimerCntrl);
-
-	/* Write the lower 32bit value to timer counter register */
-	Xil_Out32(SLEEP_TIMER_BASEADDR + SLEEP_TIMER_CNTR_VAL_OFFSET,
-				Xtime_Global);
-
-	/* Enable the Timer */
-	TimerCntrl = Xil_In32(SLEEP_TIMER_BASEADDR +
-							SLEEP_TIMER_CNTR_CNTRL_OFFSET);
-	TimerCntrl = TimerCntrl & (~SLEEP_TIMER_COUNTER_CONTROL_DIS_MASK);
-	Xil_Out32(SLEEP_TIMER_BASEADDR + SLEEP_TIMER_CNTR_CNTRL_OFFSET,
-				TimerCntrl);
+/*Timer cannot be set to desired value, so the API is left unimplemented*/
+    xdbg_printf(XDBG_DEBUG_GENERAL,
+                "XTime_SetTime:Timer cannot be set to desired value,so API is not implemented\n");
 }
 
 /****************************************************************************
@@ -184,4 +173,4 @@ void XTime_GetTime(XTime *Xtime_Global)
 	*Xtime_Global = Xil_In32(SLEEP_TIMER_BASEADDR +
 								SLEEP_TIMER_CNTR_VAL_OFFSET);
 }
-#endif
-\ No newline at end of file
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xtime_l.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xtime_l.h
index 36c416d5a..36c416d5a 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xtime_l.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xtime_l.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/Makefile
index b832910b8..b832910b8 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/Makefile
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/Makefile
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu.c
index a30a257fb..b047a4599 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu.c
@@ -51,6 +51,16 @@
 *              03/03/16 Added Temperature remote channel for Setsingle
 *                       channel API. Also corrected external mux channel
 *                       numbers.
+* 1.1   kvn    05/05/16 Modified code for MISRA-C:2012 Compliance.
+* 2.0   vns    08/14/16 Fixed CR #956780, added support for enabling/disabling
+*                       SEQ_CH2 and SEQ_AVG2 registers, modified function
+*                       prototypes of XSysMonPsu_GetSeqAvgEnables,
+*                       XSysMonPsu_SetSeqAvgEnables, XSysMonPsu_SetSeqChEnables,
+*                       XSysMonPsu_GetSeqChEnables,
+*                       XSysMonPsu_SetSeqInputMode, XSysMonPsu_GetSeqInputMode,
+*                       XSysMonPsu_SetSeqAcqTime
+*                       and XSysMonPsu_GetSeqAcqTime to provide support for
+*                       set/get 64 bit value.
 *
 * </pre>
 *
@@ -148,7 +158,6 @@ s32 XSysMonPsu_CfgInitialize(XSysMonPsu *InstancePtr, XSysMonPsu_Config *ConfigP
 * function will be called.
 *
 * @param	CallBackRef is unused by this function.
-* @param	Event is unused by this function.
 *
 * @return	None.
 *
@@ -575,11 +584,6 @@ s32 XSysMonPsu_SetSingleChParams(XSysMonPsu *InstancePtr, u8 Channel,
 			  (IsDifferentialMode == FALSE));
 	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
 
-	/* Calculate the effective baseaddress based on the Sysmon instance. */
-	EffectiveBaseAddress =
-			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
-					SysmonBlk);
-
 	/* Check if the device is in single channel mode else return failure */
 	if ((XSysMonPsu_GetSequencerMode(InstancePtr, SysmonBlk)
 				!= XSM_SEQ_MODE_SINGCHAN)) {
@@ -587,6 +591,11 @@ s32 XSysMonPsu_SetSingleChParams(XSysMonPsu *InstancePtr, u8 Channel,
 		goto End;
 	}
 
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
 	/* Read the Configuration Register 0 and extract out Averaging value. */
 	RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
 			XSYSMONPSU_CFG_REG0_OFFSET) & XSYSMONPSU_CFG_REG0_AVRGNG_MASK;
@@ -653,10 +662,11 @@ End:
 *
 * @param	InstancePtr is a pointer to the XSysMonPsu instance.
 * @param	AlmEnableMask is the bit-mask of the alarm outputs to be enabled
-*		in the Configuration Register 1.
+*		in the Configuration Registers 1 and 3.
 *		Bit positions of 1 will be enabled. Bit positions of 0 will be
 *		disabled. This mask is formed by OR'ing XSYSMONPSU_CFR_REG1_ALRM_*_MASK
-*		masks defined in xsysmonpsu.h.
+*		masks defined in xsysmonpsu.h, but XSM_CFR_ALM_SUPPLY8_MASK to
+*		XSM_CFR_ALM_SUPPLY13_MASK are applicable only for PS.
 * @param	SysmonBlk is the value that tells whether it is for PS Sysmon
 *       block or PL Sysmon block register region.
 *
@@ -668,6 +678,7 @@ End:
 *		The alarm outputs specified by the AlmEnableMask are negated
 *		before writing to the Configuration Register 1 because it
 *		was Disable register bits.
+*		Upper 16 bits of AlmEnableMask are applicable only for PS.
 *
 *****************************************************************************/
 void XSysMonPsu_SetAlarmEnables(XSysMonPsu *InstancePtr, u32 AlmEnableMask,
@@ -679,7 +690,9 @@ void XSysMonPsu_SetAlarmEnables(XSysMonPsu *InstancePtr, u32 AlmEnableMask,
 	/* Assert the arguments. */
 	Xil_AssertVoid(InstancePtr != NULL);
 	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
-	Xil_AssertVoid(AlmEnableMask <= XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK);
+	Xil_AssertVoid(AlmEnableMask <=
+			(XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK |
+			(XSYSMONPSU_CFG_REG3_ALRM_ALL_MASK << XSM_CFG_ALARM_SHIFT)));
 	Xil_AssertVoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
 
 	/* Calculate the effective baseaddress based on the Sysmon instance. */
@@ -698,6 +711,16 @@ void XSysMonPsu_SetAlarmEnables(XSysMonPsu *InstancePtr, u32 AlmEnableMask,
 	 */
 	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG1_OFFSET,
 			 RegValue);
+	/* Upper 16 bits of AlmEnableMask are valid only for PS */
+	if (SysmonBlk == XSYSMON_PS) {
+		RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
+					XSYSMONPSU_CFG_REG3_OFFSET);
+		RegValue &= (u32)(~XSYSMONPSU_CFG_REG3_ALRM_ALL_MASK);
+		RegValue |= (~(AlmEnableMask >> XSM_CFG_ALARM_SHIFT) &
+				(u32)XSYSMONPSU_CFG_REG3_ALRM_ALL_MASK);
+		XSysmonPsu_WriteReg(EffectiveBaseAddress +
+			XSYSMONPSU_CFG_REG3_OFFSET, RegValue);
+	}
 }
 
 /****************************************************************************/
@@ -723,13 +746,15 @@ void XSysMonPsu_SetAlarmEnables(XSysMonPsu *InstancePtr, u32 AlmEnableMask,
 *		be disabled and alarms for bit positions of 0 will be enabled.
 *		The enabled alarm outputs returned by this function is the
 *		negated value of the the data read from the Configuration
-*		Register 1.
+*		Register 1. Upper 16 bits of return value are valid only if the
+*		channel selected is PS.
 *
 *****************************************************************************/
 u32 XSysMonPsu_GetAlarmEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
 {
 	u32 RegValue;
 	u32 EffectiveBaseAddress;
+	u32 ReadReg;
 
 	/* Assert the arguments. */
 	Xil_AssertNonvoid(InstancePtr != NULL);
@@ -749,6 +774,13 @@ u32 XSysMonPsu_GetAlarmEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
 			XSYSMONPSU_CFG_REG1_OFFSET) & XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK;
 	RegValue = (~RegValue & XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK);
 
+	if (SysmonBlk == XSYSMON_PS) {
+		ReadReg = XSysmonPsu_ReadReg(EffectiveBaseAddress +
+			XSYSMONPSU_CFG_REG3_OFFSET) & XSYSMONPSU_CFG_REG3_ALRM_ALL_MASK;
+		ReadReg = (~ReadReg & XSYSMONPSU_CFG_REG3_ALRM_ALL_MASK);
+		RegValue |= ReadReg << XSM_CFG_ALARM_SHIFT;
+	}
+
 	return RegValue;
 }
 
@@ -1143,7 +1175,7 @@ u8 XSysMonPsu_GetAdcClkDivisor(XSysMonPsu *InstancePtr, u32 SysmonBlk)
 *		Use XSYSMONPSU_SEQ_CH* defined in xsysmon_hw.h to specify the Channel
 *		numbers. Bit masks of 1 will be enabled and bit mask of 0 will
 *		be disabled.
-*		The ChEnableMask is a 32 bit mask that is written to the two
+*		The ChEnableMask is a 64 bit mask that is written to the three
 *		16 bit ADC Channel Selection Sequencer Registers.
 * @param	SysmonBlk is the value that tells whether it is for PS Sysmon
 *       block or PL Sysmon block register region.
@@ -1156,7 +1188,7 @@ u8 XSysMonPsu_GetAdcClkDivisor(XSysMonPsu *InstancePtr, u32 SysmonBlk)
 * @note		None.
 *
 *****************************************************************************/
-s32 XSysMonPsu_SetSeqChEnables(XSysMonPsu *InstancePtr, u32 ChEnableMask,
+s32 XSysMonPsu_SetSeqChEnables(XSysMonPsu *InstancePtr, u64 ChEnableMask,
 		u32 SysmonBlk)
 {
 	s32 Status;
@@ -1193,6 +1225,10 @@ s32 XSysMonPsu_SetSeqChEnables(XSysMonPsu *InstancePtr, u32 ChEnableMask,
 			 (ChEnableMask >> XSM_SEQ_CH_SHIFT) &
 			 XSYSMONPSU_SEQ_CH1_VALID_MASK);
 
+	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_SEQ_CH2_OFFSET,
+				 (ChEnableMask >> XSM_SEQ_CH2_SHIFT) &
+			 XSYSMONPSU_SEQ_CH2_VALID_MASK);
+
 	Status = (s32)XST_SUCCESS;
 
 End:
@@ -1219,9 +1255,9 @@ End:
 * @note		None.
 *
 *****************************************************************************/
-u32 XSysMonPsu_GetSeqChEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
+u64 XSysMonPsu_GetSeqChEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
 {
-	u32 RegVal;
+	u64 RegVal;
 	u32 EffectiveBaseAddress;
 
 	/* Assert the arguments. */
@@ -1243,6 +1279,9 @@ u32 XSysMonPsu_GetSeqChEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
 	RegVal |= (XSysmonPsu_ReadReg(EffectiveBaseAddress +
 			XSYSMONPSU_SEQ_CH1_OFFSET) & XSYSMONPSU_SEQ_CH1_VALID_MASK) <<
 					XSM_SEQ_CH_SHIFT;
+	RegVal |= (u64)(XSysmonPsu_ReadReg(EffectiveBaseAddress +
+			XSYSMONPSU_SEQ_CH2_OFFSET) &
+			XSYSMONPSU_SEQ_CH2_VALID_MASK) << XSM_SEQ_CH2_SHIFT;
 
 	return RegVal;
 }
@@ -1259,8 +1298,8 @@ u32 XSysMonPsu_GetSeqChEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
 *		averaging is to be enabled. Use XSYSMONPSU_SEQ_AVERAGE* defined in
 *		xsysmonpsu_hw.h to specify the Channel numbers. Averaging will be
 *		enabled for bit masks of 1 and disabled for bit mask of 0.
-*		The AvgEnableChMask is a 32 bit mask that is written to the
-*		two 16 bit ADC Channel Averaging Enable Sequencer Registers.
+*		The AvgEnableChMask is a 64 bit mask that is written to the
+*		three 16 bit ADC Channel Averaging Enable Sequencer Registers.
 * @param	SysmonBlk is the value that tells whether it is for PS Sysmon
 *       block or PL Sysmon block register region.
 *
@@ -1272,7 +1311,7 @@ u32 XSysMonPsu_GetSeqChEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
 * @note		None.
 *
 *****************************************************************************/
-s32 XSysMonPsu_SetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 AvgEnableChMask,
+s32 XSysMonPsu_SetSeqAvgEnables(XSysMonPsu *InstancePtr, u64 AvgEnableChMask,
 		u32 SysmonBlk)
 {
 	s32 Status;
@@ -1283,11 +1322,6 @@ s32 XSysMonPsu_SetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 AvgEnableChMask,
 	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
 
-	/* Calculate the effective baseaddress based on the Sysmon instance. */
-	EffectiveBaseAddress =
-			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
-					SysmonBlk);
-
 	/*
 	 * The sequencer must be disabled for writing any of these registers.
 	 * Return XST_FAILURE if the channel sequencer is enabled.
@@ -1295,24 +1329,32 @@ s32 XSysMonPsu_SetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 AvgEnableChMask,
 	if ((XSysMonPsu_GetSequencerMode(InstancePtr,SysmonBlk)
 	                                     != XSM_SEQ_MODE_SAFE)) {
 		Status = (s32)XST_FAILURE;
-		goto End;
+	} else {
+		/* Calculate the effective baseaddress based on the Sysmon instance. */
+		EffectiveBaseAddress =
+				XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+						SysmonBlk);
+		/*
+		 * Enable/disable the averaging for the specified channels in the
+		 * ADC Channel Averaging Enables Sequencer Registers.
+		 */
+		XSysmonPsu_WriteReg(EffectiveBaseAddress +
+				XSYSMONPSU_SEQ_AVERAGE0_OFFSET,
+				(AvgEnableChMask & XSYSMONPSU_SEQ_AVERAGE0_MASK));
+
+		XSysmonPsu_WriteReg(EffectiveBaseAddress +
+				XSYSMONPSU_SEQ_AVERAGE1_OFFSET,
+				 (AvgEnableChMask >> XSM_SEQ_CH_SHIFT) &
+				 XSYSMONPSU_SEQ_AVERAGE1_MASK);
+
+		XSysmonPsu_WriteReg(EffectiveBaseAddress +
+				XSYSMONPSU_SEQ_AVERAGE2_OFFSET,
+				 (AvgEnableChMask >> XSM_SEQ_CH2_SHIFT) &
+				 XSYSMONPSU_SEQ_AVERAGE2_MASK);
+
+		Status = (s32)XST_SUCCESS;
 	}
 
-	/*
-	 * Enable/disable the averaging for the specified channels in the
-	 * ADC Channel Averaging Enables Sequencer Registers.
-	 */
-	XSysmonPsu_WriteReg(EffectiveBaseAddress +
-			XSYSMONPSU_SEQ_AVERAGE0_OFFSET,
-			(AvgEnableChMask & XSYSMONPSU_SEQ_AVERAGE0_MASK));
-
-	XSysmonPsu_WriteReg(EffectiveBaseAddress +
-			XSYSMONPSU_SEQ_AVERAGE1_OFFSET,
-			 (AvgEnableChMask >> XSM_SEQ_CH_SHIFT) &
-			 XSYSMONPSU_SEQ_AVERAGE1_MASK);
-
-	Status = (s32)XST_SUCCESS;
-End:
 	return Status;
 }
 
@@ -1335,9 +1377,9 @@ End:
 * @note		None.
 *
 *****************************************************************************/
-u32 XSysMonPsu_GetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
+u64 XSysMonPsu_GetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
 {
-	u32 RegVal;
+	u64 RegVal;
 	u32 EffectiveBaseAddress;
 
 	/* Assert the arguments. */
@@ -1359,6 +1401,9 @@ u32 XSysMonPsu_GetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
 	RegVal |= (XSysmonPsu_ReadReg(EffectiveBaseAddress +
 			XSYSMONPSU_SEQ_AVERAGE1_OFFSET) & XSYSMONPSU_SEQ_AVERAGE1_MASK) <<
 			XSM_SEQ_CH_SHIFT;
+	RegVal |= (u64)(XSysmonPsu_ReadReg(EffectiveBaseAddress +
+			XSYSMONPSU_SEQ_AVERAGE2_OFFSET) &
+			XSYSMONPSU_SEQ_AVERAGE2_MASK) << XSM_SEQ_CH2_SHIFT;
 
 	return RegVal;
 }
@@ -1376,7 +1421,7 @@ u32 XSysMonPsu_GetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
 *		defined in xsysmonpsu_hw.h to specify the channel numbers. Differential
 *		or  Bipolar input mode will be set for bit masks of 1 and unipolar input
 *		mode for bit masks of 0.
-*		The InputModeChMask is a 32 bit mask that is written to the two
+*		The InputModeChMask is a 64 bit mask that is written to the three
 *		16 bit ADC Channel Analog-Input Mode Sequencer Registers.
 * @param	SysmonBlk is the value that tells whether it is for PS Sysmon
 *       block or PL Sysmon block register region.
@@ -1389,7 +1434,7 @@ u32 XSysMonPsu_GetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
 * @note		None.
 *
 *****************************************************************************/
-s32 XSysMonPsu_SetSeqInputMode(XSysMonPsu *InstancePtr, u32 InputModeChMask,
+s32 XSysMonPsu_SetSeqInputMode(XSysMonPsu *InstancePtr, u64 InputModeChMask,
 		u32 SysmonBlk)
 {
 	s32 Status;
@@ -1429,6 +1474,11 @@ s32 XSysMonPsu_SetSeqInputMode(XSysMonPsu *InstancePtr, u32 InputModeChMask,
 			 (InputModeChMask >> XSM_SEQ_CH_SHIFT) &
 			 XSYSMONPSU_SEQ_INPUT_MDE1_MASK);
 
+	XSysmonPsu_WriteReg(EffectiveBaseAddress +
+		XSYSMONPSU_SEQ_INPUT_MDE2_OFFSET,
+		 (InputModeChMask >> XSM_SEQ_CH2_SHIFT) &
+		 XSYSMONPSU_SEQ_INPUT_MDE2_MASK);
+
 	Status = (s32)XST_SUCCESS;
 
 End:
@@ -1454,9 +1504,9 @@ End:
 * @note		None.
 *
 *****************************************************************************/
-u32 XSysMonPsu_GetSeqInputMode(XSysMonPsu *InstancePtr, u32 SysmonBlk)
+u64 XSysMonPsu_GetSeqInputMode(XSysMonPsu *InstancePtr, u32 SysmonBlk)
 {
-	u32 InputMode;
+	u64 InputMode;
 	u32 EffectiveBaseAddress;
 
 	/* Assert the arguments. */
@@ -1478,6 +1528,9 @@ u32 XSysMonPsu_GetSeqInputMode(XSysMonPsu *InstancePtr, u32 SysmonBlk)
 	InputMode |= (XSysmonPsu_ReadReg(EffectiveBaseAddress +
 			XSYSMONPSU_SEQ_INPUT_MDE1_OFFSET) & XSYSMONPSU_SEQ_INPUT_MDE1_MASK) <<
 				XSM_SEQ_CH_SHIFT;
+	InputMode |= (u64)(XSysmonPsu_ReadReg(EffectiveBaseAddress +
+			XSYSMONPSU_SEQ_INPUT_MDE2_OFFSET) &
+			XSYSMONPSU_SEQ_INPUT_MDE2_MASK) << XSM_SEQ_CH2_SHIFT;
 
 	return InputMode;
 }
@@ -1496,7 +1549,7 @@ u32 XSysMonPsu_GetSeqInputMode(XSysMonPsu *InstancePtr, u32 SysmonBlk)
 *		numbers. Acquisition cycles will be extended to 10 ADCCLK cycles
 *		for bit masks of 1 and will be the default 4 ADCCLK cycles for
 *		bit masks of 0.
-*		The AcqCyclesChMask is a 32 bit mask that is written to the two
+*		The AcqCyclesChMask is a 64 bit mask that is written to the three
 *		16 bit ADC Channel Acquisition Time Sequencer Registers.
 * @param	SysmonBlk is the value that tells whether it is for PS Sysmon
 *       block or PL Sysmon block register region.
@@ -1509,7 +1562,7 @@ u32 XSysMonPsu_GetSeqInputMode(XSysMonPsu *InstancePtr, u32 SysmonBlk)
 * @note		None.
 *
 *****************************************************************************/
-s32 XSysMonPsu_SetSeqAcqTime(XSysMonPsu *InstancePtr, u32 AcqCyclesChMask,
+s32 XSysMonPsu_SetSeqAcqTime(XSysMonPsu *InstancePtr, u64 AcqCyclesChMask,
 		u32 SysmonBlk)
 {
 	s32 Status;
@@ -1546,6 +1599,10 @@ s32 XSysMonPsu_SetSeqAcqTime(XSysMonPsu *InstancePtr, u32 AcqCyclesChMask,
 	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_SEQ_ACQ1_OFFSET,
 			 (AcqCyclesChMask >> XSM_SEQ_CH_SHIFT) & XSYSMONPSU_SEQ_ACQ1_MASK);
 
+	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_SEQ_ACQ2_OFFSET,
+			(AcqCyclesChMask >> XSM_SEQ_CH2_SHIFT) &
+					XSYSMONPSU_SEQ_ACQ2_MASK);
+
 	Status = (s32)XST_SUCCESS;
 
 End:
@@ -1571,9 +1628,9 @@ End:
 * @note		None.
 *
 *****************************************************************************/
-u32 XSysMonPsu_GetSeqAcqTime(XSysMonPsu *InstancePtr, u32 SysmonBlk)
+u64 XSysMonPsu_GetSeqAcqTime(XSysMonPsu *InstancePtr, u32 SysmonBlk)
 {
-	u32 RegValAcq;
+	u64 RegValAcq;
 	u32 EffectiveBaseAddress;
 
 	/* Assert the arguments. */
@@ -1595,6 +1652,9 @@ u32 XSysMonPsu_GetSeqAcqTime(XSysMonPsu *InstancePtr, u32 SysmonBlk)
 	RegValAcq |= (XSysmonPsu_ReadReg(EffectiveBaseAddress +
 					XSYSMONPSU_SEQ_ACQ1_OFFSET) & XSYSMONPSU_SEQ_ACQ1_MASK) <<
 					XSM_SEQ_CH_SHIFT;
+	RegValAcq |= (u64)(XSysmonPsu_ReadReg(EffectiveBaseAddress +
+			XSYSMONPSU_SEQ_ACQ2_OFFSET) &
+			XSYSMONPSU_SEQ_ACQ2_MASK) << XSM_SEQ_CH2_SHIFT;
 
 	return RegValAcq;
 }
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu.h
index ae55db9ce..ba090c5aa 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu.h
@@ -151,6 +151,18 @@
 *              03/03/16 Added Temperature remote channel for Setsingle
 *                       channel API. Also corrected external mux channel
 *                       numbers.
+* 1.1   kvn    05/05/16 Modified code for MISRA-C:2012 Compliance.
+* 2.0   vns    08/14/16 Fixed CR #956780, added support for enabling/disabling
+*                       SEQ_CH2 and SEQ_AVG2 registers, modified function
+*                       prototypes of XSysMonPsu_GetSeqAvgEnables,
+*                       XSysMonPsu_SetSeqAvgEnables, XSysMonPsu_SetSeqChEnables,
+*                       XSysMonPsu_GetSeqChEnables,
+*                       XSysMonPsu_SetSeqInputMode, XSysMonPsu_GetSeqInputMode,
+*                       XSysMonPsu_SetSeqAcqTime
+*                       and XSysMonPsu_GetSeqAcqTime to provide support for
+*                       set/get 64 bit value.
+*                       Added constants XSM_CFR_ALM_SUPPLY*(8-31)_MASKs to
+*                       provide support for enabling extra PS alarams.
 *
 * </pre>
 *
@@ -332,6 +344,12 @@ extern "C" {
  * @name Alarm masks for channels in Configuration registers 1
  * @{
  */
+#define XSM_CFR_ALM_SUPPLY13_MASK	0x200000 /**< Alarm 6 - SUPPLY6 */
+#define XSM_CFR_ALM_SUPPLY12_MASK	0x100000 /**< Alarm 6 - SUPPLY6 */
+#define XSM_CFR_ALM_SUPPLY11_MASK	0x080000 /**< Alarm 6 - SUPPLY6 */
+#define XSM_CFR_ALM_SUPPLY10_MASK	0x040000 /**< Alarm 6 - SUPPLY6 */
+#define XSM_CFR_ALM_SUPPLY9_MASK	0x020000 /**< Alarm 6 - SUPPLY6 */
+#define XSM_CFR_ALM_SUPPLY8_MASK	0x010000 /**< Alarm 6 - SUPPLY6 */
 #define XSM_CFR_ALM_SUPPLY6_MASK	0x0800 /**< Alarm 6 - SUPPLY6 */
 #define XSM_CFR_ALM_SUPPLY5_MASK	0x0400 /**< Alarm 5 - SUPPLY5 */
 #define XSM_CFR_ALM_SUPPLY4_MASK	0x0200 /**< Alarm 4 - SUPPLY4 */
@@ -458,7 +476,7 @@ typedef struct {
 *
 *****************************************************************************/
 #define XSysMonPsu_TemperatureToRaw_OnChip(Temperature)				\
-	((int)(((Temperature) + 273.6777f)*65536.0f*0.00199451786f))
+	((s32)(((Temperature) + 273.6777f)*65536.0f*0.00199451786f))
 
 /****************************************************************************/
 /**
@@ -476,7 +494,7 @@ typedef struct {
 *
 *****************************************************************************/
 #define XSysMonPsu_TemperatureToRaw_ExternalRef(Temperature)		\
-	((int)(((Temperature) + 273.8195f)*65536.0f*0.00198842814f))
+	((s32)(((Temperature) + 273.8195f)*65536.0f*0.00198842814f))
 
 /****************************************************************************/
 /**
@@ -534,7 +552,7 @@ void XSysMonPsu_Reset(XSysMonPsu *InstancePtr);
 void XSysMonPsu_Reset_FromLPD(XSysMonPsu *InstancePtr);
 u32 XSysMonPsu_GetStatus(XSysMonPsu *InstancePtr, u32 SysmonBlk);
 void XSysMonPsu_StartAdcConversion(XSysMonPsu *InstancePtr);
-u16 XSysMonPsu_GetAdcData(XSysMonPsu *InstancePtr, u8 Channel, u32 SysmonBlk);
+u16 XSysMonPsu_GetAdcData(XSysMonPsu *InstancePtr, u8 Channel, u32 Block);
 u16 XSysMonPsu_GetCalibCoefficient(XSysMonPsu *InstancePtr, u8 CoeffType, u32 SysmonBlk);
 u16 XSysMonPsu_GetMinMaxMeasurement(XSysMonPsu *InstancePtr, u8 MeasurementType,
 		u32 SysmonBlk);
@@ -556,18 +574,18 @@ void XSysMonPsu_SetExtenalMux(XSysMonPsu *InstancePtr, u8 Channel, u32 SysmonBlk
 u32 XSysMonPsu_GetExtenalMux(XSysMonPsu *InstancePtr, u32 SysmonBlk);
 void XSysMonPsu_SetAdcClkDivisor(XSysMonPsu *InstancePtr, u8 Divisor, u32 SysmonBlk);
 u8 XSysMonPsu_GetAdcClkDivisor(XSysMonPsu *InstancePtr, u32 SysmonBlk);
-s32 XSysMonPsu_SetSeqChEnables(XSysMonPsu *InstancePtr, u32 ChEnableMask,
+s32 XSysMonPsu_SetSeqChEnables(XSysMonPsu *InstancePtr, u64 ChEnableMask,
 		u32 SysmonBlk);
-u32 XSysMonPsu_GetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk);
-u32 XSysMonPsu_GetSeqChEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk);
-s32 XSysMonPsu_SetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 AvgEnableChMask,
+u64 XSysMonPsu_GetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk);
+u64 XSysMonPsu_GetSeqChEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk);
+s32 XSysMonPsu_SetSeqAvgEnables(XSysMonPsu *InstancePtr, u64 AvgEnableChMask,
 		u32 SysmonBlk);
-s32 XSysMonPsu_SetSeqInputMode(XSysMonPsu *InstancePtr, u32 InputModeChMask,
+s32 XSysMonPsu_SetSeqInputMode(XSysMonPsu *InstancePtr, u64 InputModeChMask,
 		u32 SysmonBlk);
-u32 XSysMonPsu_GetSeqInputMode(XSysMonPsu *InstancePtr, u32 SysmonBlk);
-s32 XSysMonPsu_SetSeqAcqTime(XSysMonPsu *InstancePtr, u32 AcqCyclesChMask,
+u64 XSysMonPsu_GetSeqInputMode(XSysMonPsu *InstancePtr, u32 SysmonBlk);
+s32 XSysMonPsu_SetSeqAcqTime(XSysMonPsu *InstancePtr, u64 AcqCyclesChMask,
 		u32 SysmonBlk);
-u32 XSysMonPsu_GetSeqAcqTime(XSysMonPsu *InstancePtr, u32 SysmonBlk);
+u64 XSysMonPsu_GetSeqAcqTime(XSysMonPsu *InstancePtr, u32 SysmonBlk);
 void XSysMonPsu_SetAlarmThreshold(XSysMonPsu *InstancePtr, u8 AlarmThrReg,
 		u16 Value, u32 SysmonBlk);
 u16 XSysMonPsu_GetAlarmThreshold(XSysMonPsu *InstancePtr, u8 AlarmThrReg,
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_g.c
index ace39e369..b692531ad 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_g.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_hw.h
index 3012bf327..80266ebf9 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_hw.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_hw.h
@@ -44,6 +44,8 @@
 * Ver   Who    Date	Changes
 * ----- -----  -------- -----------------------------------------------
 * 1.0   kvn	  12/15/15 First release
+* 2.0   vns    08/14/16  Added CFG_REG3, SEQ_INPUT_MODE2, SEQ_ACQ2,
+*                        SEQ_CH2 and SEQ_AVG2 offsets and bit masks
 *
 * </pre>
 *
@@ -1563,6 +1565,40 @@ extern "C" {
 #define XSYSMONPSU_CFG_REG2_TST_MDE_WIDTH   2U
 #define XSYSMONPSU_CFG_REG2_TST_MDE_MASK    0x00000003U
 
+/* Register: XSysmonPsuCfgReg3 */
+#define XSYSMONPSU_CFG_REG3_OFFSET		0x0000010CU
+#define XSYSMONPSU_CFG_REG3_ALRM_ALL_MASK	0x0000003FU
+
+#define XSM_CFG_ALARM_SHIFT			16U
+
+/* Register: XSysmonPsuSeqCh2 */
+#define XSYSMONPSU_SEQ_CH2_OFFSET   0x00000118U
+
+#define XSYSMONPSU_SEQ_CH2_TEMP_RMT_SHIFT	5U
+#define XSYSMONPSU_SEQ_CH2_TEMP_RMT_MASK	0x00000020U
+
+#define XSYSMONPSU_SEQ_CH2_VCCAMS_SHIFT		4U
+#define XSYSMONPSU_SEQ_CH2_VCCAMS_MASK		0x00000010U
+
+#define XSYSMONPSU_SEQ_CH2_SUP10_SHIFT		3U
+#define XSYSMONPSU_SEQ_CH2_SUP10_MASK		0x00000008U
+
+#define XSYSMONPSU_SEQ_CH2_SUP9_SHIFT		2U
+#define XSYSMONPSU_SEQ_CH2_SUP9_MASK		0x00000004U
+
+#define XSYSMONPSU_SEQ_CH2_SUP8_SHIFT		1U
+#define XSYSMONPSU_SEQ_CH2_SUP8_MASK		0x00000002U
+
+#define XSYSMONPSU_SEQ_CH2_SUP7_SHIFT		0U
+#define XSYSMONPSU_SEQ_CH2_SUP7_MASK		0x00000001U
+
+#define XSYSMONPSU_SEQ_CH2_VALID_MASK     	0x0000003FU
+
+/* Register: XSysmonPsuSeqAverage0 */
+#define XSYSMONPSU_SEQ_AVERAGE2_OFFSET  0x0000011CU
+#define XSYSMONPSU_SEQ_AVERAGE1_RSTVAL  0x00000000U
+#define XSYSMONPSU_SEQ_AVERAGE2_MASK	0x0000003FU
+
 /**
  * Register: XSysmonPsuSeqCh0
  */
@@ -1695,6 +1731,7 @@ extern "C" {
 #define XSYSMONPSU_SEQ_CH1_VAUX00_MASK    0x00000001U
 
 #define XSM_SEQ_CH_SHIFT                  16U
+#define XSM_SEQ_CH2_SHIFT                 32U
 
 /**
  * Register: XSysmonPsuSeqAverage0
@@ -2048,6 +2085,22 @@ extern "C" {
 #define XSYSMONPSU_ALRM_TREMOTE_LWR_TSHLD_MDE_WIDTH   1U
 #define XSYSMONPSU_ALRM_TREMOTE_LWR_TSHLD_MDE_MASK    0x00000001U
 
+/* Register: XSysmonPsuSeqInputMde2 */
+#define XSYSMONPSU_SEQ_INPUT_MDE2_OFFSET	0x000001E0U
+#define XSYSMONPSU_SEQ_INPUT_MDE2_RSTVAL	0x00000000U
+
+#define XSYSMONPSU_SEQ_INPUT_MDE2_SHIFT		0U
+#define XSYSMONPSU_SEQ_INPUT_MDE2_MASK		0x0000003FU
+
+/**
+ * Register: XSysmonPsuSeqAcq2
+ */
+#define XSYSMONPSU_SEQ_ACQ2_OFFSET		0x000001E4U
+#define XSYSMONPSU_SEQ_ACQ2_RSTVAL		0x00000000U
+
+#define XSYSMONPSU_SEQ_ACQ2_SHIFT		0U
+#define XSYSMONPSU_SEQ_ACQ2_MASK		0x0000003FU
+
 /**
  * Register: XSysmonPsuSup7
  */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_intr.c
index b178c2e11..b178c2e11 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_intr.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_intr.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_selftest.c
index 5b709be14..5b709be14 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_selftest.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_selftest.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_sinit.c
index 34249a209..34249a209 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_sinit.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_sinit.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/Makefile
index 35c277dde..35c277dde 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/Makefile
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/Makefile
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps.c
index 4534553f6..394262868 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps.c
@@ -50,6 +50,8 @@
 * 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
 * 3.01	pkp	   01/30/16 Modified XTtcPs_CfgInitialize to add XTtcps_Stop
 *						to stop the timer before configuring
+* 3.2   mus    10/28/16 Modified XTtcPs_CalcIntervalFromFreq to calculate
+*                       32 bit interval count for zynq ultrascale+mpsoc
 *
 * </pre>
 *
@@ -377,7 +379,7 @@ u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr)
 *
 ****************************************************************************/
 void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
-        u16 *Interval, u8 *Prescaler)
+        XInterval *Interval, u8 *Prescaler)
 {
 	u8 TmpPrescaler;
 	u32 TempValue;
@@ -396,7 +398,7 @@ void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
 		 * The frequency is too high, it is too close to the input
 		 * clock value. Use maximum values to signal caller.
 		 */
-		*Interval = 0xFFFFU;
+		*Interval = XTTCPS_MAX_INTERVAL_COUNT;
 		*Prescaler = 0xFFU;
 		return;
 	}
@@ -408,7 +410,7 @@ void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
 		/*
 		 * We do not need a prescaler, so set the values appropriately
 		 */
-		*Interval = (u16)TempValue;
+		*Interval = (XInterval)TempValue;
 		*Prescaler = XTTCPS_CLK_CNTRL_PS_DISABLE;
 		return;
 	}
@@ -425,7 +427,7 @@ void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
 			/*
 			 * Set the values appropriately
 			 */
-			*Interval = (u16)TempValue;
+			*Interval = (XInterval)TempValue;
 			*Prescaler = TmpPrescaler;
 			return;
 		}
@@ -434,7 +436,7 @@ void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
 	/* Can not find interval values that work for the given frequency.
 	 * Return maximum values to signal caller.
 	 */
-	*Interval = 0XFFFFU;
+	*Interval = XTTCPS_MAX_INTERVAL_COUNT;
 	*Prescaler = 0XFFU;
 	return;
 }
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps.h
index 646d24db5..be266d9b3 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps.h
@@ -91,6 +91,8 @@
 * 2.0   adk    12/10/13 Updated as per the New Tcl API's
 * 3.0	pkp    12/09/14 Added support for Zynq Ultrascale Mp.Also code
 *			modified for MISRA-C:2012 compliance.
+* 3.2   mus    10/28/16 Modified XTtcPs_GetCounterValue and XTtcPs_SetInterval
+*                       macros to return 32 bit values for zynq ultrascale+mpsoc
 * </pre>
 *
 ******************************************************************************/
@@ -108,6 +110,21 @@ extern "C" {
 #include "xstatus.h"
 
 /************************** Constant Definitions *****************************/
+/*
+ * Flag for a9 processor
+ */
+ #if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
+ #define ARMA9
+ #endif
+
+/*
+ * Maximum Value for interval counter
+ */
+ #if defined(ARMA9)
+ #define XTTCPS_MAX_INTERVAL_COUNT 0xFFFFU
+ #else
+ #define XTTCPS_MAX_INTERVAL_COUNT 0xFFFFFFFFU
+ #endif
 
 /** @name Configuration options
  *
@@ -125,7 +142,6 @@ extern "C" {
 #define XTTCPS_OPTION_WAVE_DISABLE	0x00000020U 	/**< No waveform output */
 #define XTTCPS_OPTION_WAVE_POLARITY	0x00000040U	/**< Waveform polarity */
 /*@}*/
-
 /**************************** Type Definitions *******************************/
 
 /**
@@ -148,7 +164,14 @@ typedef struct {
 	u32 IsReady;		/**< Device is initialized and ready */
 } XTtcPs;
 
-
+/**
+ * This typedef contains interval count
+ */
+#if defined(ARMA9)
+typedef u16 XInterval;
+#else
+typedef u32 XInterval;
+#endif
 /***************** Macros (Inline Functions) Definitions *********************/
 
 /*
@@ -223,14 +246,27 @@ typedef struct {
 *
 * @param	InstancePtr is a pointer to the XTtcPs instance.
 *
-* @return	16-bit counter value.
+* @return	zynq:16 bit counter value.
+*           zynq ultrascale+mpsoc:32 bit counter value.
 *
 * @note		C-style signature:
-*		u16 XTtcPs_GetCounterValue(XTtcPs *InstancePtr)
+*		zynq: u16 XTtcPs_GetCounterValue(XTtcPs *InstancePtr)
+*       zynq ultrascale+mpsoc: u32 XTtcPs_GetCounterValue(XTtcPs *InstancePtr)
 *
 ****************************************************************************/
+#if defined(ARMA9)
+/*
+ * ttc supports 16 bit counter for zynq
+ */
 #define XTtcPs_GetCounterValue(InstancePtr) \
 		(u16)InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET)
+#else
+/*
+ * ttc supports 32 bit counter for zynq ultrascale+mpsoc
+ */
+#define XTtcPs_GetCounterValue(InstancePtr) \
+               InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET)
+#endif
 
 /*****************************************************************************/
 /**
@@ -256,15 +292,27 @@ typedef struct {
 *
 * @param	InstancePtr is a pointer to the XTtcPs instance.
 *
-* @return	16-bit interval value
+* @return	zynq:16 bit interval value.
+*           zynq ultrascale+mpsoc:32 bit interval value.
 *
 * @note		C-style signature:
-*		u16 XTtcPs_GetInterval(XTtcPs *InstancePtr)
+*		zynq: u16 XTtcPs_GetInterval(XTtcPs *InstancePtr)
+*       zynq ultrascale+mpsoc: u32 XTtcPs_GetInterval(XTtcPs *InstancePtr)
 *
 ****************************************************************************/
+#if defined(ARMA9)
+/*
+ * ttc supports 16 bit interval counter for zynq
+ */
 #define XTtcPs_GetInterval(InstancePtr) \
 		(u16)InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET)
-
+#else
+/*
+ * ttc supports 32 bit interval counter for zynq ultrascale+mpsoc
+ */
+#define XTtcPs_GetInterval(InstancePtr) \
+		InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET)
+#endif
 /*****************************************************************************/
 /**
 *
@@ -391,7 +439,7 @@ void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue);
 u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr);
 
 void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
-        u16 *Interval, u8 *Prescaler);
+        XInterval *Interval, u8 *Prescaler);
 
 /*
  * Functions for options, in file xttcps_options.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_g.c
index 10c16eb02..28d356092 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_g.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_hw.h
index af78bcd67..af78bcd67 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_hw.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_hw.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_options.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_options.c
index 532b235c5..532b235c5 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_options.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_options.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_selftest.c
index 4923df667..4923df667 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_selftest.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_selftest.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_sinit.c
index ef3c6ea6b..ef3c6ea6b 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_sinit.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_sinit.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/Makefile
index 88b1e625c..88b1e625c 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/Makefile
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/Makefile
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps.c
index a338d1f09..a338d1f09 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps.h
index 6bd42b21c..d915917bb 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps.h
@@ -161,6 +161,7 @@
 *						platform variable in driver instance structure.
 * 3.1   adk   14/03/16  Include interrupt examples in the peripheral test when
 *			uart is connected to a valid interrupt controller CR#946803.
+* 3.2   rk     07/20/16 Modified the logic for transmission break bit set
 *
 * </pre>
 *
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_g.c
index 94aaf5b2e..d4a8e5ab9 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_g.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_hw.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_hw.c
index 299dd35ae..299dd35ae 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_hw.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_hw.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_hw.h
index 9f5f0b700..9f5f0b700 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_hw.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_hw.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_intr.c
index 849cb48db..3068ee795 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_intr.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_intr.c
@@ -249,7 +249,7 @@ void XUartPs_InterruptHandler(XUartPs *InstancePtr)
 *****************************************************************************/
 static void ReceiveErrorHandler(XUartPs *InstancePtr, u32 IsrStatus)
 {
-	u32 ByteStatusValue, EventData;
+	u32 EventData;
 	u32 Event;
 
 	InstancePtr->is_rxbs_error = 0;
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_options.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_options.c
index 7051d07ec..9a699afa1 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_options.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_options.c
@@ -47,6 +47,7 @@
 * 1.00  sdm    09/27/11 Fixed a bug in XUartPs_SetFlowDelay where the input
 *			value was not being written to the register.
 * 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.2   rk     07/20/16 Modified the logic for transmission break bit set
 *
 * </pre>
 *
@@ -199,6 +200,8 @@ void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options)
 		 * the register.
 		 */
 		if ((Options & OptionsTable[Index].Option) != (u16)0) {
+			if(OptionsTable[Index].Option == XUARTPS_OPTION_SET_BREAK)
+				Register &= ~XUARTPS_CR_STOPBRK;
 			Register |= OptionsTable[Index].Mask;
 		}
 		else {
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_selftest.c
index a1a7dd366..a1a7dd366 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_selftest.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_selftest.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_sinit.c
index 8dc87dae3..8dc87dae3 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_sinit.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_sinit.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/Makefile
new file mode 100644
index 000000000..d30648814
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xusbps_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling usbpsu"
+
+xusbps_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xusbps_includes
+
+xusbps_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu.c
new file mode 100644
index 000000000..c39d11a2f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu.c
@@ -0,0 +1,906 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xusbpsu.c
+* @addtogroup usbpsu_v1_0
+* @{
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.0   sg    06/16/16 First release
+* 1.1   sg    10/24/16 Added new function XUsbPsu_IsSuperSpeed
+*
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xusbpsu.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+* Waits until a bit in a register is cleared or timeout occurs
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+* @param	Offset is register offset.
+* @param	BitMask is bit mask of required bit to be checked.
+* @param	Timeout is the time to wait specified in micro seconds.
+*
+* @return
+*			- XST_SUCCESS when bit is cleared.
+*			- XST_FAILURE when timed out.
+*
+******************************************************************************/
+s32 XUsbPsu_Wait_Clear_Timeout(struct XUsbPsu *InstancePtr, u32 Offset,
+								u32 BitMask, u32 Timeout)
+{
+	u32 RegVal;
+	u32 LocalTimeout = Timeout;
+
+	do {
+		RegVal = XUsbPsu_ReadReg(InstancePtr, Offset);
+		if ((RegVal & BitMask) == 0U) {
+			break;
+		}
+		LocalTimeout--;
+		if (LocalTimeout == 0U) {
+			return XST_FAILURE;
+		}
+		XUsbSleep(1U);
+	} while (1);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* Waits until a bit in a register is set or timeout occurs
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+* @param	Offset is register offset.
+* @param	BitMask is bit mask of required bit to be checked.
+* @param	Timeout is the time to wait specified in micro seconds.
+*
+* @return
+*			- XST_SUCCESS when bit is set.
+*			- XST_FAILURE when timed out.
+*
+******************************************************************************/
+s32 XUsbPsu_Wait_Set_Timeout(struct XUsbPsu *InstancePtr, u32 Offset,
+								u32 BitMask, u32 Timeout)
+{
+	u32 RegVal;
+	u32 LocalTimeout = Timeout;
+
+	do {
+		RegVal = XUsbPsu_ReadReg(InstancePtr, Offset);
+		if ((RegVal & BitMask) != 0U) {
+			break;
+		}
+		LocalTimeout--;
+		if (LocalTimeout == 0U) {
+			return XST_FAILURE;
+		}
+		XUsbSleep(1U);
+	} while (1);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* Sets mode of Core to USB Device/Host/OTG.
+*
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+* @param	Mode is mode to set
+*			- XUSBPSU_GCTL_PRTCAP_OTG
+*			- XUSBPSU_GCTL_PRTCAP_HOST
+*			- XUSBPSU_GCTL_PRTCAP_DEVICE
+*
+* @return	None
+*
+******************************************************************************/
+void XUsbPsu_SetMode(struct XUsbPsu *InstancePtr, u32 Mode)
+{
+	u32 RegVal;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid((Mode <= XUSBPSU_GCTL_PRTCAP_OTG) &&
+					(Mode >= XUSBPSU_GCTL_PRTCAP_HOST));
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GCTL);
+	RegVal &= ~(XUSBPSU_GCTL_PRTCAPDIR(XUSBPSU_GCTL_PRTCAP_OTG));
+	RegVal |= XUSBPSU_GCTL_PRTCAPDIR(Mode);
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GCTL, RegVal);
+}
+
+/*****************************************************************************/
+/**
+* Issues core PHY reset.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+*
+* @return	None
+*
+******************************************************************************/
+void XUsbPsu_PhyReset(struct XUsbPsu *InstancePtr)
+{
+	u32		RegVal;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	/* Before Resetting PHY, put Core in Reset */
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GCTL);
+	RegVal |= XUSBPSU_GCTL_CORESOFTRESET;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GCTL, RegVal);
+
+	/* Assert USB3 PHY reset */
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GUSB3PIPECTL(0));
+	RegVal |= XUSBPSU_GUSB3PIPECTL_PHYSOFTRST;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GUSB3PIPECTL(0), RegVal);
+
+	/* Assert USB2 PHY reset */
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GUSB2PHYCFG(0));
+	RegVal |= XUSBPSU_GUSB2PHYCFG_PHYSOFTRST;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GUSB2PHYCFG(0), RegVal);
+
+	XUsbSleep(XUSBPSU_PHY_TIMEOUT);
+
+	/* Clear USB3 PHY reset */
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GUSB3PIPECTL(0));
+	RegVal &= ~XUSBPSU_GUSB3PIPECTL_PHYSOFTRST;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GUSB3PIPECTL(0), RegVal);
+
+	/* Clear USB2 PHY reset */
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GUSB2PHYCFG(0));
+	RegVal &= ~XUSBPSU_GUSB2PHYCFG_PHYSOFTRST;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GUSB2PHYCFG(0), RegVal);
+
+	XUsbSleep(XUSBPSU_PHY_TIMEOUT);
+
+	/* Take Core out of reset state after PHYS are stable*/
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GCTL);
+	RegVal &= ~XUSBPSU_GCTL_CORESOFTRESET;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GCTL, RegVal);
+}
+
+/*****************************************************************************/
+/**
+* Sets up Event buffers so that events are written by Core.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+*
+* @return	None
+*
+******************************************************************************/
+void XUsbPsu_EventBuffersSetup(struct XUsbPsu *InstancePtr)
+{
+    struct XUsbPsu_EvtBuffer *Evt;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	Evt = &InstancePtr->Evt;
+	Evt->BuffAddr = (void *)InstancePtr->EventBuffer;
+
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTADRLO(0),
+						(UINTPTR)InstancePtr->EventBuffer);
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTADRHI(0),
+						((UINTPTR)(InstancePtr->EventBuffer) >> 16U) >> 16U);
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTSIZ(0),
+					XUSBPSU_GEVNTSIZ_SIZE(sizeof(InstancePtr->EventBuffer)));
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0), 0);
+}
+
+/*****************************************************************************/
+/**
+* Resets Event buffer Registers to zero so that events are not written by Core.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+*
+* @return	None
+*
+******************************************************************************/
+void XUsbPsu_EventBuffersReset(struct XUsbPsu *InstancePtr)
+{
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTADRLO(0U), 0U);
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTADRHI(0U), 0U);
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTSIZ(0U),
+			(u32)XUSBPSU_GEVNTSIZ_INTMASK | XUSBPSU_GEVNTSIZ_SIZE(0U));
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0U), 0U);
+}
+
+/*****************************************************************************/
+/**
+* Reads data from Hardware Params Registers of Core.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+* @param	RegIndex is Register number to read
+*			- XUSBPSU_GHWPARAMS0
+*			- XUSBPSU_GHWPARAMS1
+*			- XUSBPSU_GHWPARAMS2
+*			- XUSBPSU_GHWPARAMS3
+*			- XUSBPSU_GHWPARAMS4
+*			- XUSBPSU_GHWPARAMS5
+*			- XUSBPSU_GHWPARAMS6
+*			- XUSBPSU_GHWPARAMS7
+*
+* @return	One of the GHWPARAMS RegValister contents.
+*
+******************************************************************************/
+u32 XUsbPsu_ReadHwParams(struct XUsbPsu *InstancePtr, u8 RegIndex)
+{
+	u32 RegVal;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(RegIndex <= (u8)XUSBPSU_GHWPARAMS7);
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, ((u32)XUSBPSU_GHWPARAMS0_OFFSET +
+							((u32)RegIndex * (u32)4)));
+	return RegVal;
+}
+
+/*****************************************************************************/
+/**
+* Initializes Core.
+*
+* @param  InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+*
+* @return
+*	 	- XST_SUCCESS if initialization was successful
+*		- XST_FAILURE if initialization was not successful
+*
+******************************************************************************/
+s32 XUsbPsu_CoreInit(struct XUsbPsu *InstancePtr)
+{
+	u32		RegVal;
+	u32		Hwparams1;
+
+	/* issue device SoftReset too */
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, XUSBPSU_DCTL_CSFTRST);
+
+	if (XUsbPsu_Wait_Clear_Timeout(InstancePtr, XUSBPSU_DCTL,
+			XUSBPSU_DCTL_CSFTRST, 500U) == XST_FAILURE) {
+		/* timed out return failure */
+		return XST_FAILURE;
+	}
+
+	XUsbPsu_PhyReset(InstancePtr);
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GCTL);
+    RegVal &= ~XUSBPSU_GCTL_SCALEDOWN_MASK;
+    RegVal &= ~XUSBPSU_GCTL_DISSCRAMBLE;
+    RegVal |= XUSBPSU_GCTL_U2EXIT_LFPS;
+
+	Hwparams1 = XUsbPsu_ReadHwParams(InstancePtr, 1U);
+
+	switch (XUSBPSU_GHWPARAMS1_EN_PWROPT(Hwparams1)) {
+		case XUSBPSU_GHWPARAMS1_EN_PWROPT_CLK:
+			RegVal &= ~XUSBPSU_GCTL_DSBLCLKGTNG;
+			break;
+
+		case XUSBPSU_GHWPARAMS1_EN_PWROPT_HIB:
+		/* enable hibernation here */
+			break;
+
+		default:
+			/* Made for Misra-C Compliance. */
+			break;
+	}
+
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GCTL, RegVal);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* Enables an interrupt in Event Enable RegValister.
+*
+* @param  InstancePtr is a pointer to the XUsbPsu instance to be worked on
+* @param  Mask is the OR of any Interrupt Enable Masks:
+*		- XUSBPSU_DEVTEN_VNDRDEVTSTRCVEDEN
+*		- XUSBPSU_DEVTEN_EVNTOVERFLOWEN
+*		- XUSBPSU_DEVTEN_CMDCMPLTEN
+*		- XUSBPSU_DEVTEN_ERRTICERREN
+*		- XUSBPSU_DEVTEN_SOFEN
+*		- XUSBPSU_DEVTEN_EOPFEN
+*		- XUSBPSU_DEVTEN_HIBERNATIONREQEVTEN
+*		- XUSBPSU_DEVTEN_WKUPEVTEN
+*		- XUSBPSU_DEVTEN_ULSTCNGEN
+*		- XUSBPSU_DEVTEN_CONNECTDONEEN
+*		- XUSBPSU_DEVTEN_USBRSTEN
+*		- XUSBPSU_DEVTEN_DISCONNEVTEN
+*
+* @return  None
+*
+******************************************************************************/
+void XUsbPsu_EnableIntr(struct XUsbPsu *InstancePtr, u32 Mask)
+{
+    u32	RegVal;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+    RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DEVTEN);
+    RegVal |= Mask;
+
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DEVTEN, RegVal);
+}
+
+/*****************************************************************************/
+/**
+* Disables an interrupt in Event Enable RegValister.
+*
+* @param  InstancePtr is a pointer to the XUsbPsu instance to be worked on.
+* @param  Mask is the OR of Interrupt Enable Masks
+*		- XUSBPSU_DEVTEN_VNDRDEVTSTRCVEDEN
+*		- XUSBPSU_DEVTEN_EVNTOVERFLOWEN
+*		- XUSBPSU_DEVTEN_CMDCMPLTEN
+*		- XUSBPSU_DEVTEN_ERRTICERREN
+*		- XUSBPSU_DEVTEN_SOFEN
+*		- XUSBPSU_DEVTEN_EOPFEN
+*		- XUSBPSU_DEVTEN_HIBERNATIONREQEVTEN
+*		- XUSBPSU_DEVTEN_WKUPEVTEN
+*		- XUSBPSU_DEVTEN_ULSTCNGEN
+*		- XUSBPSU_DEVTEN_CONNECTDONEEN
+*		- XUSBPSU_DEVTEN_USBRSTEN
+*		- XUSBPSU_DEVTEN_DISCONNEVTEN
+*
+* @return  None
+*
+******************************************************************************/
+void XUsbPsu_DisableIntr(struct XUsbPsu *InstancePtr, u32 Mask)
+{
+	u32 RegVal;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DEVTEN);
+	RegVal &= ~Mask;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DEVTEN, RegVal);
+}
+
+/****************************************************************************/
+/**
+*
+* This function does the following:
+*	- initializes a specific XUsbPsu instance.
+*	- sets up Event Buffer for Core to write events.
+*	- Core Reset and PHY Reset.
+*	- Sets core in Device Mode.
+*	- Sets default speed as HIGH_SPEED.
+*	- Sets Device Address to 0.
+*	- Enables interrupts.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	ConfigPtr points to the XUsbPsu device configuration structure.
+* @param	BaseAddress is the device base address in the virtual memory
+*			address space. If the address translation is not used then the
+*			physical address is passed.
+*			Unexpected errors may occur if the address mapping is changed
+*			after this function is invoked.
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XUsbPsu_CfgInitialize(struct XUsbPsu *InstancePtr,
+			XUsbPsu_Config *ConfigPtr, u32 BaseAddress)
+{
+	int Status;
+	u32 RegVal;
+
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr   != NULL);
+	Xil_AssertNonvoid(BaseAddress != 0U)
+
+	InstancePtr->ConfigPtr = ConfigPtr;
+
+	Status = XUsbPsu_CoreInit(InstancePtr);
+	if (Status != XST_SUCCESS) {
+#ifdef XUSBPSU_DEBUG
+		xil_printf("Core initialization failed\r\n");
+#endif
+		return XST_FAILURE;
+	}
+
+	RegVal = XUsbPsu_ReadHwParams(InstancePtr, 3U);
+	InstancePtr->NumInEps = (u8)XUSBPSU_NUM_IN_EPS(RegVal);
+	InstancePtr->NumOutEps = (u8)(XUSBPSU_NUM_EPS(RegVal) -
+			InstancePtr->NumInEps);
+
+	/* Map USB and Physical Endpoints */
+	XUsbPsu_InitializeEps(InstancePtr);
+
+	XUsbPsu_EventBuffersSetup(InstancePtr);
+
+	XUsbPsu_SetMode(InstancePtr, XUSBPSU_GCTL_PRTCAP_DEVICE);
+
+    /*
+     * Setting to max speed to support SS and HS
+     */
+    XUsbPsu_SetSpeed(InstancePtr, XUSBPSU_DCFG_SUPERSPEED);
+
+	(void)XUsbPsu_SetDeviceAddress(InstancePtr, 0U);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* Starts the controller so that Host can detect this device.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XUsbPsu_Start(struct XUsbPsu *InstancePtr)
+{
+	u32			RegVal;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+
+	RegVal |= XUSBPSU_DCTL_RUN_STOP;
+
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+	if (XUsbPsu_Wait_Clear_Timeout(InstancePtr, XUSBPSU_DSTS,
+			XUSBPSU_DSTS_DEVCTRLHLT, 500U) == XST_FAILURE) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* Stops the controller so that Device disconnects from Host.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XUsbPsu_Stop(struct XUsbPsu *InstancePtr)
+{
+	u32	RegVal;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+	RegVal &= ~XUSBPSU_DCTL_RUN_STOP;
+
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+	if (XUsbPsu_Wait_Set_Timeout(InstancePtr, XUSBPSU_DSTS,
+			XUSBPSU_DSTS_DEVCTRLHLT, 500U) == XST_FAILURE) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+ * Enables USB2 Test Modes
+ *
+ * @param	InstancePtr is a pointer to the XUsbPsu instance.
+ * @param	Mode is Test mode to set.
+ *
+ * @return	XST_SUCCESS else XST_FAILURE
+ *
+ * @note	None.
+ *
+ ****************************************************************************/
+s32 XUsbPsu_SetTestMode(struct XUsbPsu *InstancePtr, u32 Mode)
+{
+	u32	RegVal;
+	s32 Status = XST_SUCCESS;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid((Mode >= XUSBPSU_TEST_J)
+			&& (Mode <= XUSBPSU_TEST_FORCE_ENABLE));
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+	RegVal &= ~XUSBPSU_DCTL_TSTCTRL_MASK;
+
+	switch (Mode) {
+		case XUSBPSU_TEST_J:
+		case XUSBPSU_TEST_K:
+		case XUSBPSU_TEST_SE0_NAK:
+		case XUSBPSU_TEST_PACKET:
+		case XUSBPSU_TEST_FORCE_ENABLE:
+			RegVal |= (u32)Mode << 1;
+			break;
+
+		default:
+			Status = (s32)XST_FAILURE;
+			break;
+	}
+
+	if (Status != (s32)XST_FAILURE) {
+		XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+		Status = XST_SUCCESS;
+	}
+
+	return Status;
+}
+
+/****************************************************************************/
+/**
+ * Gets current State of USB Link
+ *
+ * @param	InstancePtr is a pointer to the XUsbPsu instance.
+ *
+ * @return	Link State
+ *
+ * @note	None.
+ *
+ ****************************************************************************/
+XusbPsuLinkState XUsbPsu_GetLinkState(struct XUsbPsu *InstancePtr)
+{
+	u32		RegVal;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DSTS);
+
+	return XUSBPSU_DSTS_USBLNKST(RegVal);
+}
+
+/****************************************************************************/
+/**
+ * Sets USB Link to a particular State
+ *
+ * @param	InstancePtr is a pointer to the XUsbPsu instance.
+ * @param	State is State of Link to set.
+ *
+ * @return	XST_SUCCESS else XST_FAILURE
+ *
+ * @note	None.
+ *
+ ****************************************************************************/
+s32 XUsbPsu_SetLinkState(struct XUsbPsu *InstancePtr,
+		XusbPsuLinkStateChange State)
+{
+	u32		RegVal;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	 /* Wait until device controller is ready. */
+	if (XUsbPsu_Wait_Clear_Timeout(InstancePtr, XUSBPSU_DSTS,
+			XUSBPSU_DSTS_DCNRD, 500U) == XST_FAILURE) {
+		return XST_FAILURE;
+	}
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+	RegVal &= ~XUSBPSU_DCTL_ULSTCHNGREQ_MASK;
+
+	RegVal |= XUSBPSU_DCTL_ULSTCHNGREQ(State);
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Sets speed of the Core for connecting to Host
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Speed is required speed
+*				- XUSBPSU_DCFG_HIGHSPEED
+*				- XUSBPSU_DCFG_FULLSPEED2
+*				- XUSBPSU_DCFG_LOWSPEED
+*				- XUSBPSU_DCFG_FULLSPEED1
+*
+* @return	None
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_SetSpeed(struct XUsbPsu *InstancePtr, u32 Speed)
+{
+	u32	RegVal;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Speed <= (u32)XUSBPSU_DCFG_SUPERSPEED);
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCFG);
+	RegVal &= ~(XUSBPSU_DCFG_SPEED_MASK);
+	RegVal |= Speed;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCFG, RegVal);
+}
+
+/****************************************************************************/
+/**
+* Sets Device Address of the Core
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Addr is address to set.
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note	None.
+*
+*****************************************************************************/
+s32 XUsbPsu_SetDeviceAddress(struct XUsbPsu *InstancePtr, u16 Addr)
+{
+	u32 RegVal;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Addr <= 127U);
+
+	if (InstancePtr->State == XUSBPSU_STATE_CONFIGURED) {
+		return XST_FAILURE;
+	}
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCFG);
+	RegVal &= ~(XUSBPSU_DCFG_DEVADDR_MASK);
+	RegVal |= XUSBPSU_DCFG_DEVADDR(Addr);
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCFG, RegVal);
+
+	if (Addr) {
+		InstancePtr->State = XUSBPSU_STATE_ADDRESS;
+	}
+	else {
+		InstancePtr->State = XUSBPSU_STATE_DEFAULT;
+	}
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Sets speed of the Core for connecting to Host
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XUsbPsu_IsSuperSpeed(struct XUsbPsu *InstancePtr)
+{
+	if (InstancePtr->Speed != XUSBPSU_SPEED_SUPER) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Set U1 sleep timeout
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Sleep is time in microseconds
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note	None.
+*
+*****************************************************************************/
+s32 XUsbPsu_SetU1SleepTimeout(struct XUsbPsu *InstancePtr, u8 Sleep)
+{
+	u32 RegVal;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_PORTMSC_30);
+	RegVal &= ~XUSBPSU_PORTMSC_30_U1_TIMEOUT_MASK;
+	RegVal |= (Sleep << XUSBPSU_PORTMSC_30_U1_TIMEOUT_SHIFT);
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_PORTMSC_30, RegVal);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Set U2 sleep timeout
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Sleep is time in microseconds
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note	None.
+*
+*****************************************************************************/
+s32 XUsbPsu_SetU2SleepTimeout(struct XUsbPsu *InstancePtr, u8 Sleep)
+{
+	u32 RegVal;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_PORTMSC_30);
+	RegVal &= ~XUSBPSU_PORTMSC_30_U2_TIMEOUT_MASK;
+	RegVal |= (Sleep << XUSBPSU_PORTMSC_30_U2_TIMEOUT_SHIFT);
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_PORTMSC_30, RegVal);
+
+	return XST_SUCCESS;
+}
+/****************************************************************************/
+/**
+* Enable Accept U1 and U2 sleep enable
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note	None.
+*
+*****************************************************************************/
+s32 XUsbPsu_AcceptU1U2Sleep(struct XUsbPsu *InstancePtr)
+{
+	u32 RegVal;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+	RegVal |= XUSBPSU_DCTL_ACCEPTU2ENA | XUSBPSU_DCTL_ACCEPTU1ENA;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Enable U1 enable sleep
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note	None.
+*
+*****************************************************************************/
+s32 XUsbPsu_U1SleepEnable(struct XUsbPsu *InstancePtr)
+{
+	u32 RegVal;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+	RegVal |= XUSBPSU_DCTL_INITU1ENA;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Enable U2 enable sleep
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note	None.
+*
+*****************************************************************************/
+s32 XUsbPsu_U2SleepEnable(struct XUsbPsu *InstancePtr)
+{
+	u32 RegVal;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+	RegVal |= XUSBPSU_DCTL_INITU2ENA;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Enable U1 disable sleep
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note	None.
+*
+*****************************************************************************/
+s32 XUsbPsu_U1SleepDisable(struct XUsbPsu *InstancePtr)
+{
+	u32 RegVal;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+	RegVal &= ~XUSBPSU_DCTL_INITU1ENA;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Enable U2 disable sleep
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note	None.
+*
+*****************************************************************************/
+s32 XUsbPsu_U2SleepDisable(struct XUsbPsu *InstancePtr)
+{
+	u32 RegVal;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+	RegVal &= ~XUSBPSU_DCTL_INITU2ENA;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+	return XST_SUCCESS;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu.h
new file mode 100644
index 000000000..a1366487b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu.h
@@ -0,0 +1,608 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xusbpsu.h
+* @addtogroup usbpsu_v1_0
+* @{
+* @details
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.0   sg    06/06/16 First release
+* 1.1   sg    10/24/16 Update for backward compatability
+*                      Added XUsbPsu_IsSuperSpeed function in xusbpsu.c
+*
+* </pre>
+*
+*****************************************************************************/
+#ifndef XUSBPSU_H  /* Prevent circular inclusions */
+#define XUSBPSU_H  /* by using protection macros  */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+#include "xparameters.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xusbpsu_hw.h"
+#include "xil_io.h"
+/*
+ * The header sleep.h and API usleep() can only be used with an arm design.
+ * MB_Sleep() is used for microblaze design.
+ */
+#if defined (__arm__) || defined (__aarch64__)
+#include "sleep.h"
+#endif
+
+#ifdef __MICROBLAZE__
+#include "microblaze_sleep.h"
+#endif
+#include "xil_cache.h"
+
+/************************** Constant Definitions ****************************/
+
+#define ALIGNMENT_CACHELINE		__attribute__ ((aligned(64)))
+
+#define	XUSBPSU_PHY_TIMEOUT		5000U /* in micro seconds */
+
+#define XUSBPSU_EP_DIR_IN				1U
+#define XUSBPSU_EP_DIR_OUT				0U
+
+#define XUSBPSU_ENDPOINT_NUMBER_MASK        0x0f    /* in bEndpointAddress */
+#define XUSBPSU_ENDPOINT_DIR_MASK           0x80
+
+#define XUSBPSU_ENDPOINT_XFERTYPE_MASK      0x03    /* in bmAttributes */
+#define XUSBPSU_ENDPOINT_XFER_CONTROL       0U
+#define XUSBPSU_ENDPOINT_XFER_ISOC          1U
+#define XUSBPSU_ENDPOINT_XFER_BULK          2U
+#define XUSBPSU_ENDPOINT_XFER_INT           3U
+#define XUSBPSU_ENDPOINT_MAX_ADJUSTABLE     0x80
+
+#define	XUSBPSU_TEST_J							1U
+#define	XUSBPSU_TEST_K							2U
+#define	XUSBPSU_TEST_SE0_NAK					3U
+#define	XUSBPSU_TEST_PACKET						4U
+#define	XUSBPSU_TEST_FORCE_ENABLE				5U
+
+#define XUSBPSU_NUM_TRBS				8
+
+#define XUSBPSU_EVENT_PENDING		(0x00000001U << 0)
+
+#define XUSBPSU_EP_ENABLED			(0x00000001U << 0)
+#define XUSBPSU_EP_STALL			(0x00000001U << 1)
+#define XUSBPSU_EP_WEDGE			(0x00000001U << 2)
+#define XUSBPSU_EP_BUSY				((u32)0x00000001U << 4)
+#define XUSBPSU_EP_PENDING_REQUEST	(0x00000001U << 5)
+#define XUSBPSU_EP_MISSED_ISOC		(0x00000001U << 6)
+
+#define	XUSBPSU_GHWPARAMS0				0U
+#define	XUSBPSU_GHWPARAMS1				1U
+#define	XUSBPSU_GHWPARAMS2				2U
+#define	XUSBPSU_GHWPARAMS3				3U
+#define	XUSBPSU_GHWPARAMS4				4U
+#define	XUSBPSU_GHWPARAMS5				5U
+#define	XUSBPSU_GHWPARAMS6				6U
+#define	XUSBPSU_GHWPARAMS7				7U
+
+/* HWPARAMS0 */
+#define XUSBPSU_MODE(n)					((n) & 0x7)
+#define XUSBPSU_MDWIDTH(n)				(((n) & 0xff00) >> 8)
+
+/* HWPARAMS1 */
+#define XUSBPSU_NUM_INT(n)				(((n) & (0x3f << 15)) >> 15)
+
+/* HWPARAMS3 */
+#define XUSBPSU_NUM_IN_EPS_MASK		((u32)0x0000001fU << (u32)18)
+#define XUSBPSU_NUM_EPS_MASK		((u32)0x0000003fU << (u32)12)
+#define XUSBPSU_NUM_EPS(p)			(((u32)(p) &		\
+									(XUSBPSU_NUM_EPS_MASK)) >> (u32)12)
+#define XUSBPSU_NUM_IN_EPS(p)		(((u32)(p) &		\
+									(XUSBPSU_NUM_IN_EPS_MASK)) >> (u32)18)
+
+/* HWPARAMS7 */
+#define XUSBPSU_RAM1_DEPTH(n)			((n) & 0xffff)
+
+#define XUSBPSU_DEPEVT_XFERCOMPLETE		0x01U
+#define XUSBPSU_DEPEVT_XFERINPROGRESS	0x02U
+#define XUSBPSU_DEPEVT_XFERNOTREADY		0x03U
+#define XUSBPSU_DEPEVT_STREAMEVT		0x06U
+#define XUSBPSU_DEPEVT_EPCMDCMPLT		0x07U
+
+/* Within XferNotReady */
+#define DEPEVT_STATUS_TRANSFER_ACTIVE	(1 << 3)
+
+/* Within XferComplete */
+#define DEPEVT_STATUS_BUSERR			(1 << 0)
+#define DEPEVT_STATUS_SHORT				(1 << 1)
+#define DEPEVT_STATUS_IOC				(1 << 2)
+#define DEPEVT_STATUS_LST				(1 << 3)
+
+/* Stream event only */
+#define DEPEVT_STREAMEVT_FOUND		1U
+#define DEPEVT_STREAMEVT_NOTFOUND	2U
+
+/* Control-only Status */
+#define DEPEVT_STATUS_CONTROL_DATA				1U
+#define DEPEVT_STATUS_CONTROL_STATUS			2U
+#define DEPEVT_STATUS_CONTROL_DATA_INVALTRB		9
+#define DEPEVT_STATUS_CONTROL_STATUS_INVALTRB	0xA
+
+#define XUSBPSU_ENDPOINTS_NUM			12U
+
+#define XUSBPSU_EVENT_SIZE				4U       /* bytes */
+#define XUSBPSU_EVENT_MAX_NUM			64U      /* 2 events/endpoint */
+#define XUSBPSU_EVENT_BUFFERS_SIZE		(XUSBPSU_EVENT_SIZE * \
+										XUSBPSU_EVENT_MAX_NUM)
+
+#define XUSBPSU_EVENT_TYPE_MASK                 0x000000feU
+
+#define XUSBPSU_EVENT_TYPE_DEV                  0U
+#define XUSBPSU_EVENT_TYPE_CARKIT               3U
+#define XUSBPSU_EVENT_TYPE_I2C                  4U
+
+#define XUSBPSU_DEVICE_EVENT_DISCONNECT         0U
+#define XUSBPSU_DEVICE_EVENT_RESET              1U
+#define XUSBPSU_DEVICE_EVENT_CONNECT_DONE       2U
+#define XUSBPSU_DEVICE_EVENT_LINK_STATUS_CHANGE 3U
+#define XUSBPSU_DEVICE_EVENT_WAKEUP             4U
+#define XUSBPSU_DEVICE_EVENT_HIBER_REQ          5U
+#define XUSBPSU_DEVICE_EVENT_EOPF               6U
+#define XUSBPSU_DEVICE_EVENT_SOF                7U
+#define XUSBPSU_DEVICE_EVENT_ERRATIC_ERROR      9U
+#define XUSBPSU_DEVICE_EVENT_CMD_CMPL           10U
+#define XUSBPSU_DEVICE_EVENT_OVERFLOW           11U
+
+#define XUSBPSU_GEVNTCOUNT_MASK                 0x0000fffcU
+
+/*
+ * Control Endpoint state
+ */
+#define	XUSBPSU_EP0_SETUP_PHASE				1U	/**< Setup Phase */
+#define	XUSBPSU_EP0_DATA_PHASE				2U	/**< Data Phase */
+#define	XUSBPSU_EP0_STATUS_PHASE			3U	/**< Status Pahse */
+
+/*
+ * Link State
+ */
+#define		XUSBPSU_LINK_STATE_MASK			0x0FU
+
+typedef enum {
+	XUSBPSU_LINK_STATE_U0 = 0x00U, /**< in HS - ON */
+	XUSBPSU_LINK_STATE_U1 =	0x01U,
+	XUSBPSU_LINK_STATE_U2 =	0x02U, /**< in HS - SLEEP */
+	XUSBPSU_LINK_STATE_U3 =	0x03U, /**< in HS - SUSPEND */
+	XUSBPSU_LINK_STATE_SS_DIS =	0x04U,
+	XUSBPSU_LINK_STATE_RX_DET =	0x05U,
+	XUSBPSU_LINK_STATE_SS_INACT = 0x06U,
+	XUSBPSU_LINK_STATE_POLL	=	0x07U,
+	XUSBPSU_LINK_STATE_RECOV =	0x08U,
+	XUSBPSU_LINK_STATE_HRESET =	0x09U,
+	XUSBPSU_LINK_STATE_CMPLY =	0x0AU,
+	XUSBPSU_LINK_STATE_LPBK	=	0x0BU,
+	XUSBPSU_LINK_STATE_RESET = 	0x0EU,
+	XUSBPSU_LINK_STATE_RESUME =	0x0FU,
+}XusbPsuLinkState;
+
+typedef enum {
+	XUSBPSU_LINK_STATE_CHANGE_U0 = 0x00U, /**< in HS - ON */
+	XUSBPSU_LINK_STATE_CHANGE_SS_DIS =	0x04U,
+	XUSBPSU_LINK_STATE_CHANGE_RX_DET =	0x05U,
+	XUSBPSU_LINK_STATE_CHANGE_SS_INACT = 0x06U,
+	XUSBPSU_LINK_STATE_CHANGE_RECOV =	0x08U,
+	XUSBPSU_LINK_STATE_CHANGE_CMPLY =	0x0AU,
+}XusbPsuLinkStateChange;
+
+/*
+ * Device States
+ */
+#define		XUSBPSU_STATE_ATTACHED			0U
+#define		XUSBPSU_STATE_POWERED			1U
+#define		XUSBPSU_STATE_DEFAULT			2U
+#define		XUSBPSU_STATE_ADDRESS			3U
+#define		XUSBPSU_STATE_CONFIGURED		4U
+#define		XUSBPSU_STATE_SUSPENDED			5U
+
+/*
+ * Device Speeds
+ */
+#define		XUSBPSU_SPEED_UNKNOWN			0U
+#define		XUSBPSU_SPEED_LOW				1U
+#define		XUSBPSU_SPEED_FULL				2U
+#define		XUSBPSU_SPEED_HIGH				3U
+#define		XUSBPSU_SPEED_SUPER				4U
+
+
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the XUSBPSU
+ * device.
+ */
+typedef struct {
+        u16 DeviceId;           /**< Unique ID of controller */
+        u32 BaseAddress;        /**< Core register base address */
+} XUsbPsu_Config;
+
+/**
+ * Software Event buffer representation
+ */
+struct XUsbPsu_EvtBuffer {
+	void	*BuffAddr;
+	u32		Offset;
+	u32		Count;
+	u32		Flags;
+};
+
+/**
+ * Transfer Request Block - Hardware format
+ */
+struct XUsbPsu_Trb {
+	u32		BufferPtrLow;
+	u32		BufferPtrHigh;
+	u32		Size;
+	u32		Ctrl;
+} __attribute__((packed));
+
+
+/*
+ * Endpoint Parameters
+ */
+struct XUsbPsu_EpParams {
+	u32	Param2;		/**< Parameter 2 */
+	u32	Param1;		/**< Parameter 1 */
+	u32	Param0;		/**< Parameter 0 */
+};
+
+/**
+ * USB Standard Control Request
+ */
+typedef struct {
+        u8  bRequestType;
+        u8  bRequest;
+        u16 wValue;
+        u16 wIndex;
+        u16 wLength;
+} __attribute__ ((packed)) SetupPacket;
+
+/**
+ * Endpoint representation
+ */
+struct XUsbPsu_Ep {
+	void (*Handler)(void *, u32, u32);
+						/** < User handler called
+						 *   when data is sent for IN Ep
+						 *   and received for OUT Ep
+						 */
+	struct XUsbPsu_Trb	EpTrb ALIGNMENT_CACHELINE;/**< TRB used by endpoint */
+	u32	EpStatus;		/**< Flags to represent Endpoint status */
+	u32	RequestedBytes;	/**< RequestedBytes for transfer */
+	u32	BytesTxed;		/**< Actual Bytes transferred */
+	u16	MaxSize;		/**< Size of endpoint */
+	u8	*BufferPtr;		/**< Buffer location */
+	u8	ResourceIndex;	/**< Resource Index assigned to
+						 *  Endpoint by core
+						 */
+	u8	PhyEpNum;		/**< Physical Endpoint Number in core */
+	u8	UsbEpNum;		/**< USB Endpoint Number */
+	u8	Type;			/**< Type of Endpoint -
+						 *	 Control/BULK/INTERRUPT/ISOC
+						 */
+	u8	Direction;		/**< Direction - EP_DIR_OUT/EP_DIR_IN */
+	u8	UnalignedTx;
+};
+
+/**
+ * USB Device Controller representation
+ */
+struct XUsbPsu {
+	SetupPacket SetupData ALIGNMENT_CACHELINE;
+					/**< Setup Packet buffer */
+	struct XUsbPsu_Trb Ep0_Trb ALIGNMENT_CACHELINE;
+					/**< TRB for control transfers */
+	XUsbPsu_Config *ConfigPtr;	/**< Configuration info pointer */
+	struct XUsbPsu_Ep eps[XUSBPSU_ENDPOINTS_NUM]; /**< Endpoints */
+	struct XUsbPsu_EvtBuffer Evt;
+	struct XUsbPsu_EpParams EpParams;
+	u32 BaseAddress;	/**< Core register base address */
+	u32 DevDescSize;
+	u32 ConfigDescSize;
+	void (*Chapter9)(struct XUsbPsu *, SetupPacket *);
+	void (*ClassHandler)(struct XUsbPsu *, SetupPacket *);
+	void *DevDesc;
+	void *ConfigDesc;
+	u8 EventBuffer[XUSBPSU_EVENT_BUFFERS_SIZE]
+						__attribute__((aligned(XUSBPSU_EVENT_BUFFERS_SIZE)));
+	u8 NumOutEps;
+	u8 NumInEps;
+	u8 ControlDir;
+	u8 IsInTestMode;
+	u8 TestMode;
+	u8 Speed;
+	u8 State;
+	u8 Ep0State;
+	u8 LinkState;
+	u8 UnalignedTx;
+	u8 IsConfigDone;
+	u8 IsThreeStage;
+};
+
+struct XUsbPsu_Event_Type {
+	u32	Is_DevEvt:1;
+	u32	Type:7;
+	u32	Reserved8_31:24;
+} __attribute__((packed));
+
+/**
+ * struct XUsbPsu_event_depvt - Device Endpoint Events
+ * @Is_EpEvt: indicates this is an endpoint event
+ * @endpoint_number: number of the endpoint
+ * @endpoint_event: The event we have:
+ *	0x00	- Reserved
+ *	0x01	- XferComplete
+ *	0x02	- XferInProgress
+ *	0x03	- XferNotReady
+ *	0x04	- RxTxFifoEvt (IN->Underrun, OUT->Overrun)
+ *	0x05	- Reserved
+ *	0x06	- StreamEvt
+ *	0x07	- EPCmdCmplt
+ * @Reserved11_10: Reserved, don't use.
+ * @Status: Indicates the status of the event. Refer to databook for
+ *	more information.
+ * @Parameters: Parameters of the current event. Refer to databook for
+ *	more information.
+ */
+struct XUsbPsu_Event_Epevt {
+	u32	Is_EpEvt:1;
+	u32	Epnumber:5;
+	u32	Endpoint_Event:4;
+	u32	Reserved11_10:2;
+	u32	Status:4;
+	u32	Parameters:16;
+} __attribute__((packed));
+
+/**
+ * struct XUsbPsu_event_devt - Device Events
+ * @Is_DevEvt: indicates this is a non-endpoint event
+ * @Device_Event: indicates it's a device event. Should read as 0x00
+ * @Type: indicates the type of device event.
+ *	0	- DisconnEvt
+ *	1	- USBRst
+ *	2	- ConnectDone
+ *	3	- ULStChng
+ *	4	- WkUpEvt
+ *	5	- Reserved
+ *	6	- EOPF
+ *	7	- SOF
+ *	8	- Reserved
+ *	9	- ErrticErr
+ *	10	- CmdCmplt
+ *	11	- EvntOverflow
+ *	12	- VndrDevTstRcved
+ * @Reserved15_12: Reserved, not used
+ * @Event_Info: Information about this event
+ * @Reserved31_25: Reserved, not used
+ */
+struct XUsbPsu_Event_Devt {
+	u32	Is_DevEvt:1;
+	u32	Device_Event:7;
+	u32	Type:4;
+	u32	Reserved15_12:4;
+	u32	Event_Info:9;
+	u32	Reserved31_25:7;
+} __attribute__((packed));
+
+/**
+ * struct XUsbPsu_event_gevt - Other Core Events
+ * @one_bit: indicates this is a non-endpoint event (not used)
+ * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
+ * @phy_port_number: self-explanatory
+ * @reserved31_12: Reserved, not used.
+ */
+struct XUsbPsu_Event_Gevt {
+	u32	Is_GlobalEvt:1;
+	u32	Device_Event:7;
+	u32	Phy_Port_Number:4;
+	u32	Reserved31_12:20;
+} __attribute__((packed));
+
+/**
+ * union XUsbPsu_event - representation of Event Buffer contents
+ * @raw: raw 32-bit event
+ * @type: the type of the event
+ * @depevt: Device Endpoint Event
+ * @devt: Device Event
+ * @gevt: Global Event
+ */
+union XUsbPsu_Event {
+	u32				Raw;
+	struct XUsbPsu_Event_Type	Type;
+	struct XUsbPsu_Event_Epevt	Epevt;
+	struct XUsbPsu_Event_Devt	Devt;
+	struct XUsbPsu_Event_Gevt	Gevt;
+};
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define IS_ALIGNED(x, a)	(((x) & ((typeof(x))(a) - 1)) == 0U)
+
+#define roundup(x, y) (                                 \
+{                                                       \
+        const typeof(y) y__ = (y);                        \
+        (((x) + (u32)(y__ - 1)) / (u32)y__) * (u32)y__;                \
+}                                                       \
+)
+
+#define DECLARE_DEV_DESC(Instance, desc)			\
+	(Instance).DevDesc = &(desc); 					\
+	(Instance).DevDescSize = sizeof((desc))
+
+#define DECLARE_CONFIG_DESC(Instance, desc) 		\
+	(Instance).ConfigDesc = &(desc); 				\
+	(Instance).ConfigDescSize = sizeof((desc))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Functions in xusbpsu.c
+ */
+s32 XUsbPsu_Wait_Clear_Timeout(struct XUsbPsu *InstancePtr, u32 Offset,
+								u32 BitMask, u32 Timeout);
+s32 XUsbPsu_Wait_Set_Timeout(struct XUsbPsu *InstancePtr, u32 Offset,
+								u32 BitMask, u32 Timeout);
+void XUsbPsu_SetMode(struct XUsbPsu *InstancePtr, u32 Mode);
+void XUsbPsu_PhyReset(struct XUsbPsu *InstancePtr);
+void XUsbPsu_EventBuffersSetup(struct XUsbPsu *InstancePtr);
+void XUsbPsu_EventBuffersReset(struct XUsbPsu *InstancePtr);
+void XUsbPsu_CoreNumEps(struct XUsbPsu *InstancePtr);
+void XUsbPsu_cache_hwparams(struct XUsbPsu *InstancePtr);
+u32 XUsbPsu_ReadHwParams(struct XUsbPsu *InstancePtr, u8 RegIndex);
+s32 XUsbPsu_CoreInit(struct XUsbPsu *InstancePtr);
+void XUsbPsu_EnableIntr(struct XUsbPsu *InstancePtr, u32 Mask);
+void XUsbPsu_DisableIntr(struct XUsbPsu *InstancePtr, u32 Mask);
+s32 XUsbPsu_CfgInitialize(struct XUsbPsu *InstancePtr,
+			XUsbPsu_Config *ConfigPtr, u32 BaseAddress);
+s32 XUsbPsu_Start(struct XUsbPsu *InstancePtr);
+s32 XUsbPsu_Stop(struct XUsbPsu *InstancePtr);
+s32 XUsbPsu_SetTestMode(struct XUsbPsu *InstancePtr, u32 Mode);
+XusbPsuLinkState XUsbPsu_GetLinkState(struct XUsbPsu *InstancePtr);
+s32 XUsbPsu_SetLinkState(struct XUsbPsu *InstancePtr,
+		XusbPsuLinkStateChange State);
+s32 XUsbPsu_SendGenericCmd(struct XUsbPsu *InstancePtr,
+					s32 Cmd, u32 Param);
+void XUsbPsu_SetSpeed(struct XUsbPsu *InstancePtr, u32 Speed);
+s32 XUsbPsu_SetDeviceAddress(struct XUsbPsu *InstancePtr, u16 Addr);
+s32 XUsbPsu_IsSuperSpeed(struct XUsbPsu *InstancePtr);
+s32 XUsbPsu_SetU1SleepTimeout(struct XUsbPsu *InstancePtr, u8 Sleep);
+s32 XUsbPsu_SetU2SleepTimeout(struct XUsbPsu *InstancePtr, u8 Sleep);
+s32 XUsbPsu_AcceptU1U2Sleep(struct XUsbPsu *InstancePtr);
+s32 XUsbPsu_U1SleepEnable(struct XUsbPsu *InstancePtr);
+s32 XUsbPsu_U2SleepEnable(struct XUsbPsu *InstancePtr);
+s32 XUsbPsu_U1SleepDisable(struct XUsbPsu *InstancePtr);
+s32 XUsbPsu_U2SleepDisable(struct XUsbPsu *InstancePtr);
+
+/*
+ * Functions in xusbpsu_endpoint.c
+ */
+struct XUsbPsu_EpParams *XUsbPsu_GetEpParams(struct XUsbPsu *InstancePtr);
+u32 XUsbPsu_EpGetTransferIndex(struct XUsbPsu *InstancePtr, u8 UsbEpNum,
+				u8 Dir);
+const char *XUsbPsu_EpCmdString(u8 Cmd);
+s32 XUsbPsu_SendEpCmd(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir,
+			u32 Cmd, struct XUsbPsu_EpParams *Params);
+s32 XUsbPsu_StartEpConfig(struct XUsbPsu *InstancePtr, u32 UsbEpNum,
+				u8 Dir);
+s32 XUsbPsu_SetEpConfig(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir,
+				u16 Size, u8 Type);
+s32 XUsbPsu_SetXferResource(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir);
+s32 XUsbPsu_EpEnable(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir,
+			u16 Maxsize, u8 Type);
+s32 XUsbPsu_EpDisable(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir);
+s32 XUsbPsu_EnableControlEp(struct XUsbPsu *InstancePtr, u16 Size);
+void XUsbPsu_InitializeEps(struct XUsbPsu *InstancePtr);
+void XUsbPsu_StopTransfer(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir);
+void XUsbPsu_ClearStalls(struct XUsbPsu *InstancePtr);
+s32 XUsbPsu_EpBufferSend(struct XUsbPsu *InstancePtr, u8 UsbEp,
+			u8 *BufferPtr, u32 BufferLen);
+s32 XUsbPsu_EpBufferRecv(struct XUsbPsu *InstancePtr, u8 UsbEp,
+				u8 *BufferPtr, u32 Length);
+void XUsbPsu_EpSetStall(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir);
+void XUsbPsu_EpClearStall(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir);
+void XUsbPsu_SetEpHandler(struct XUsbPsu *InstancePtr, u8 Epnum,
+			u8 Dir, void (*Handler)(void *, u32, u32));
+s32 XUsbPsu_IsEpStalled(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir);
+void XUsbPsu_EpXferComplete(struct XUsbPsu *InstancePtr,
+							const struct XUsbPsu_Event_Epevt *Event);
+
+/*
+ * Functions in xusbpsu_controltransfers.c
+ */
+s32 XUsbPsu_RecvSetup(struct XUsbPsu *InstancePtr);
+void XUsbPsu_Ep0StallRestart(struct XUsbPsu *InstancePtr);
+s32 XUsbPsu_SetConfiguration(struct XUsbPsu *InstancePtr,
+				SetupPacket *Ctrl);
+void XUsbPsu_Ep0DataDone(struct XUsbPsu *InstancePtr,
+		const struct XUsbPsu_Event_Epevt *Event);
+void XUsbPsu_Ep0StatusDone(struct XUsbPsu *InstancePtr,
+		const struct XUsbPsu_Event_Epevt *Event);
+void XUsbPsu_Ep0XferComplete(struct XUsbPsu *InstancePtr,
+			const struct XUsbPsu_Event_Epevt *Event);
+s32 XUsbPsu_Ep0StartStatus(struct XUsbPsu *InstancePtr,
+				const struct XUsbPsu_Event_Epevt *Event);
+void XUsbPsu_Ep0_EndControlData(struct XUsbPsu *InstancePtr,
+					struct XUsbPsu_Ep *Ept);
+void XUsbPsu_Ep0XferNotReady(struct XUsbPsu *InstancePtr,
+		const struct XUsbPsu_Event_Epevt *Event);
+void XUsbPsu_Ep0Intr(struct XUsbPsu *InstancePtr,
+		const struct XUsbPsu_Event_Epevt *Event);
+s32 XUsbPsu_Ep0Send(struct XUsbPsu *InstancePtr, u8 *BufferPtr,
+			u32 BufferLen);
+s32 XUsbPsu_Ep0Recv(struct XUsbPsu *InstancePtr, u8 *BufferPtr, u32 Length);
+void XUsbSleep(u32 USeconds);
+
+/*
+ * Functions in xusbpsu_intr.c
+ */
+void XUsbPsu_EpInterrupt(struct XUsbPsu *InstancePtr,
+		const struct XUsbPsu_Event_Epevt *Event);
+void XUsbPsu_DisconnectIntr(struct XUsbPsu *InstancePtr);
+void XUsbPsu_ResetIntr(struct XUsbPsu *InstancePtr);
+void XUsbPsu_ConnDoneIntr(struct XUsbPsu *InstancePtr);
+void XUsbPsu_LinkStsChangeIntr(struct XUsbPsu *InstancePtr,
+				u32 EvtInfo);
+void XUsbPsu_DevInterrupt(struct XUsbPsu *InstancePtr,
+		const struct XUsbPsu_Event_Devt *Event);
+void XUsbPsu_EventHandler(struct XUsbPsu *InstancePtr,
+                const union XUsbPsu_Event *Event);
+void XUsbPsu_EventBufferHandler(struct XUsbPsu *InstancePtr);
+void XUsbPsu_IntrHandler(void *XUsbPsuInstancePtr);
+
+/*
+ * Functions in xusbpsu_sinit.c
+ */
+XUsbPsu_Config *XUsbPsu_LookupConfig(u16 DeviceId);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* End of protection macro. */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_controltransfers.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_controltransfers.c
new file mode 100644
index 000000000..b3a93dc63
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_controltransfers.c
@@ -0,0 +1,681 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xusbpsu_controltransfers.c
+* @addtogroup usbpsu_v1_0
+* @{
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.0   sg  06/06/16 First release
+*
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xusbpsu.h"
+#include "xusbpsu_endpoint.h"
+/************************** Constant Definitions *****************************/
+
+#define USB_DIR_OUT				0U		/* to device */
+#define USB_DIR_IN				0x80U	/* to host */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/****************************************************************************/
+/**
+* Initiates DMA on Control Endpoint 0 to receive Setup packet.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	XST_SUCCESS else XST_FAILURE.
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XUsbPsu_RecvSetup(struct XUsbPsu *InstancePtr)
+{
+	struct XUsbPsu_EpParams *Params;
+	struct XUsbPsu_Trb	*TrbPtr;
+	struct XUsbPsu_Ep	*Ept;
+	s32	Ret;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	Params = XUsbPsu_GetEpParams(InstancePtr);
+	Xil_AssertNonvoid(Params != NULL);
+
+	/* Setup packet always on EP0 */
+	Ept = &InstancePtr->eps[0];
+	if ((Ept->EpStatus & XUSBPSU_EP_BUSY) != 0U) {
+		return XST_FAILURE;
+	}
+
+	TrbPtr = &InstancePtr->Ep0_Trb;
+
+	TrbPtr->BufferPtrLow = (UINTPTR)&InstancePtr->SetupData;
+	TrbPtr->BufferPtrHigh = ((UINTPTR)&InstancePtr->SetupData >> 16) >> 16;
+	TrbPtr->Size = 8U;
+	TrbPtr->Ctrl = XUSBPSU_TRBCTL_CONTROL_SETUP;
+
+	TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO
+			| XUSBPSU_TRB_CTRL_LST
+			| XUSBPSU_TRB_CTRL_IOC
+			| XUSBPSU_TRB_CTRL_ISP_IMI);
+
+	Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb));
+
+	Params->Param0 = 0U;
+	Params->Param1 = (UINTPTR)TrbPtr;
+
+	InstancePtr->Ep0State = XUSBPSU_EP0_SETUP_PHASE;
+
+	Ret = XUsbPsu_SendEpCmd(InstancePtr, 0U, XUSBPSU_EP_DIR_OUT,
+				XUSBPSU_DEPCMD_STARTTRANSFER, Params);
+	if (Ret != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	Ept->EpStatus |= XUSBPSU_EP_BUSY;
+	Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr,
+						Ept->UsbEpNum, Ept->Direction);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Stalls Control Endpoint and restarts to receive Setup packet.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	None
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_Ep0StallRestart(struct XUsbPsu *InstancePtr)
+{
+	struct XUsbPsu_Ep		*Ept;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	/* reinitialize physical ep1 */
+	Ept = &InstancePtr->eps[1];
+	Ept->EpStatus = XUSBPSU_EP_ENABLED;
+
+	/* stall is always issued on EP0 */
+	XUsbPsu_EpSetStall(InstancePtr, 0U, XUSBPSU_EP_DIR_OUT);
+
+	Ept = &InstancePtr->eps[0];
+	Ept->EpStatus = XUSBPSU_EP_ENABLED;
+	InstancePtr->Ep0State = XUSBPSU_EP0_SETUP_PHASE;
+	(void)XUsbPsu_RecvSetup(InstancePtr);
+}
+
+/****************************************************************************/
+/**
+* Checks the Data Phase and calls user Endpoint handler.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Event is a pointer to the Endpoint event occured in core.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_Ep0DataDone(struct XUsbPsu *InstancePtr,
+						 const struct XUsbPsu_Event_Epevt *Event)
+{
+	struct XUsbPsu_Ep	*Ept;
+	struct XUsbPsu_Trb	*TrbPtr;
+	u32	Status;
+	u32	Length;
+	u32	Epnum;
+	u8	Dir;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Event != NULL);
+
+	Epnum = Event->Epnumber;
+	Dir = (u8)(!!Epnum);
+	Ept = &InstancePtr->eps[Epnum];
+	TrbPtr = &InstancePtr->Ep0_Trb;
+
+	Xil_DCacheInvalidateRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb));
+
+	Status = XUSBPSU_TRB_SIZE_TRBSTS(TrbPtr->Size);
+	if (Status == XUSBPSU_TRBSTS_SETUP_PENDING) {
+		return;
+	}
+
+	Length = TrbPtr->Size & XUSBPSU_TRB_SIZE_MASK;
+
+	if (Length == 0U) {
+		Ept->BytesTxed = Ept->RequestedBytes;
+	} else {
+		if (Dir == XUSBPSU_EP_DIR_IN) {
+			Ept->BytesTxed = Ept->RequestedBytes - Length;
+		} else if (Dir == XUSBPSU_EP_DIR_OUT) {
+			if (Ept->UnalignedTx == 1U) {
+				Ept->BytesTxed = Ept->RequestedBytes;
+				Ept->UnalignedTx = 0U;
+			}
+		}
+	}
+
+	if (Dir == XUSBPSU_EP_DIR_OUT) {
+		/* Invalidate Cache */
+		Xil_DCacheInvalidateRange((INTPTR)Ept->BufferPtr, Ept->BytesTxed);
+	}
+
+	if (Ept->Handler != NULL) {
+		Ept->Handler(InstancePtr, Ept->RequestedBytes, Ept->BytesTxed);
+	}
+}
+
+/****************************************************************************/
+/**
+* Checks the Status Phase and starts next Control transfer.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Event is a pointer to the Endpoint event occured in core.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_Ep0StatusDone(struct XUsbPsu *InstancePtr,
+		const struct XUsbPsu_Event_Epevt *Event)
+{
+	struct XUsbPsu_Trb	*TrbPtr;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Event != NULL);
+
+	TrbPtr = &InstancePtr->Ep0_Trb;
+
+	if (InstancePtr->IsInTestMode != 0U) {
+		s32 Ret;
+
+		Ret = XUsbPsu_SetTestMode(InstancePtr,
+					InstancePtr->TestMode);
+		if (Ret < 0) {
+			XUsbPsu_Ep0StallRestart(InstancePtr);
+			return;
+		}
+	}
+	Xil_DCacheInvalidateRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb));
+
+	(void)XUsbPsu_RecvSetup(InstancePtr);
+}
+
+/****************************************************************************/
+/**
+* Handles Transfer complete event of Control Endpoints EP0 OUT and EP0 IN.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Event is a pointer to the Endpoint event occured in core.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_Ep0XferComplete(struct XUsbPsu *InstancePtr,
+							 const struct XUsbPsu_Event_Epevt *Event)
+{
+	struct XUsbPsu_Ep *Ept;
+	SetupPacket *Ctrl;
+	u16 Length;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Event != NULL);
+
+	Ept = &InstancePtr->eps[Event->Epnumber];
+	Ctrl = &InstancePtr->SetupData;
+
+	Ept->EpStatus &= ~XUSBPSU_EP_BUSY;
+	Ept->ResourceIndex = 0U;
+
+	switch (InstancePtr->Ep0State) {
+	case XUSBPSU_EP0_SETUP_PHASE:
+		Xil_DCacheInvalidateRange((INTPTR)&InstancePtr->SetupData,
+					sizeof(InstancePtr->SetupData));
+		Length = Ctrl->wLength;
+		if (Length == 0U) {
+			InstancePtr->IsThreeStage = 0U;
+			InstancePtr->ControlDir = XUSBPSU_EP_DIR_OUT;
+		} else {
+			InstancePtr->IsThreeStage = 1U;
+			InstancePtr->ControlDir = !!(Ctrl->bRequestType &
+							USB_DIR_IN);
+		}
+
+		Xil_AssertVoid(InstancePtr->Chapter9 != NULL);
+
+		InstancePtr->Chapter9(InstancePtr,
+									&InstancePtr->SetupData);
+		break;
+
+	case XUSBPSU_EP0_DATA_PHASE:
+		XUsbPsu_Ep0DataDone(InstancePtr, Event);
+		break;
+
+	case XUSBPSU_EP0_STATUS_PHASE:
+		XUsbPsu_Ep0StatusDone(InstancePtr, Event);
+		break;
+
+	default:
+		/* Default case is a required MISRA-C guideline. */
+		break;
+	}
+}
+
+/****************************************************************************/
+/**
+* Starts Status Phase of Control Transfer
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Event is a pointer to the Endpoint event occured in core.
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XUsbPsu_Ep0StartStatus(struct XUsbPsu *InstancePtr,
+				const struct XUsbPsu_Event_Epevt *Event)
+{
+	struct XUsbPsu_Ep  *Ept;
+	struct XUsbPsu_EpParams *Params;
+	struct XUsbPsu_Trb *TrbPtr;
+	u32 Type;
+	s32 Ret;
+	u8 Dir;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Event != NULL);
+
+	Ept = &InstancePtr->eps[Event->Epnumber];
+	Params = XUsbPsu_GetEpParams(InstancePtr);
+	Xil_AssertNonvoid(Params != NULL);
+	if ((Ept->EpStatus & XUSBPSU_EP_BUSY) != 0U) {
+		return XST_FAILURE;
+	}
+
+	Type = (InstancePtr->IsThreeStage != 0U) ? XUSBPSU_TRBCTL_CONTROL_STATUS3
+					: XUSBPSU_TRBCTL_CONTROL_STATUS2;
+	TrbPtr = &InstancePtr->Ep0_Trb;
+	/* we use same TrbPtr for setup packet */
+	TrbPtr->BufferPtrLow = (UINTPTR)&InstancePtr->SetupData;
+	TrbPtr->BufferPtrHigh = ((UINTPTR)&InstancePtr->SetupData >> 16) >> 16;
+	TrbPtr->Size = 0U;
+	TrbPtr->Ctrl = Type;
+
+	TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO
+			| XUSBPSU_TRB_CTRL_LST
+			| XUSBPSU_TRB_CTRL_IOC
+			| XUSBPSU_TRB_CTRL_ISP_IMI);
+
+	Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb));
+
+	Params->Param0 = 0U;
+	Params->Param1 = (UINTPTR)TrbPtr;
+
+	InstancePtr->Ep0State = XUSBPSU_EP0_STATUS_PHASE;
+
+	/*
+	 * Control OUT transfer - Status stage happens on EP0 IN - EP1
+	 * Control IN transfer - Status stage happens on EP0 OUT - EP0
+	 */
+	Dir = !InstancePtr->ControlDir;
+
+	Ret = XUsbPsu_SendEpCmd(InstancePtr, 0U, Dir,
+							XUSBPSU_DEPCMD_STARTTRANSFER, Params);
+	if (Ret != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	Ept->EpStatus |= XUSBPSU_EP_BUSY;
+	Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr,
+							Ept->UsbEpNum, Ept->Direction);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Ends Data Phase - used incase of error.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Dep is a pointer to the Endpoint structure.
+*
+* @return	None
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_Ep0_EndControlData(struct XUsbPsu *InstancePtr,
+								struct XUsbPsu_Ep *Ept)
+{
+	struct XUsbPsu_EpParams *Params;
+	u32	Cmd;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Ept != NULL);
+
+	if (Ept->ResourceIndex == 0U) {
+		return;
+	}
+
+	Params = XUsbPsu_GetEpParams(InstancePtr);
+	Xil_AssertVoid(Params != NULL);
+
+	Cmd = XUSBPSU_DEPCMD_ENDTRANSFER;
+	Cmd |= XUSBPSU_DEPCMD_PARAM(Ept->ResourceIndex);
+	(void)XUsbPsu_SendEpCmd(InstancePtr, Ept->UsbEpNum, Ept->Direction,
+						Cmd, Params);
+	Ept->ResourceIndex = 0U;
+	XUsbSleep(200U);
+}
+
+/****************************************************************************/
+/**
+* Handles Transfer Not Ready event of Control Endpoints EP0 OUT and EP0 IN.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Event is a pointer to the Endpoint event occured in core.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_Ep0XferNotReady(struct XUsbPsu *InstancePtr,
+							 const struct XUsbPsu_Event_Epevt *Event)
+{
+	struct XUsbPsu_Ep *Ept;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Event != NULL);
+
+	Ept = &InstancePtr->eps[Event->Epnumber];
+
+	switch (Event->Status) {
+	case DEPEVT_STATUS_CONTROL_DATA:
+		/*
+		 * We already have a DATA transfer in the controller's cache,
+		 * if we receive a XferNotReady(DATA) we will ignore it, unless
+		 * it's for the wrong direction.
+		 *
+		 * In that case, we must issue END_TRANSFER command to the Data
+		 * Phase we already have started and issue SetStall on the
+		 * control endpoint.
+		 */
+		if (Event->Epnumber != InstancePtr->ControlDir) {
+			XUsbPsu_Ep0_EndControlData(InstancePtr, Ept);
+			XUsbPsu_Ep0StallRestart(InstancePtr);
+		}
+		break;
+
+	case DEPEVT_STATUS_CONTROL_STATUS:
+		(void)XUsbPsu_Ep0StartStatus(InstancePtr, Event);
+		break;
+
+	default:
+		/* Default case is a required MIRSA-C guideline. */
+		break;
+	}
+}
+
+/****************************************************************************/
+/**
+* Handles Interrupts of Control Endpoints EP0 OUT and EP0 IN.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Event is a pointer to the Endpoint event occured in core.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_Ep0Intr(struct XUsbPsu *InstancePtr,
+		const struct XUsbPsu_Event_Epevt *Event)
+{
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Event != NULL);
+
+	switch (Event->Endpoint_Event) {
+	case XUSBPSU_DEPEVT_XFERCOMPLETE:
+		XUsbPsu_Ep0XferComplete(InstancePtr, Event);
+		break;
+
+	case XUSBPSU_DEPEVT_XFERNOTREADY:
+		XUsbPsu_Ep0XferNotReady(InstancePtr, Event);
+		break;
+
+	case XUSBPSU_DEPEVT_XFERINPROGRESS:
+	case XUSBPSU_DEPEVT_STREAMEVT:
+	case XUSBPSU_DEPEVT_EPCMDCMPLT:
+		break;
+
+	default:
+		/* Default case is a required MIRSA-C guideline. */
+		break;
+	}
+}
+
+/****************************************************************************/
+/**
+* Initiates DMA to send data on Control Endpoint EP0 IN to Host.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	BufferPtr is pointer to data.
+* @param	BufferLen is Length of data buffer.
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XUsbPsu_Ep0Send(struct XUsbPsu *InstancePtr, u8 *BufferPtr, u32 BufferLen)
+{
+	/* Control IN - EP1 */
+	struct XUsbPsu_EpParams *Params;
+	struct XUsbPsu_Ep 	*Ept;
+	struct XUsbPsu_Trb	*TrbPtr;
+	s32 Ret;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(BufferPtr != NULL);
+
+	Ept = &InstancePtr->eps[1];
+	Params = XUsbPsu_GetEpParams(InstancePtr);
+	Xil_AssertNonvoid(Params != NULL);
+
+	if ((Ept->EpStatus & XUSBPSU_EP_BUSY) != 0U) {
+		return XST_FAILURE;
+	}
+
+	Ept->RequestedBytes = BufferLen;
+	Ept->BytesTxed = 0U;
+	Ept->BufferPtr = BufferPtr;
+
+	TrbPtr = &InstancePtr->Ep0_Trb;
+
+	TrbPtr->BufferPtrLow  = (UINTPTR)BufferPtr;
+	TrbPtr->BufferPtrHigh  = ((UINTPTR)BufferPtr >> 16) >> 16;
+	TrbPtr->Size = BufferLen;
+	TrbPtr->Ctrl = XUSBPSU_TRBCTL_CONTROL_DATA;
+
+	TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO
+			| XUSBPSU_TRB_CTRL_LST
+			| XUSBPSU_TRB_CTRL_IOC
+			| XUSBPSU_TRB_CTRL_ISP_IMI);
+
+	Params->Param0 = 0U;
+	Params->Param1 = (UINTPTR)TrbPtr;
+
+	Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb));
+	Xil_DCacheFlushRange((INTPTR)BufferPtr, BufferLen);
+
+	InstancePtr->Ep0State = XUSBPSU_EP0_DATA_PHASE;
+
+	Ret = XUsbPsu_SendEpCmd(InstancePtr, 0U, XUSBPSU_EP_DIR_IN,
+							XUSBPSU_DEPCMD_STARTTRANSFER, Params);
+	if (Ret != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	Ept->EpStatus |= XUSBPSU_EP_BUSY;
+	Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr,
+						Ept->UsbEpNum, Ept->Direction);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Initiates DMA to receive data on Control Endpoint EP0 OUT from Host.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	BufferPtr is pointer to data.
+* @param	Length is Length of data to be received.
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XUsbPsu_Ep0Recv(struct XUsbPsu *InstancePtr, u8 *BufferPtr, u32 Length)
+{
+	struct XUsbPsu_EpParams *Params;
+	struct XUsbPsu_Ep 	*Ept;
+	struct XUsbPsu_Trb	*TrbPtr;
+	u32 Size;
+	s32 Ret;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(BufferPtr != NULL);
+
+	Ept = &InstancePtr->eps[0];
+	Params = XUsbPsu_GetEpParams(InstancePtr);
+	Xil_AssertNonvoid(Params != NULL);
+
+	if ((Ept->EpStatus & XUSBPSU_EP_BUSY) != 0U) {
+		return XST_FAILURE;
+	}
+
+	Ept->RequestedBytes = Length;
+	Size = Length;
+	Ept->BytesTxed = 0U;
+	Ept->BufferPtr = BufferPtr;
+
+	/*
+	 * 8.2.5 - An OUT transfer size (Total TRB buffer allocation)
+	 * must be a multiple of MaxPacketSize even if software is expecting a
+	 * fixed non-multiple of MaxPacketSize transfer from the Host.
+	 */
+	if (!IS_ALIGNED(Length, Ept->MaxSize)) {
+		Size = (u32)roundup(Length, Ept->MaxSize);
+		InstancePtr->UnalignedTx = 1U;
+	}
+
+	TrbPtr = &InstancePtr->Ep0_Trb;
+
+	TrbPtr->BufferPtrLow = (UINTPTR)BufferPtr;
+	TrbPtr->BufferPtrHigh = ((UINTPTR)BufferPtr >> 16) >> 16;
+	TrbPtr->Size = Size;
+	TrbPtr->Ctrl = XUSBPSU_TRBCTL_CONTROL_DATA;
+
+	TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO
+			| XUSBPSU_TRB_CTRL_LST
+			| XUSBPSU_TRB_CTRL_IOC
+			| XUSBPSU_TRB_CTRL_ISP_IMI);
+
+	Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb));
+	Xil_DCacheInvalidateRange((INTPTR)BufferPtr, Length);
+
+	Params->Param0 = 0U;
+	Params->Param1 = (UINTPTR)TrbPtr;
+
+	InstancePtr->Ep0State = XUSBPSU_EP0_DATA_PHASE;
+
+	Ret = XUsbPsu_SendEpCmd(InstancePtr, 0U, XUSBPSU_EP_DIR_OUT,
+				XUSBPSU_DEPCMD_STARTTRANSFER, Params);
+	if (Ret != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+
+	Ept->EpStatus |= XUSBPSU_EP_BUSY;
+	Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr,
+							Ept->UsbEpNum, Ept->Direction);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* API for Sleep routine.
+*
+* @param	USeconds is time in MicroSeconds.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XUsbSleep(u32 USeconds) {
+	(void)usleep(USeconds);
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.c
new file mode 100644
index 000000000..41368e526
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.c
@@ -0,0 +1,927 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+*****************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xusbpsu_endpoint.c
+* @addtogroup usbpsu_v1_0
+* @{
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.0   sg  06/06/16 First release
+*
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xusbpsu.h"
+#include "xusbpsu_endpoint.h"
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/* return Physical EP number as dwc3 mapping */
+#define PhysicalEp(epnum, direction)	(((epnum) << 1 ) | (direction))
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/****************************************************************************/
+/**
+* Returns zeroed parameters to be used by Endpoint commands
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	Zeroed Params structure pointer.
+*
+* @note		None.
+*
+*****************************************************************************/
+struct XUsbPsu_EpParams *XUsbPsu_GetEpParams(struct XUsbPsu *InstancePtr)
+{
+	if (InstancePtr == NULL) {
+		return NULL;
+	}
+
+	InstancePtr->EpParams.Param0 = 0x00U;
+	InstancePtr->EpParams.Param1 = 0x00U;
+	InstancePtr->EpParams.Param2 = 0x00U;
+
+	return &InstancePtr->EpParams;
+}
+
+/****************************************************************************/
+/**
+* Returns Transfer Index assigned by Core for an Endpoint transfer.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	UsbEpNum is USB endpoint number.
+* @param	Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT
+*
+* @return	Transfer Resource Index.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XUsbPsu_EpGetTransferIndex(struct XUsbPsu *InstancePtr, u8 UsbEpNum,
+								u8 Dir)
+{
+	u8 PhyEpNum;
+	u32 ResourceIndex;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(UsbEpNum <= (u8)16U);
+	Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) ||
+						(Dir == XUSBPSU_EP_DIR_OUT));
+
+	PhyEpNum = (u8)PhysicalEp(UsbEpNum, Dir);
+	ResourceIndex = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DEPCMD(PhyEpNum));
+
+	return (u32)XUSBPSU_DEPCMD_GET_RSC_IDX(ResourceIndex);
+}
+
+/****************************************************************************/
+/**
+* Sends Endpoint command to Endpoint.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	UsbEpNum is USB endpoint number.
+* @param	Dir is direction of endpoint
+*			- XUSBPSU_EP_DIR_IN/ XUSBPSU_EP_DIR_OUT.
+* @param	Cmd is Endpoint command.
+* @param	Params is Endpoint command parameters.
+*
+* @return	XST_SUCCESS else XST_FAILURE.
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XUsbPsu_SendEpCmd(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir,
+					  u32 Cmd, struct XUsbPsu_EpParams *Params)
+{
+	u32	PhyEpNum;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(UsbEpNum <= (u8)16U);
+	Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) ||
+					  (Dir == XUSBPSU_EP_DIR_OUT));
+
+	PhyEpNum = PhysicalEp(UsbEpNum, Dir);
+
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DEPCMDPAR0(PhyEpNum),
+					 Params->Param0);
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DEPCMDPAR1(PhyEpNum),
+					 Params->Param1);
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DEPCMDPAR2(PhyEpNum),
+					 Params->Param2);
+
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DEPCMD(PhyEpNum),
+			Cmd | XUSBPSU_DEPCMD_CMDACT);
+
+	if (XUsbPsu_Wait_Clear_Timeout(InstancePtr, XUSBPSU_DEPCMD(PhyEpNum),
+			XUSBPSU_DEPCMD_CMDACT, 500U) == (s32)XST_FAILURE) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Sends Start New Configuration command to Endpoint.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	UsbEpNum is USB endpoint number.
+* @param	Dir is direction of endpoint
+*			- XUSBPSU_EP_DIR_IN/ XUSBPSU_EP_DIR_OUT.
+*
+* @return	XST_SUCCESS else XST_FAILURE.
+*
+* @note
+* 			As per data book this command should be issued by software
+*			under these conditions:
+*				1. After power-on-reset with XferRscIdx=0 before starting
+*				   to configure Physical Endpoints 0 and 1.
+*				2. With XferRscIdx=2 before starting to configure
+*				   Physical Endpoints > 1
+*				3. This command should always be issued to
+*				   Endpoint 0 (DEPCMD0).
+*
+*****************************************************************************/
+s32 XUsbPsu_StartEpConfig(struct XUsbPsu *InstancePtr, u32 UsbEpNum, u8 Dir)
+{
+	struct XUsbPsu_EpParams *Params;
+	u32	Cmd;
+	u8 PhyEpNum;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(UsbEpNum <= (u32)16U);
+	Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) ||
+					  (Dir == XUSBPSU_EP_DIR_OUT));
+
+	PhyEpNum = (u8)PhysicalEp(UsbEpNum, (u32)Dir);
+	Params =  XUsbPsu_GetEpParams(InstancePtr);
+	Xil_AssertNonvoid(Params != NULL);
+
+	if (PhyEpNum != 1U) {
+		Cmd = XUSBPSU_DEPCMD_DEPSTARTCFG;
+		/* XferRscIdx == 0 for EP0 and 2 for the remaining */
+		if (PhyEpNum > 1U) {
+			if (InstancePtr->IsConfigDone != 0U) {
+				return XST_SUCCESS;
+			}
+			InstancePtr->IsConfigDone = 1U;
+			Cmd |= XUSBPSU_DEPCMD_PARAM(2);
+		}
+
+		return XUsbPsu_SendEpCmd(InstancePtr, 0U, XUSBPSU_EP_DIR_OUT,
+								 Cmd, Params);
+	}
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Sends Set Endpoint Configuration command to Endpoint.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	UsbEpNum is USB endpoint number.
+* @param	Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT.
+* @param	Size is size of Endpoint size.
+* @param	Type is Endpoint type Control/Bulk/Interrupt/Isoc.
+*
+* @return	XST_SUCCESS else XST_FAILURE.
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XUsbPsu_SetEpConfig(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir,
+						u16 Size, u8 Type)
+{
+	struct XUsbPsu_EpParams *Params;
+	u8 PhyEpNum;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(UsbEpNum <= (u8)16U);
+	Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) ||
+						(Dir == XUSBPSU_EP_DIR_OUT));
+	Xil_AssertNonvoid((Size >= 64U) && (Size <= 1024U));
+
+	Params = XUsbPsu_GetEpParams(InstancePtr);
+	Xil_AssertNonvoid(Params != NULL);
+
+	PhyEpNum = PhysicalEp(UsbEpNum , Dir);
+
+	Params->Param0 = XUSBPSU_DEPCFG_EP_TYPE(Type)
+		| XUSBPSU_DEPCFG_MAX_PACKET_SIZE(Size);
+
+	/*
+	 * Set burst size to 1 as recommended
+	 */
+	Params->Param0 |= XUSBPSU_DEPCFG_BURST_SIZE(1);
+
+	Params->Param1 = XUSBPSU_DEPCFG_XFER_COMPLETE_EN
+		| XUSBPSU_DEPCFG_XFER_NOT_READY_EN;
+
+	/*
+	 * We are doing 1:1 mapping for endpoints, meaning
+	 * Physical Endpoints 2 maps to Logical Endpoint 2 and
+	 * so on. We consider the direction bit as part of the physical
+	 * endpoint number. So USB endpoint 0x81 is 0x03.
+	 */
+	Params->Param1 |= XUSBPSU_DEPCFG_EP_NUMBER(PhyEpNum);
+
+	if (Dir != XUSBPSU_EP_DIR_OUT) {
+		 Params->Param0 |= XUSBPSU_DEPCFG_FIFO_NUMBER((u32)PhyEpNum >> 1);
+	}
+
+	return XUsbPsu_SendEpCmd(InstancePtr, UsbEpNum, Dir,
+							 XUSBPSU_DEPCMD_SETEPCONFIG, Params);
+}
+
+/****************************************************************************/
+/**
+* Sends Set Transfer Resource command to Endpoint.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	UsbEpNum is USB endpoint number.
+* @param	Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/
+*											XUSBPSU_EP_DIR_OUT.
+*
+* @return	XST_SUCCESS else XST_FAILURE.
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XUsbPsu_SetXferResource(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir)
+{
+	struct XUsbPsu_EpParams *Params;
+
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(UsbEpNum <= (u8)16U);
+	Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) ||
+						(Dir == XUSBPSU_EP_DIR_OUT));
+
+	Params = XUsbPsu_GetEpParams(InstancePtr);
+	Xil_AssertNonvoid(Params != NULL);
+
+	Params->Param0 = XUSBPSU_DEPXFERCFG_NUM_XFER_RES(1);
+
+	return XUsbPsu_SendEpCmd(InstancePtr, UsbEpNum, Dir,
+							 XUSBPSU_DEPCMD_SETTRANSFRESOURCE, Params);
+}
+
+/****************************************************************************/
+/**
+* Enables Endpoint for sending/receiving data.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	UsbEpNum is USB endpoint number.
+* @param	Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT.
+* @param	Maxsize is size of Endpoint size.
+* @param	Type is Endpoint type Control/Bulk/Interrupt/Isoc.
+*
+* @return	XST_SUCCESS else XST_FAILURE.
+*
+* @note		None.
+*
+****************************************************************************/
+s32 XUsbPsu_EpEnable(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir,
+			u16 Maxsize, u8 Type)
+{
+	struct XUsbPsu_Ep *Ept;
+	u32 RegVal;
+	s32 Ret = (s32)XST_FAILURE;
+	u32 PhyEpNum;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(UsbEpNum <= (u8)16U);
+	Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) ||
+					  (Dir == XUSBPSU_EP_DIR_OUT));
+	Xil_AssertNonvoid((Maxsize >= 64U) && (Maxsize <= 1024U));
+
+	PhyEpNum = PhysicalEp(UsbEpNum , Dir);
+	Ept = &InstancePtr->eps[PhyEpNum];
+
+	Ept->UsbEpNum	= UsbEpNum;
+	Ept->Direction	= Dir;
+	Ept->Type	= Type;
+	Ept->MaxSize	= Maxsize;
+	Ept->PhyEpNum	= (u8)PhyEpNum;
+
+	if ((Ept->EpStatus & XUSBPSU_EP_ENABLED) == 0U) {
+		Ret = XUsbPsu_StartEpConfig(InstancePtr, UsbEpNum, Dir);
+		if (Ret != 0) {
+			return Ret;
+		}
+	}
+
+	Ret = XUsbPsu_SetEpConfig(InstancePtr, UsbEpNum, Dir, Maxsize, Type);
+	if (Ret != 0) {
+		return Ret;
+	}
+
+	if ((Ept->EpStatus & XUSBPSU_EP_ENABLED) == 0U) {
+		Ret = XUsbPsu_SetXferResource(InstancePtr, UsbEpNum, Dir);
+		if (Ret != 0) {
+			return Ret;
+		}
+
+		Ept->EpStatus |= XUSBPSU_EP_ENABLED;
+
+		RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DALEPENA);
+		RegVal |= XUSBPSU_DALEPENA_EP(Ept->PhyEpNum);
+		XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DALEPENA, RegVal);
+	}
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Disables Endpoint.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	UsbEpNum is USB endpoint number.
+* @param	Dir is direction of endpoint
+*			- XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT.
+*
+* @return	XST_SUCCESS else XST_FAILURE.
+*
+* @note		None.
+*
+****************************************************************************/
+s32 XUsbPsu_EpDisable(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir)
+{
+	u32	RegVal;
+	u8	PhyEpNum;
+	struct XUsbPsu_Ep *Ept;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(UsbEpNum <= (u8)16U);
+	Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) ||
+						(Dir == XUSBPSU_EP_DIR_OUT));
+
+	PhyEpNum = PhysicalEp(UsbEpNum , Dir);
+	Ept = &InstancePtr->eps[PhyEpNum];
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DALEPENA);
+	RegVal &= ~XUSBPSU_DALEPENA_EP(PhyEpNum);
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DALEPENA, RegVal);
+
+	Ept->Type = 0U;
+	Ept->EpStatus = 0U;
+	Ept->MaxSize = 0U;
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Enables USB Control Endpoint i.e., EP0OUT and EP0IN of Core.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Size is control endpoint size.
+*
+* @return	XST_SUCCESS else XST_FAILURE.
+*
+* @note		None.
+*
+****************************************************************************/
+s32 XUsbPsu_EnableControlEp(struct XUsbPsu *InstancePtr, u16 Size)
+{
+	s32 RetVal;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid((Size >= 64U) && (Size <= 512U));
+
+	RetVal = XUsbPsu_EpEnable(InstancePtr, 0U, XUSBPSU_EP_DIR_OUT, Size,
+				XUSBPSU_ENDPOINT_XFER_CONTROL);
+	if (RetVal != 0) {
+		return XST_FAILURE;
+	}
+
+	RetVal = XUsbPsu_EpEnable(InstancePtr, 0U, XUSBPSU_EP_DIR_IN, Size,
+				XUSBPSU_ENDPOINT_XFER_CONTROL);
+	if (RetVal != 0) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Initializes Endpoints. All OUT endpoints are even numbered and all IN
+* endpoints are odd numbered. EP0 is for Control OUT and EP1 is for
+* Control IN.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XUsbPsu_InitializeEps(struct XUsbPsu *InstancePtr)
+{
+	u8  i;
+	u8 Epnum;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	for (i = 0U; i < InstancePtr->NumOutEps; i++) {
+		Epnum = (i << 1U) | XUSBPSU_EP_DIR_OUT;
+		InstancePtr->eps[Epnum].PhyEpNum = Epnum;
+		InstancePtr->eps[Epnum].Direction = XUSBPSU_EP_DIR_OUT;
+	}
+	for (i = 0U; i < InstancePtr->NumInEps; i++) {
+		Epnum = (i << 1U) | XUSBPSU_EP_DIR_IN;
+		InstancePtr->eps[Epnum].PhyEpNum = Epnum;
+		InstancePtr->eps[Epnum].Direction = XUSBPSU_EP_DIR_IN;
+	}
+}
+
+/****************************************************************************/
+/**
+* Stops transfer on Endpoint.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	UsbEpNum is USB endpoint number.
+* @param	Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XUsbPsu_StopTransfer(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir)
+{
+	struct XUsbPsu_Ep *Ept;
+	struct XUsbPsu_EpParams *Params;
+	u8 PhyEpNum;
+	u32 Cmd;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(UsbEpNum <= (u8)16U);
+	Xil_AssertVoid((Dir == XUSBPSU_EP_DIR_IN) || (Dir == XUSBPSU_EP_DIR_OUT));
+
+	PhyEpNum = PhysicalEp(UsbEpNum, Dir);
+	Params = XUsbPsu_GetEpParams(InstancePtr);
+	Xil_AssertVoid(Params != NULL);
+
+	Ept = &InstancePtr->eps[PhyEpNum];
+
+	if (Ept->ResourceIndex == 0U) {
+		return;
+	}
+
+	/*
+	 * - Issue EndTransfer WITH CMDIOC bit set
+	 * - Wait 100us
+	 */
+	Cmd = XUSBPSU_DEPCMD_ENDTRANSFER;
+	Cmd |= XUSBPSU_DEPCMD_CMDIOC;
+	Cmd |= XUSBPSU_DEPCMD_PARAM(Ept->ResourceIndex);
+	(void)XUsbPsu_SendEpCmd(InstancePtr, Ept->PhyEpNum, Ept->Direction,
+							Cmd, Params);
+	Ept->ResourceIndex = 0U;
+	Ept->EpStatus &= ~XUSBPSU_EP_BUSY;
+	XUsbSleep(100U);
+}
+
+/****************************************************************************/
+/**
+* Clears Stall on all endpoints.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XUsbPsu_ClearStalls(struct XUsbPsu *InstancePtr)
+{
+	struct XUsbPsu_EpParams *Params;
+	u32 Epnum;
+	struct XUsbPsu_Ep *Ept;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	Params = XUsbPsu_GetEpParams(InstancePtr);
+	Xil_AssertVoid(Params != NULL);
+
+	for (Epnum = 1U; Epnum < XUSBPSU_ENDPOINTS_NUM; Epnum++) {
+
+		Ept = &InstancePtr->eps[Epnum];
+		if (Ept == NULL) {
+			continue;
+		}
+
+		if ((Ept->EpStatus & XUSBPSU_EP_STALL) == 0U) {
+			continue;
+		}
+
+		Ept->EpStatus &= ~XUSBPSU_EP_STALL;
+
+		(void)XUsbPsu_SendEpCmd(InstancePtr, Ept->PhyEpNum,
+						  Ept->Direction, XUSBPSU_DEPCMD_CLEARSTALL,
+						  Params);
+	}
+}
+
+/****************************************************************************/
+/**
+* Initiates DMA to send data on endpoint to Host.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	UsbEp is USB endpoint number.
+* @param	BufferPtr is pointer to data.
+* @param	BufferLen is length of data buffer.
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XUsbPsu_EpBufferSend(struct XUsbPsu *InstancePtr, u8 UsbEp,
+						 u8 *BufferPtr, u32 BufferLen)
+{
+	u8	PhyEpNum;
+	s32	RetVal;
+	struct XUsbPsu_Trb	*TrbPtr;
+	struct XUsbPsu_Ep *Ept;
+	struct XUsbPsu_EpParams *Params;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(UsbEp <= (u8)16U);
+	Xil_AssertNonvoid(BufferPtr != NULL);
+
+	PhyEpNum = PhysicalEp(UsbEp, XUSBPSU_EP_DIR_IN);
+	if (PhyEpNum == 1U) {
+		RetVal = XUsbPsu_Ep0Send(InstancePtr, BufferPtr, BufferLen);
+		return RetVal;
+	}
+
+	Ept = &InstancePtr->eps[PhyEpNum];
+
+	if (Ept->Direction != XUSBPSU_EP_DIR_IN) {
+		return XST_FAILURE;
+	}
+
+	Ept->RequestedBytes = BufferLen;
+	Ept->BytesTxed = 0U;
+	Ept->BufferPtr = BufferPtr;
+
+	TrbPtr = &Ept->EpTrb;
+	Xil_AssertNonvoid(TrbPtr != NULL);
+
+	TrbPtr->BufferPtrLow  = (UINTPTR)BufferPtr;
+	TrbPtr->BufferPtrHigh  = ((UINTPTR)BufferPtr >> 16) >> 16;
+	TrbPtr->Size = BufferLen & XUSBPSU_TRB_SIZE_MASK;
+	TrbPtr->Ctrl = XUSBPSU_TRBCTL_NORMAL;
+
+	TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO
+					| XUSBPSU_TRB_CTRL_LST
+					| XUSBPSU_TRB_CTRL_IOC
+					| XUSBPSU_TRB_CTRL_ISP_IMI);
+
+	Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb));
+	Xil_DCacheFlushRange((INTPTR)BufferPtr, BufferLen);
+
+	Params = XUsbPsu_GetEpParams(InstancePtr);
+	Xil_AssertNonvoid(Params != NULL);
+	Params->Param0 = 0U;
+	Params->Param1 = (UINTPTR)TrbPtr;
+
+	RetVal = XUsbPsu_SendEpCmd(InstancePtr, UsbEp, Ept->Direction,
+								XUSBPSU_DEPCMD_STARTTRANSFER, Params);
+	if (RetVal != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+	Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr,
+													Ept->UsbEpNum,
+													Ept->Direction);
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Initiates DMA to receive data on Endpoint from Host.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	EpNum is USB endpoint number.
+* @param	BufferPtr is pointer to data.
+* @param	Length is length of data to be received.
+*
+* @return	XST_SUCCESS else XST_FAILURE
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XUsbPsu_EpBufferRecv(struct XUsbPsu *InstancePtr, u8 UsbEp,
+						 u8 *BufferPtr, u32 Length)
+{
+	u8	PhyEpNum;
+	u32 Size;
+	s32	RetVal;
+	struct XUsbPsu_Trb	*TrbPtr;
+	struct XUsbPsu_Ep *Ept;
+	struct XUsbPsu_EpParams *Params;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(UsbEp <= (u8)16U);
+	Xil_AssertNonvoid(BufferPtr != NULL);
+
+	PhyEpNum = PhysicalEp(UsbEp, XUSBPSU_EP_DIR_OUT);
+	if (PhyEpNum == 0U) {
+		RetVal = XUsbPsu_Ep0Recv(InstancePtr, BufferPtr, Length);
+		return RetVal;
+	}
+
+	Ept = &InstancePtr->eps[PhyEpNum];
+
+	if (Ept->Direction != XUSBPSU_EP_DIR_OUT) {
+		return XST_FAILURE;
+	}
+
+	Ept->RequestedBytes = Length;
+	Size = Length;
+	Ept->BytesTxed = 0U;
+	Ept->BufferPtr = BufferPtr;
+
+	/*
+	 * 8.2.5 - An OUT transfer size (Total TRB buffer allocation)
+	 * must be a multiple of MaxPacketSize even if software is expecting a
+	 * fixed non-multiple of MaxPacketSize transfer from the Host.
+	 */
+	if (!IS_ALIGNED(Length, Ept->MaxSize)) {
+		Size = (u32)roundup(Length, Ept->MaxSize);
+		Ept->UnalignedTx = 1U;
+	}
+
+	TrbPtr = &Ept->EpTrb;
+	Xil_AssertNonvoid(TrbPtr != NULL);
+
+	TrbPtr->BufferPtrLow  = (UINTPTR)BufferPtr;
+	TrbPtr->BufferPtrHigh = ((UINTPTR)BufferPtr >> 16) >> 16;
+	TrbPtr->Size = Size;
+	TrbPtr->Ctrl = XUSBPSU_TRBCTL_NORMAL;
+
+	TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO
+					| XUSBPSU_TRB_CTRL_LST
+					| XUSBPSU_TRB_CTRL_IOC
+					| XUSBPSU_TRB_CTRL_ISP_IMI);
+
+
+	Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb));
+	Xil_DCacheInvalidateRange((INTPTR)BufferPtr, Length);
+
+	Params = XUsbPsu_GetEpParams(InstancePtr);
+	Xil_AssertNonvoid(Params != NULL);
+	Params->Param0 = 0U;
+	Params->Param1 = (UINTPTR)TrbPtr;
+
+	RetVal = XUsbPsu_SendEpCmd(InstancePtr, UsbEp, Ept->Direction,
+								XUSBPSU_DEPCMD_STARTTRANSFER, Params);
+	if (RetVal != XST_SUCCESS) {
+		return XST_FAILURE;
+	}
+	Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr,
+													Ept->UsbEpNum,
+													Ept->Direction);
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* Stalls an Endpoint.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	EpNum is USB endpoint number.
+* @param	Dir	is direction.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_EpSetStall(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir)
+{
+	u8	PhyEpNum;
+	struct XUsbPsu_Ep *Ept = NULL;
+	struct XUsbPsu_EpParams *Params;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Epnum <= (u8)16U);
+	Xil_AssertVoid((Dir == XUSBPSU_EP_DIR_IN) || (Dir == XUSBPSU_EP_DIR_OUT));
+
+	PhyEpNum = PhysicalEp(Epnum, Dir);
+	Ept = &InstancePtr->eps[PhyEpNum];
+
+	Params = XUsbPsu_GetEpParams(InstancePtr);
+	Xil_AssertVoid(Params != NULL);
+
+	(void)XUsbPsu_SendEpCmd(InstancePtr, Ept->PhyEpNum, Ept->Direction,
+							XUSBPSU_DEPCMD_SETSTALL, Params);
+
+	Ept->EpStatus |= XUSBPSU_EP_STALL;
+}
+
+/****************************************************************************/
+/**
+* Clears Stall on an Endpoint.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	EpNum is USB endpoint number.
+* @param	Dir	is direction.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_EpClearStall(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir)
+{
+	u8	PhyEpNum;
+	struct XUsbPsu_Ep *Ept = NULL;
+	struct XUsbPsu_EpParams *Params;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Epnum <= (u8)16U);
+	Xil_AssertVoid((Dir == XUSBPSU_EP_DIR_IN) || (Dir == XUSBPSU_EP_DIR_OUT));
+
+	PhyEpNum = PhysicalEp(Epnum, Dir);
+	Ept = &InstancePtr->eps[PhyEpNum];
+
+	Params = XUsbPsu_GetEpParams(InstancePtr);
+	Xil_AssertVoid(Params != NULL);
+
+	(void)XUsbPsu_SendEpCmd(InstancePtr, Ept->PhyEpNum, Ept->Direction,
+							XUSBPSU_DEPCMD_CLEARSTALL, Params);
+
+	Ept->EpStatus &= ~XUSBPSU_EP_STALL;
+}
+
+/****************************************************************************/
+/**
+* Sets an user handler to be called after data is sent/received by an Endpoint
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	EpNum is USB endpoint number.
+* @param	Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT.
+* @param	Handler is user handler to be called.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_SetEpHandler(struct XUsbPsu *InstancePtr, u8 Epnum,
+			u8 Dir, void (*Handler)(void *, u32, u32))
+{
+	u8 PhyEpNum;
+	struct XUsbPsu_Ep *Ept;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Epnum <= (u8)16U);
+	Xil_AssertVoid((Dir == XUSBPSU_EP_DIR_IN) || (Dir == XUSBPSU_EP_DIR_OUT));
+
+	PhyEpNum = PhysicalEp(Epnum, Dir);
+	Ept = &InstancePtr->eps[PhyEpNum];
+	Ept->Handler = Handler;
+}
+
+/****************************************************************************/
+/**
+* Returns status of endpoint - Stalled or not
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	EpNum is USB endpoint number.
+* @param	Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT.
+*
+* @return
+*			1 - if stalled
+*			0 - if not stalled
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XUsbPsu_IsEpStalled(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir)
+{
+	u8 PhyEpNum;
+	struct XUsbPsu_Ep *Ept;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Epnum <= (u8)16U);
+	Xil_AssertNonvoid((Dir == XUSBPSU_EP_DIR_IN) || (Dir == XUSBPSU_EP_DIR_OUT));
+
+	PhyEpNum = PhysicalEp(Epnum, Dir);
+	Ept = &InstancePtr->eps[PhyEpNum];
+
+	return (s32)(!!(Ept->EpStatus & XUSBPSU_EP_STALL));
+}
+
+/****************************************************************************/
+/**
+* Checks the Data Phase and calls user Endpoint handler.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Event is a pointer to the Endpoint event occured in core.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_EpXferComplete(struct XUsbPsu *InstancePtr,
+							const struct XUsbPsu_Event_Epevt *Event)
+{
+	struct XUsbPsu_Ep	*Ept;
+	struct XUsbPsu_Trb	*TrbPtr;
+	u32	Length;
+	u32	Epnum;
+	u8	Dir;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Event != NULL);
+
+	Epnum = Event->Epnumber;
+	Ept = &InstancePtr->eps[Epnum];
+	Dir = Ept->Direction;
+	TrbPtr = &Ept->EpTrb;
+	Xil_AssertVoid(TrbPtr != NULL);
+
+	Xil_DCacheInvalidateRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb));
+
+	Length = TrbPtr->Size & XUSBPSU_TRB_SIZE_MASK;
+
+	if (Length == 0U) {
+		Ept->BytesTxed = Ept->RequestedBytes;
+	} else {
+		if (Dir == XUSBPSU_EP_DIR_IN) {
+			Ept->BytesTxed = Ept->RequestedBytes - Length;
+		} else if (Dir == XUSBPSU_EP_DIR_OUT) {
+			if (Ept->UnalignedTx == 1U) {
+				Ept->BytesTxed = Ept->RequestedBytes;
+				Ept->UnalignedTx = 0U;
+			}
+		}
+	}
+
+	if (Dir == XUSBPSU_EP_DIR_OUT) {
+		/* Invalidate Cache */
+		Xil_DCacheInvalidateRange((INTPTR)Ept->BufferPtr, Ept->BytesTxed);
+	}
+
+	if (Ept->Handler != NULL) {
+		Ept->Handler(InstancePtr, Ept->RequestedBytes, Ept->BytesTxed);
+	}
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.h
new file mode 100644
index 000000000..299837862
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.h
@@ -0,0 +1,184 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xusbps_endpoint.h
+* @addtogroup usbpsu_v1_0
+* @{
+ *
+ * This is an internal file containing the definitions for endpoints. It is
+ * included by the xusbps_endpoint.c which is implementing the endpoint
+ * functions and by xusbps_intr.c.
+ *
+ * <pre>
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- --------------------------------------------------------
+ * 1.0   sg  06/06/16  First release
+ * </pre>
+ *
+ ******************************************************************************/
+#ifndef XUSBPSU_ENDPOINT_H
+#define XUSBPSU_ENDPOINT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_cache.h"
+#include "xusbpsu.h"
+#include "xil_types.h"
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/* Device Generic Command Register */
+#define XUSBPSU_DGCMD_SET_LMP                   0x00000001U
+#define XUSBPSU_DGCMD_SET_PERIODIC_PAR          0x00000002U
+#define XUSBPSU_DGCMD_XMIT_FUNCTION             0x00000003U
+
+/* These apply for core versions 1.94a and later */
+#define XUSBPSU_DGCMD_SET_SCRATCHPAD_ADDR_LO    0x00000004U
+#define XUSBPSU_DGCMD_SET_SCRATCHPAD_ADDR_HI    0x00000005U
+
+#define XUSBPSU_DGCMD_SELECTED_FIFO_FLUSH       0x00000009U
+#define XUSBPSU_DGCMD_ALL_FIFO_FLUSH            0x0000000aU
+#define XUSBPSU_DGCMD_SET_ENDPOINT_NRDY         0x0000000cU
+#define XUSBPSU_DGCMD_RUN_SOC_BUS_LOOPBACK      0x00000010U
+
+#define XUSBPSU_DGCMD_STATUS(n)                 (((u32)(n) >> 15) & 1)
+#define XUSBPSU_DGCMD_CMDACT                    (0x00000001U << 10)
+#define XUSBPSU_DGCMD_CMDIOC                    (0x00000001U << 8)
+
+/* Device Generic Command Parameter Register */
+#define XUSBPSU_DGCMDPAR_FORCE_LINKPM_ACCEPT    (0x00000001U << 0)
+#define XUSBPSU_DGCMDPAR_FIFO_NUM(n)            ((u32)(n) << 0)
+#define XUSBPSU_DGCMDPAR_RX_FIFO                (0x00000000U << 5)
+#define XUSBPSU_DGCMDPAR_TX_FIFO                (0x00000001U << 5)
+#define XUSBPSU_DGCMDPAR_LOOPBACK_DIS           (0x00000000U << 0)
+#define XUSBPSU_DGCMDPAR_LOOPBACK_ENA           (0x00000001U << 0)
+
+/* Device Endpoint Command Register */
+#define XUSBPSU_DEPCMD_PARAM_SHIFT              16U
+#define XUSBPSU_DEPCMD_PARAM(x)         ((u32)(x) << XUSBPSU_DEPCMD_PARAM_SHIFT)
+#define XUSBPSU_DEPCMD_GET_RSC_IDX(x)  (((u32)(x) >> XUSBPSU_DEPCMD_PARAM_SHIFT) & \
+                                        (u32)0x0000007fU)
+#define XUSBPSU_DEPCMD_STATUS(x)                (((u32)(x) >> 12) & (u32)0xF)
+#define XUSBPSU_DEPCMD_HIPRI_FORCERM            (0x00000001U << 11)
+#define XUSBPSU_DEPCMD_CMDACT                   (0x00000001U << 10)
+#define XUSBPSU_DEPCMD_CMDIOC                   (0x00000001U << 8)
+
+#define XUSBPSU_DEPCMD_DEPSTARTCFG              0x00000009U
+#define XUSBPSU_DEPCMD_ENDTRANSFER              0x00000008U
+#define XUSBPSU_DEPCMD_UPDATETRANSFER           0x00000007U
+#define XUSBPSU_DEPCMD_STARTTRANSFER            0x00000006U
+#define XUSBPSU_DEPCMD_CLEARSTALL               0x00000005U
+#define XUSBPSU_DEPCMD_SETSTALL                 0x00000004U
+#define XUSBPSU_DEPCMD_GETEPSTATE               0x00000003U
+#define XUSBPSU_DEPCMD_SETTRANSFRESOURCE        0x00000002U
+#define XUSBPSU_DEPCMD_SETEPCONFIG              0x00000001U
+
+/* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
+#define XUSBPSU_DALEPENA_EP(n)                  (0x00000001U << (n))
+
+#define XUSBPSU_DEPCFG_INT_NUM(n)               ((u32)(n) << 0)
+#define XUSBPSU_DEPCFG_XFER_COMPLETE_EN         (0x00000001U << 8)
+#define XUSBPSU_DEPCFG_XFER_IN_PROGRESS_EN      (0x00000001U << 9)
+#define XUSBPSU_DEPCFG_XFER_NOT_READY_EN        (0x00000001U << 10)
+#define XUSBPSU_DEPCFG_FIFO_ERROR_EN            (0x00000001U << 11)
+#define XUSBPSU_DEPCFG_STREAM_EVENT_EN          (0x00000001U << 13)
+#define XUSBPSU_DEPCFG_BINTERVAL_M1(n)          ((u32)(n) << 16)
+#define XUSBPSU_DEPCFG_STREAM_CAPABLE           (0x00000001U << 24)
+#define XUSBPSU_DEPCFG_EP_NUMBER(n)             ((u32)(n) << 25)
+#define XUSBPSU_DEPCFG_BULK_BASED               (0x00000001U << 30)
+#define XUSBPSU_DEPCFG_FIFO_BASED               (0x00000001U << 31)
+
+/* DEPCFG parameter 0 */
+#define XUSBPSU_DEPCFG_EP_TYPE(n)               ((u32)(n) << 1)
+#define XUSBPSU_DEPCFG_MAX_PACKET_SIZE(n)       ((u32)(n) << 3)
+#define XUSBPSU_DEPCFG_FIFO_NUMBER(n)           ((u32)(n) << 17)
+#define XUSBPSU_DEPCFG_BURST_SIZE(n)            ((u32)(n) << 22)
+#define XUSBPSU_DEPCFG_DATA_SEQ_NUM(n)          ((u32)(n) << 26)
+/* This applies for core versions earlier than 1.94a */
+#define XUSBPSU_DEPCFG_IGN_SEQ_NUM              (0x00000001U << 31)
+/* These apply for core versions 1.94a and later */
+#define XUSBPSU_DEPCFG_ACTION_INIT              (0x00000000U << 30)
+#define XUSBPSU_DEPCFG_ACTION_RESTORE           (0x00000001U << 30)
+#define XUSBPSU_DEPCFG_ACTION_MODIFY            (0x00000002U << 30)
+
+/* DEPXFERCFG parameter 0 */
+#define XUSBPSU_DEPXFERCFG_NUM_XFER_RES(n) ((u32)(n) & (u32)0xffff)
+
+#define XUSBPSU_DEPCMD_TYPE_BULK                2U
+#define XUSBPSU_DEPCMD_TYPE_INTR                3U
+
+/* TRB Length, PCM and Status */
+#define XUSBPSU_TRB_SIZE_MASK           (0x00ffffffU)
+#define XUSBPSU_TRB_SIZE_LENGTH(n)      ((u32)(n) & XUSBPSU_TRB_SIZE_MASK)
+#define XUSBPSU_TRB_SIZE_PCM1(n)        (((u32)(n) & (u32)0x03) << 24)
+#define XUSBPSU_TRB_SIZE_TRBSTS(n)      (((u32)(n) & ((u32)0x0f << 28)) >> 28)
+
+#define XUSBPSU_TRBSTS_OK               0U
+#define XUSBPSU_TRBSTS_MISSED_ISOC      1U
+#define XUSBPSU_TRBSTS_SETUP_PENDING    2U
+#define XUSBPSU_TRB_STS_XFER_IN_PROG    4U
+
+/* TRB Control */
+#define XUSBPSU_TRB_CTRL_HWO            ((u32)0x00000001U << 0)
+#define XUSBPSU_TRB_CTRL_LST            ((u32)0x00000001U << 1)
+#define XUSBPSU_TRB_CTRL_CHN            ((u32)0x00000001U << 2)
+#define XUSBPSU_TRB_CTRL_CSP            ((u32)0x00000001U << 3)
+#define XUSBPSU_TRB_CTRL_TRBCTL(n)      (((u32)(n) & (u32)0x3f) << 4)
+#define XUSBPSU_TRB_CTRL_ISP_IMI        (0x00000001U << 10)
+#define XUSBPSU_TRB_CTRL_IOC            (0x00000001U << 11)
+#define XUSBPSU_TRB_CTRL_SID_SOFN(n)    (((u32)(n) & (u32)0xffff) << 14)
+
+#define XUSBPSU_TRBCTL_NORMAL                   XUSBPSU_TRB_CTRL_TRBCTL(1)
+#define XUSBPSU_TRBCTL_CONTROL_SETUP            XUSBPSU_TRB_CTRL_TRBCTL(2)
+#define XUSBPSU_TRBCTL_CONTROL_STATUS2          XUSBPSU_TRB_CTRL_TRBCTL(3)
+#define XUSBPSU_TRBCTL_CONTROL_STATUS3          XUSBPSU_TRB_CTRL_TRBCTL(4)
+#define XUSBPSU_TRBCTL_CONTROL_DATA             XUSBPSU_TRB_CTRL_TRBCTL(5)
+#define XUSBPSU_TRBCTL_ISOCHRONOUS_FIRST        XUSBPSU_TRB_CTRL_TRBCTL(6)
+#define XUSBPSU_TRBCTL_ISOCHRONOUS              XUSBPSU_TRB_CTRL_TRBCTL(7)
+#define XUSBPSU_TRBCTL_LINK_TRB                 XUSBPSU_TRB_CTRL_TRBCTL(8)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XUSBPSU_ENDPOINT_H */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_g.c
new file mode 100644
index 000000000..41a9b8c7a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xusbpsu.h"
+
+/*
+* The configuration table for devices
+*/
+
+XUsbPsu_Config XUsbPsu_ConfigTable[] =
+{
+	{
+		XPAR_PSU_USB_0_DEVICE_ID,
+		XPAR_PSU_USB_0_BASEADDR
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_hw.h
new file mode 100644
index 000000000..db612b00f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_hw.h
@@ -0,0 +1,363 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xusbpsu_hw.h
+* @addtogroup usbpsu_v1_0
+* @{
+*
+* <pre>
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.0   sg    06/06/16 First release
+*
+* </pre>
+*
+*****************************************************************************/
+
+#ifndef XUSBPSU_HW_H	/* Prevent circular inclusions */
+#define XUSBPSU_HW_H	/* by using protection macros  */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+/************************** Constant Definitions ****************************/
+
+/**@name Register offsets
+ *
+ * The following constants provide access to each of the registers of the
+ * USBPSU device.
+ * @{
+ */
+
+/**/
+#define XUSBPSU_PORTSC_30						0x430
+#define XUSBPSU_PORTMSC_30						0x434
+
+/* XUSBPSU registers memory space boundries */
+#define XUSBPSU_GLOBALS_REGS_START              0xc100
+#define XUSBPSU_GLOBALS_REGS_END                0xc6ff
+#define XUSBPSU_DEVICE_REGS_START               0xc700
+#define XUSBPSU_DEVICE_REGS_END                 0xcbff
+#define XUSBPSU_OTG_REGS_START                  0xcc00
+#define XUSBPSU_OTG_REGS_END                    0xccff
+
+/* Global Registers */
+#define XUSBPSU_GSBUSCFG0                       0xc100
+#define XUSBPSU_GSBUSCFG1                       0xc104
+#define XUSBPSU_GTXTHRCFG                       0xc108
+#define XUSBPSU_GRXTHRCFG                       0xc10c
+#define XUSBPSU_GCTL                            0xc110
+#define XUSBPSU_GEVTEN                          0xc114
+#define XUSBPSU_GSTS                            0xc118
+#define XUSBPSU_GSNPSID                         0xc120
+#define XUSBPSU_GGPIO                           0xc124
+#define XUSBPSU_GUID                            0xc128
+#define XUSBPSU_GUCTL                           0xc12c
+#define XUSBPSU_GBUSERRADDR0                    0xc130
+#define XUSBPSU_GBUSERRADDR1                    0xc134
+#define XUSBPSU_GPRTBIMAP0                      0xc138
+#define XUSBPSU_GPRTBIMAP1                      0xc13c
+#define XUSBPSU_GHWPARAMS0_OFFSET               0xc140U
+#define XUSBPSU_GHWPARAMS1_OFFSET               0xc144U
+#define XUSBPSU_GHWPARAMS2_OFFSET               0xc148U
+#define XUSBPSU_GHWPARAMS3_OFFSET               0xc14cU
+#define XUSBPSU_GHWPARAMS4_OFFSET               0xc150U
+#define XUSBPSU_GHWPARAMS5_OFFSET               0xc154U
+#define XUSBPSU_GHWPARAMS6_OFFSET               0xc158U
+#define XUSBPSU_GHWPARAMS7_OFFSET               0xc15cU
+#define XUSBPSU_GDBGFIFOSPACE                   0xc160
+#define XUSBPSU_GDBGLTSSM                       0xc164
+#define XUSBPSU_GPRTBIMAP_HS0                   0xc180
+#define XUSBPSU_GPRTBIMAP_HS1                   0xc184
+#define XUSBPSU_GPRTBIMAP_FS0                   0xc188
+#define XUSBPSU_GPRTBIMAP_FS1                   0xc18c
+
+#define XUSBPSU_GUSB2PHYCFG(n)                  ((u32)0xc200 + ((u32)(n) * (u32)0x04))
+#define XUSBPSU_GUSB2I2CCTL(n)                  ((u32)0xc240 + ((u32)(n) * (u32)0x04))
+
+#define XUSBPSU_GUSB2PHYACC(n)                  ((u32)0xc280 + ((u32)(n) * (u32)0x04))
+
+#define XUSBPSU_GUSB3PIPECTL(n)                 ((u32)0xc2c0 + ((u32)(n) * (u32)0x04))
+
+#define XUSBPSU_GTXFIFOSIZ(n)                   ((u32)0xc300 + ((u32)(n) * (u32)0x04))
+#define XUSBPSU_GRXFIFOSIZ(n)                   ((u32)0xc380 + ((u32)(n) * (u32)0x04))
+
+#define XUSBPSU_GEVNTADRLO(n)                   ((u32)0xc400 + ((u32)(n) * (u32)0x10))
+#define XUSBPSU_GEVNTADRHI(n)                   ((u32)0xc404 + ((u32)(n) * (u32)0x10))
+#define XUSBPSU_GEVNTSIZ(n)                     ((u32)0xc408 + ((u32)(n) * (u32)0x10))
+#define XUSBPSU_GEVNTCOUNT(n)                   ((u32)0xc40c + ((u32)(n) * (u32)0x10))
+
+#define XUSBPSU_GHWPARAMS8                      0x0000c600U
+
+/* Device Registers */
+#define XUSBPSU_DCFG                            0x0000c700U
+#define XUSBPSU_DCTL                            0x0000c704U
+#define XUSBPSU_DEVTEN                          0x0000c708U
+#define XUSBPSU_DSTS                            0x0000c70cU
+#define XUSBPSU_DGCMDPAR                        0x0000c710U
+#define XUSBPSU_DGCMD                           0x0000c714U
+#define XUSBPSU_DALEPENA                        0x0000c720U
+#define XUSBPSU_DEPCMDPAR2(n)                   ((u32)0xc800 + ((u32)n * (u32)0x10))
+#define XUSBPSU_DEPCMDPAR1(n)                   ((u32)0xc804 + ((u32)n * (u32)0x10))
+#define XUSBPSU_DEPCMDPAR0(n)                   ((u32)0xc808 + ((u32)n * (u32)0x10))
+#define XUSBPSU_DEPCMD(n)                       ((u32)0xc80c + ((u32)n * (u32)0x10))
+
+/* OTG Registers */
+#define XUSBPSU_OCFG                            0x0000cc00U
+#define XUSBPSU_OCTL                            0x0000cc04U
+#define XUSBPSU_OEVT                            0xcc08U
+#define XUSBPSU_OEVTEN                          0xcc0CU
+#define XUSBPSU_OSTS                            0xcc10U
+
+/* Bit fields */
+
+/* Global Configuration Register */
+#define XUSBPSU_GCTL_PWRDNSCALE(n)              ((n) << 19)
+#define XUSBPSU_GCTL_U2RSTECN                   (1 << 16)
+#define XUSBPSU_GCTL_RAMCLKSEL(x)       (((x) & XUSBPSU_GCTL_CLK_MASK) << 6)
+#define XUSBPSU_GCTL_CLK_BUS                    (0U)
+#define XUSBPSU_GCTL_CLK_PIPE                   (1U)
+#define XUSBPSU_GCTL_CLK_PIPEHALF               (2U)
+#define XUSBPSU_GCTL_CLK_MASK                   (3U)
+
+#define XUSBPSU_GCTL_PRTCAP(n)                  (((n) & (3 << 12)) >> 12)
+#define XUSBPSU_GCTL_PRTCAPDIR(n)               ((n) << 12)
+#define XUSBPSU_GCTL_PRTCAP_HOST                1U
+#define XUSBPSU_GCTL_PRTCAP_DEVICE              2U
+#define XUSBPSU_GCTL_PRTCAP_OTG                 3U
+
+#define XUSBPSU_GCTL_CORESOFTRESET              (0x00000001U << 11)
+#define XUSBPSU_GCTL_SOFITPSYNC                 (0x00000001U << 10)
+#define XUSBPSU_GCTL_SCALEDOWN(n)               ((u32)(n) << 4)
+#define XUSBPSU_GCTL_SCALEDOWN_MASK             XUSBPSU_GCTL_SCALEDOWN(3)
+#define XUSBPSU_GCTL_DISSCRAMBLE                (0x00000001U << 3)
+#define XUSBPSU_GCTL_U2EXIT_LFPS                (0x00000001U << 2)
+#define XUSBPSU_GCTL_GBLHIBERNATIONEN           (0x00000001U << 1)
+#define XUSBPSU_GCTL_DSBLCLKGTNG                (0x00000001U << 0)
+
+/* Global Status Register Device Interrupt Mask */
+#define XUSBPSU_GSTS_DEVICE_IP_MASK 			0x00000040
+
+/* Global USB2 PHY Configuration Register */
+#define XUSBPSU_GUSB2PHYCFG_PHYSOFTRST          (0x00000001U << 31)
+#define XUSBPSU_GUSB2PHYCFG_SUSPHY              (0x00000001U << 6)
+
+/* Global USB3 PIPE Control Register */
+#define XUSBPSU_GUSB3PIPECTL_PHYSOFTRST         (0x00000001U << 31)
+#define XUSBPSU_GUSB3PIPECTL_SUSPHY             (0x00000001U << 17)
+
+/* Global TX Fifo Size Register */
+#define XUSBPSU_GTXFIFOSIZ_TXFDEF(n)            ((u32)(n) & (u32)0xffffU)
+#define XUSBPSU_GTXFIFOSIZ_TXFSTADDR(n)         ((u32)(n) & 0xffff0000U)
+
+/* Global Event Size Registers */
+#define XUSBPSU_GEVNTSIZ_INTMASK                ((u32)0x00000001U << 31U)
+#define XUSBPSU_GEVNTSIZ_SIZE(n)                ((u32)(n) & (u32)0xffffU)
+
+/* Global HWPARAMS1 Register */
+#define XUSBPSU_GHWPARAMS1_EN_PWROPT(n)         (((u32)(n) & ((u32)3 << 24)) >> 24)
+#define XUSBPSU_GHWPARAMS1_EN_PWROPT_NO         0U
+#define XUSBPSU_GHWPARAMS1_EN_PWROPT_CLK        1U
+#define XUSBPSU_GHWPARAMS1_EN_PWROPT_HIB        2U
+#define XUSBPSU_GHWPARAMS1_PWROPT(n)            ((u32)(n) << 24)
+#define XUSBPSU_GHWPARAMS1_PWROPT_MASK          XUSBPSU_GHWPARAMS1_PWROPT(3)
+
+/* Global HWPARAMS4 Register */
+#define XUSBPSU_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((u32)(n) & ((u32)0x0f << 13)) >> 13)
+#define XUSBPSU_MAX_HIBER_SCRATCHBUFS           15U
+
+/* Device Configuration Register */
+#define XUSBPSU_DCFG_DEVADDR(addr)              ((u32)(addr) << 3)
+#define XUSBPSU_DCFG_DEVADDR_MASK               XUSBPSU_DCFG_DEVADDR(0x7f)
+
+#define XUSBPSU_DCFG_SPEED_MASK					7U
+#define XUSBPSU_DCFG_SUPERSPEED					4U
+#define XUSBPSU_DCFG_HIGHSPEED					0U
+#define XUSBPSU_DCFG_FULLSPEED2					1U
+#define XUSBPSU_DCFG_LOWSPEED					2U
+#define XUSBPSU_DCFG_FULLSPEED1					3U
+
+#define XUSBPSU_DCFG_LPM_CAP                    (0x00000001U << 22U)
+
+/* Device Control Register */
+#define XUSBPSU_DCTL_RUN_STOP                   (0x00000001U << 31U)
+#define XUSBPSU_DCTL_CSFTRST                    ((u32)0x00000001U << 30U)
+#define XUSBPSU_DCTL_LSFTRST                    (0x00000001U << 29U)
+
+#define XUSBPSU_DCTL_HIRD_THRES_MASK            (0x0000001fU << 24U)
+#define XUSBPSU_DCTL_HIRD_THRES(n)              ((u32)(n) << 24)
+
+#define XUSBPSU_DCTL_APPL1RES                   (0x00000001U << 23)
+
+/* These apply for core versions 1.87a and earlier */
+#define XUSBPSU_DCTL_TRGTULST_MASK              (0x0000000fU << 17)
+#define XUSBPSU_DCTL_TRGTULST(n)                ((u32)(n) << 17)
+#define XUSBPSU_DCTL_TRGTULST_U2                (XUSBPSU_DCTL_TRGTULST(2))
+#define XUSBPSU_DCTL_TRGTULST_U3                (XUSBPSU_DCTL_TRGTULST(3))
+#define XUSBPSU_DCTL_TRGTULST_SS_DIS            (XUSBPSU_DCTL_TRGTULST(4))
+#define XUSBPSU_DCTL_TRGTULST_RX_DET            (XUSBPSU_DCTL_TRGTULST(5))
+#define XUSBPSU_DCTL_TRGTULST_SS_INACT          (XUSBPSU_DCTL_TRGTULST(6))
+
+/* These apply for core versions 1.94a and later */
+#define XUSBPSU_DCTL_KEEP_CONNECT               (0x00000001U << 19)
+#define XUSBPSU_DCTL_L1_HIBER_EN                (0x00000001U << 18)
+#define XUSBPSU_DCTL_CRS                        (0x00000001U << 17)
+#define XUSBPSU_DCTL_CSS                        (0x00000001U << 16)
+
+#define XUSBPSU_DCTL_INITU2ENA                  (0x00000001U << 12)
+#define XUSBPSU_DCTL_ACCEPTU2ENA                (0x00000001U << 11)
+#define XUSBPSU_DCTL_INITU1ENA                  (0x00000001U << 10)
+#define XUSBPSU_DCTL_ACCEPTU1ENA                (0x00000001U << 9)
+#define XUSBPSU_DCTL_TSTCTRL_MASK               (0x0000000fU << 1)
+
+#define XUSBPSU_DCTL_ULSTCHNGREQ_MASK           (0x0000000fU << 5)
+#define XUSBPSU_DCTL_ULSTCHNGREQ(n) (((u32)(n) << 5) & XUSBPSU_DCTL_ULSTCHNGREQ_MASK)
+
+#define XUSBPSU_DCTL_ULSTCHNG_NO_ACTION         (XUSBPSU_DCTL_ULSTCHNGREQ(0))
+#define XUSBPSU_DCTL_ULSTCHNG_SS_DISABLED       (XUSBPSU_DCTL_ULSTCHNGREQ(4))
+#define XUSBPSU_DCTL_ULSTCHNG_RX_DETECT         (XUSBPSU_DCTL_ULSTCHNGREQ(5))
+#define XUSBPSU_DCTL_ULSTCHNG_SS_INACTIVE       (XUSBPSU_DCTL_ULSTCHNGREQ(6))
+#define XUSBPSU_DCTL_ULSTCHNG_RECOVERY          (XUSBPSU_DCTL_ULSTCHNGREQ(8))
+#define XUSBPSU_DCTL_ULSTCHNG_COMPLIANCE        (XUSBPSU_DCTL_ULSTCHNGREQ(10))
+#define XUSBPSU_DCTL_ULSTCHNG_LOOPBACK          (XUSBPSU_DCTL_ULSTCHNGREQ(11))
+
+/* Device Event Enable Register */
+#define XUSBPSU_DEVTEN_VNDRDEVTSTRCVEDEN        ((u32)0x00000001 << 12)
+#define XUSBPSU_DEVTEN_EVNTOVERFLOWEN           ((u32)0x00000001 << 11)
+#define XUSBPSU_DEVTEN_CMDCMPLTEN               ((u32)0x00000001 << 10)
+#define XUSBPSU_DEVTEN_ERRTICERREN              ((u32)0x00000001 << 9)
+#define XUSBPSU_DEVTEN_SOFEN                    ((u32)0x00000001 << 7)
+#define XUSBPSU_DEVTEN_EOPFEN                   ((u32)0x00000001 << 6)
+#define XUSBPSU_DEVTEN_HIBERNATIONREQEVTEN      ((u32)0x00000001 << 5)
+#define XUSBPSU_DEVTEN_WKUPEVTEN                ((u32)0x00000001 << 4)
+#define XUSBPSU_DEVTEN_ULSTCNGEN                ((u32)0x00000001 << 3)
+#define XUSBPSU_DEVTEN_CONNECTDONEEN            ((u32)0x00000001 << 2)
+#define XUSBPSU_DEVTEN_USBRSTEN                 ((u32)0x00000001 << 1)
+#define XUSBPSU_DEVTEN_DISCONNEVTEN             ((u32)0x00000001 << 0)
+
+/* Device Status Register */
+#define XUSBPSU_DSTS_DCNRD                      (0x00000001U << 29)
+
+/* This applies for core versions 1.87a and earlier */
+#define XUSBPSU_DSTS_PWRUPREQ                   (0x00000001U << 24)
+
+/* These apply for core versions 1.94a and later */
+#define XUSBPSU_DSTS_RSS                        (0x00000001U << 25)
+#define XUSBPSU_DSTS_SSS                        (0x00000001U << 24)
+
+#define XUSBPSU_DSTS_COREIDLE                   (0x00000001U << 23)
+#define XUSBPSU_DSTS_DEVCTRLHLT                 (0x00000001U << 22)
+
+#define XUSBPSU_DSTS_USBLNKST_MASK              (0x0000000fU << 18)
+#define XUSBPSU_DSTS_USBLNKST(n) (((u32)(n) & XUSBPSU_DSTS_USBLNKST_MASK) >> 18)
+
+#define XUSBPSU_DSTS_RXFIFOEMPTY                (0x00000001U << 17)
+
+#define XUSBPSU_DSTS_SOFFN_MASK                 (0x00003fffU << 3)
+#define XUSBPSU_DSTS_SOFFN(n)           (((u32)(n) & XUSBPSU_DSTS_SOFFN_MASK) >> 3)
+
+#define XUSBPSU_DSTS_CONNECTSPD                 (0x00000007U << 0)
+
+#define XUSBPSU_DSTS_SUPERSPEED                 (4U << 0)
+#define XUSBPSU_DSTS_HIGHSPEED                  (0U << 0)
+#define XUSBPSU_DSTS_FULLSPEED2                 (1U << 0)
+#define XUSBPSU_DSTS_LOWSPEED                   (2U << 0)
+#define XUSBPSU_DSTS_FULLSPEED1                 (3U << 0)
+
+/*Portpmsc 3.0 bit field*/
+#define XUSBPSU_PORTMSC_30_FLA_MASK				(1U << 16)
+#define XUSBPSU_PORTMSC_30_U2_TIMEOUT_MASK		(0xffU << 8)
+#define XUSBPSU_PORTMSC_30_U2_TIMEOUT_SHIFT		(8U)
+#define XUSBPSU_PORTMSC_30_U1_TIMEOUT_MASK		(0xffU << 0)
+#define XUSBPSU_PORTMSC_30_U1_TIMEOUT_SHIFT		(0U)
+
+
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+*
+* Read a register of the USBPS8 device. This macro provides register
+* access to all registers using the register offsets defined above.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Offset is the offset of the register to read.
+*
+* @return	The contents of the register.
+*
+* @note		C-style Signature:
+*		u32 XUsbPsu_ReadReg(struct XUsbPsu *InstancePtr, u32 Offset);
+*
+******************************************************************************/
+#define XUsbPsu_ReadReg(InstancePtr, Offset) \
+	Xil_In32((InstancePtr)->ConfigPtr->BaseAddress + (u32)(Offset))
+
+/*****************************************************************************/
+/**
+*
+* Write a register of the USBPS8 device. This macro provides
+* register access to all registers using the register offsets defined above.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	RegOffset is the offset of the register to write.
+* @param	Data is the value to write to the register.
+*
+* @return	None.
+*
+* @note 	C-style Signature:
+*		void XUsbPsu_WriteReg(struct XUsbPsu *InstancePtr,
+*								u32 Offset,u32 Data)
+*
+******************************************************************************/
+#define XUsbPsu_WriteReg(InstancePtr, Offset, Data) \
+	Xil_Out32((InstancePtr)->ConfigPtr->BaseAddress + (u32)(Offset), (u32)(Data))
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* End of protection macro. */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_intr.c
new file mode 100644
index 000000000..85baab0f8
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_intr.c
@@ -0,0 +1,434 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xusbpsu_intr.c
+* @addtogroup usbpsu_v1_0
+* @{
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.0   sg  06/06/16 First release
+*
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xusbpsu.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+* Endpoint interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Event is endpoint Event occured in the core.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_EpInterrupt(struct XUsbPsu *InstancePtr,
+		const struct XUsbPsu_Event_Epevt *Event)
+{
+	struct XUsbPsu_Ep *Ept;
+	u32 Epnum;
+
+	Epnum = Event->Epnumber;
+	Ept = &InstancePtr->eps[Epnum];
+
+	if ((Ept->EpStatus & XUSBPSU_EP_ENABLED) == (u32)0U) {
+		return;
+	}
+
+	if ((Epnum == (u32)0) || (Epnum == (u32)1)) {
+		XUsbPsu_Ep0Intr(InstancePtr, Event);
+		return;
+	}
+
+	/* Handle other end point events */
+	switch (Event->Endpoint_Event) {
+		case XUSBPSU_DEPEVT_XFERCOMPLETE:
+			XUsbPsu_EpXferComplete(InstancePtr, Event);
+			break;
+
+		case XUSBPSU_DEPEVT_XFERNOTREADY:
+			break;
+
+		default:
+			/* Made for Misra-C Compliance. */
+			break;
+	}
+}
+
+/****************************************************************************/
+/**
+* Disconnect Interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_DisconnectIntr(struct XUsbPsu *InstancePtr)
+{
+	u32 RegVal;
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+	RegVal &= ~XUSBPSU_DCTL_INITU1ENA;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+	RegVal &= ~XUSBPSU_DCTL_INITU2ENA;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+
+	InstancePtr->IsConfigDone = 0U;
+	InstancePtr->Speed = XUSBPSU_SPEED_UNKNOWN;
+}
+
+/****************************************************************************/
+/**
+* Reset Interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_ResetIntr(struct XUsbPsu *InstancePtr)
+{
+	u32	RegVal;
+	u32	Index;
+
+	InstancePtr->State = XUSBPSU_STATE_DEFAULT;
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL);
+	RegVal &= ~XUSBPSU_DCTL_TSTCTRL_MASK;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal);
+	InstancePtr->TestMode = 0U;
+
+	for (Index = 0U; Index < (InstancePtr->NumInEps + InstancePtr->NumOutEps);
+			Index++)
+	{
+		InstancePtr->eps[Index].EpStatus = 0U;
+	}
+
+	InstancePtr->IsConfigDone = 0U;
+
+	/* Reset device address to zero */
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCFG);
+	RegVal &= ~(XUSBPSU_DCFG_DEVADDR_MASK);
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCFG, RegVal);
+}
+
+/****************************************************************************/
+/**
+* Connection Done Interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_ConnDoneIntr(struct XUsbPsu *InstancePtr)
+{
+	u32			RegVal;
+	u16			Size;
+	u8			Speed;
+
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DSTS);
+	Speed = (u8)(RegVal & XUSBPSU_DSTS_CONNECTSPD);
+	InstancePtr->Speed = Speed;
+
+	switch (Speed) {
+	case XUSBPSU_DCFG_SUPERSPEED:
+#ifdef XUSBPSU_DEBUG
+		xil_printf("Super Speed\r\n");
+#endif
+		Size = 512U;
+		InstancePtr->Speed = XUSBPSU_SPEED_SUPER;
+		break;
+
+	case XUSBPSU_DCFG_HIGHSPEED:
+#ifdef XUSBPSU_DEBUG
+		xil_printf("High Speed\r\n");
+#endif
+		Size = 64U;
+		InstancePtr->Speed = XUSBPSU_SPEED_HIGH;
+		break;
+
+	case XUSBPSU_DCFG_FULLSPEED2:
+	case XUSBPSU_DCFG_FULLSPEED1:
+#ifdef XUSBPSU_DEBUG
+		xil_printf("Full Speed\r\n");
+#endif
+		Size = 64U;
+		InstancePtr->Speed = XUSBPSU_SPEED_FULL;
+		break;
+
+	case XUSBPSU_DCFG_LOWSPEED:
+#ifdef XUSBPSU_DEBUG
+		xil_printf("Low Speed\r\n");
+#endif
+		Size = 64U;
+		InstancePtr->Speed = XUSBPSU_SPEED_LOW;
+		break;
+	default :
+		Size = 64U;
+		break;
+	}
+
+	(void)XUsbPsu_EnableControlEp(InstancePtr, Size);
+	(void)XUsbPsu_RecvSetup(InstancePtr);
+}
+
+/****************************************************************************/
+/**
+* Link Status Change Interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	EvtInfo is Event information.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_LinkStsChangeIntr(struct XUsbPsu *InstancePtr, u32 EvtInfo)
+{
+	u32	State = EvtInfo & (u32)XUSBPSU_LINK_STATE_MASK;
+	InstancePtr->LinkState = (u8)State;
+}
+
+/****************************************************************************/
+/**
+* Interrupt handler for device specific events.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Event is the Device Event occured in core.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_DevInterrupt(struct XUsbPsu *InstancePtr,
+		const struct XUsbPsu_Event_Devt *Event)
+{
+
+	switch (Event->Type) {
+		case XUSBPSU_DEVICE_EVENT_DISCONNECT:
+			XUsbPsu_DisconnectIntr(InstancePtr);
+			break;
+
+		case XUSBPSU_DEVICE_EVENT_RESET:
+			XUsbPsu_ResetIntr(InstancePtr);
+			break;
+
+		case XUSBPSU_DEVICE_EVENT_CONNECT_DONE:
+			XUsbPsu_ConnDoneIntr(InstancePtr);
+			break;
+
+		case XUSBPSU_DEVICE_EVENT_WAKEUP:
+			break;
+
+		case XUSBPSU_DEVICE_EVENT_HIBER_REQ:
+			break;
+
+		case XUSBPSU_DEVICE_EVENT_LINK_STATUS_CHANGE:
+			XUsbPsu_LinkStsChangeIntr(InstancePtr,
+					Event->Event_Info);
+			break;
+
+		case XUSBPSU_DEVICE_EVENT_EOPF:
+			break;
+
+		case XUSBPSU_DEVICE_EVENT_SOF:
+			break;
+
+		case XUSBPSU_DEVICE_EVENT_ERRATIC_ERROR:
+			break;
+
+		case XUSBPSU_DEVICE_EVENT_CMD_CMPL:
+			break;
+
+		case XUSBPSU_DEVICE_EVENT_OVERFLOW:
+			break;
+
+		default:
+			/* Made for Misra-C Compliance. */
+			break;
+	}
+}
+
+/****************************************************************************/
+/**
+* Processes an Event entry in Event Buffer.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @param	Event is the Event entry.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_EventHandler(struct XUsbPsu *InstancePtr,
+			const union XUsbPsu_Event *Event)
+{
+
+	if (Event->Type.Is_DevEvt == 0U) {
+		/* End point Specific Event */
+		XUsbPsu_EpInterrupt(InstancePtr, &Event->Epevt);
+		return;
+	}
+
+	switch (Event->Type.Type) {
+	case XUSBPSU_EVENT_TYPE_DEV:
+		/* Device Specific Event */
+		XUsbPsu_DevInterrupt(InstancePtr, &Event->Devt);
+		break;
+	/* Carkit and I2C events not supported now */
+	default:
+		/* Made for Misra-C Compliance. */
+		break;
+	}
+}
+
+/****************************************************************************/
+/**
+* Processes events in an Event Buffer.
+*
+* @param	InstancePtr is a pointer to the XUsbPsu instance.
+* @bus		Event buffer number.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_EventBufferHandler(struct XUsbPsu *InstancePtr)
+{
+	struct XUsbPsu_EvtBuffer *Evt;
+	union XUsbPsu_Event Event = {0};
+
+	Evt = &InstancePtr->Evt;
+
+	Xil_DCacheInvalidateRange((INTPTR)Evt->BuffAddr,
+                              (u32)XUSBPSU_EVENT_BUFFERS_SIZE);
+
+	while (Evt->Count > 0) {
+		Event.Raw = *(UINTPTR *)(Evt->BuffAddr + Evt->Offset);
+
+		/*
+         * Process the event received
+         */
+        XUsbPsu_EventHandler(InstancePtr, &Event);
+
+		Evt->Offset = (Evt->Offset + 4U) % XUSBPSU_EVENT_BUFFERS_SIZE;
+		Evt->Count -= 4;
+		XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0), 4U);
+	}
+
+	Evt->Flags &= ~XUSBPSU_EVENT_PENDING;
+}
+
+/****************************************************************************/
+/**
+* Main Interrupt Handler.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUsbPsu_IntrHandler(void *XUsbPsuInstancePtr)
+{
+	struct XUsbPsu	*InstancePtr;
+	struct XUsbPsu_EvtBuffer *Evt;
+	u32 Count;
+	u32 RegVal;
+
+	InstancePtr = XUsbPsuInstancePtr;
+
+	Evt = &InstancePtr->Evt;
+
+	Count = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0));
+	Count &= XUSBPSU_GEVNTCOUNT_MASK;
+	/*
+	 * As per data book software should only process Events if Event count
+	 * is greater than zero.
+	 */
+	if (Count == 0U) {
+		return;
+	}
+
+	Evt->Count = Count;
+	Evt->Flags |= XUSBPSU_EVENT_PENDING;
+
+	/* Mask event interrupt */
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GEVNTSIZ(0));
+	RegVal |= XUSBPSU_GEVNTSIZ_INTMASK;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTSIZ(0), RegVal);
+
+	/* Processes events in an Event Buffer */
+	XUsbPsu_EventBufferHandler(InstancePtr);
+
+	/* Unmask event interrupt */
+	RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GEVNTSIZ(0));
+	RegVal &= ~XUSBPSU_GEVNTSIZ_INTMASK;
+	XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTSIZ(0), RegVal);
+}
+
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_sinit.c
new file mode 100644
index 000000000..c172c5d69
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_sinit.c
@@ -0,0 +1,99 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xusbpsu_sinit.h
+* @addtogroup usbpsu_v1_0
+* @{
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.0   sg   06/06/16 First release
+*
+* </pre>
+*
+*****************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xusbpsu.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+extern XUsbPsu_Config XUsbPsu_ConfigTable[];
+
+
+/*****************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID.  The table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId is the unique device ID of the device being looked up.
+*
+* @return
+* A pointer to the configuration table entry corresponding to the given
+* device ID, or NULL if no match is found.
+*
+******************************************************************************/
+XUsbPsu_Config *XUsbPsu_LookupConfig(u16 DeviceId)
+{
+	XUsbPsu_Config *CfgPtr = NULL;
+	u32 i;
+
+	for (i = 0U; i < (u32)XPAR_XUSBPSU_NUM_INSTANCES; i++) {
+			if (XUsbPsu_ConfigTable[i].DeviceId == DeviceId) {
+			CfgPtr = &XUsbPsu_ConfigTable[i];
+			break;
+		}
+	}
+
+	return (XUsbPsu_Config *)(CfgPtr);
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps_g.c
index 5147be676..6ea6b192b 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps_g.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_g.c
index 33202264d..194aac12e 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_g.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/system.mss b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/system.mss
index 5a742ad93..76354534a 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/system.mss
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/system.mss
@@ -4,7 +4,7 @@
 
 BEGIN OS
  PARAMETER OS_NAME = standalone
- PARAMETER OS_VER = 5.4
+ PARAMETER OS_VER = 6.1
  PARAMETER PROC_INSTANCE = psu_cortexr5_0
  PARAMETER stdin = psu_uart_0
  PARAMETER stdout = psu_uart_0
@@ -15,13 +15,12 @@ BEGIN PROCESSOR
  PARAMETER DRIVER_NAME = cpu_cortexr5
  PARAMETER DRIVER_VER = 1.1
  PARAMETER HW_INSTANCE = psu_cortexr5_0
- PARAMETER extra_compiler_flags = -g -DARMR5 -mfpu=vfpv3-d16
 END
 
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = scugic
- PARAMETER DRIVER_VER = 3.2
+ PARAMETER DRIVER_VER = 3.5
  PARAMETER HW_INSTANCE = psu_acpu_gic
 END
 
@@ -117,31 +116,31 @@ END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = sysmonpsu
- PARAMETER DRIVER_VER = 1.0
+ PARAMETER DRIVER_VER = 2.0
  PARAMETER HW_INSTANCE = psu_ams
 END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = axipmon
- PARAMETER DRIVER_VER = 6.4
+ PARAMETER DRIVER_VER = 6.5
  PARAMETER HW_INSTANCE = psu_apm_0
 END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = axipmon
- PARAMETER DRIVER_VER = 6.4
+ PARAMETER DRIVER_VER = 6.5
  PARAMETER HW_INSTANCE = psu_apm_1
 END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = axipmon
- PARAMETER DRIVER_VER = 6.4
+ PARAMETER DRIVER_VER = 6.5
  PARAMETER HW_INSTANCE = psu_apm_2
 END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = axipmon
- PARAMETER DRIVER_VER = 6.4
+ PARAMETER DRIVER_VER = 6.5
  PARAMETER HW_INSTANCE = psu_apm_5
 END
 
@@ -152,14 +151,8 @@ BEGIN DRIVER
 END
 
 BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = psu_bbram_0
-END
-
-BEGIN DRIVER
  PARAMETER DRIVER_NAME = canps
- PARAMETER DRIVER_VER = 3.1
+ PARAMETER DRIVER_VER = 3.2
  PARAMETER HW_INSTANCE = psu_can_1
 END
 
@@ -177,7 +170,7 @@ END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = coresightps_dcc
- PARAMETER DRIVER_VER = 1.2
+ PARAMETER DRIVER_VER = 1.3
  PARAMETER HW_INSTANCE = psu_coresight_0
 END
 
@@ -201,7 +194,7 @@ END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = csudma
- PARAMETER DRIVER_VER = 1.0
+ PARAMETER DRIVER_VER = 1.1
  PARAMETER HW_INSTANCE = psu_csudma
 END
 
@@ -254,8 +247,8 @@ BEGIN DRIVER
 END
 
 BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
+ PARAMETER DRIVER_NAME = ddrcpsu
+ PARAMETER DRIVER_VER = 1.1
  PARAMETER HW_INSTANCE = psu_ddrc_0
 END
 
@@ -279,7 +272,7 @@ END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = emacps
- PARAMETER DRIVER_VER = 3.2
+ PARAMETER DRIVER_VER = 3.3
  PARAMETER HW_INSTANCE = psu_ethernet_3
 END
 
@@ -375,25 +368,19 @@ END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = iicps
- PARAMETER DRIVER_VER = 3.1
+ PARAMETER DRIVER_VER = 3.4
  PARAMETER HW_INSTANCE = psu_i2c_0
 END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = iicps
- PARAMETER DRIVER_VER = 3.1
+ PARAMETER DRIVER_VER = 3.4
  PARAMETER HW_INSTANCE = psu_i2c_1
 END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = generic
  PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = psu_iou_s
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
  PARAMETER HW_INSTANCE = psu_iou_scntr
 END
 
@@ -417,13 +404,13 @@ END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = ipipsu
- PARAMETER DRIVER_VER = 2.0
+ PARAMETER DRIVER_VER = 2.1
  PARAMETER HW_INSTANCE = psu_ipi_1
 END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = ipipsu
- PARAMETER DRIVER_VER = 2.0
+ PARAMETER DRIVER_VER = 2.1
  PARAMETER HW_INSTANCE = psu_ipi_2
 END
 
@@ -472,12 +459,6 @@ END
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = generic
  PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = psu_ocm_ram_1
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
  PARAMETER HW_INSTANCE = psu_ocm_xmpu_cfg
 END
 
@@ -502,24 +483,24 @@ END
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = generic
  PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = psu_pmu_global_0
+ PARAMETER HW_INSTANCE = psu_pcie_low
 END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = generic
  PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = psu_pmu_iomodule
+ PARAMETER HW_INSTANCE = psu_pmu_global_0
 END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = generic
  PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = psu_pmu_ram
+ PARAMETER HW_INSTANCE = psu_pmu_iomodule
 END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = qspipsu
- PARAMETER DRIVER_VER = 1.0
+ PARAMETER DRIVER_VER = 1.3
  PARAMETER HW_INSTANCE = psu_qspi_0
 END
 
@@ -538,36 +519,12 @@ END
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = generic
  PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = psu_r5_0_atcm_lockstep
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
  PARAMETER HW_INSTANCE = psu_r5_0_btcm
 END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = generic
  PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = psu_r5_0_btcm_lockstep
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = psu_r5_1_atcm
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
- PARAMETER HW_INSTANCE = psu_r5_1_btcm
-END
-
-BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
  PARAMETER HW_INSTANCE = psu_r5_ddr_0
 END
 
@@ -579,7 +536,7 @@ END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = scugic
- PARAMETER DRIVER_VER = 3.2
+ PARAMETER DRIVER_VER = 3.5
  PARAMETER HW_INSTANCE = psu_rcpu_gic
 END
 
@@ -597,7 +554,7 @@ END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = rtcpsu
- PARAMETER DRIVER_VER = 1.2
+ PARAMETER DRIVER_VER = 1.3
  PARAMETER HW_INSTANCE = psu_rtc
 END
 
@@ -609,7 +566,7 @@ END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = sdps
- PARAMETER DRIVER_VER = 2.7
+ PARAMETER DRIVER_VER = 3.1
  PARAMETER HW_INSTANCE = psu_sd_1
 END
 
@@ -639,43 +596,43 @@ END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = ttcps
- PARAMETER DRIVER_VER = 3.1
+ PARAMETER DRIVER_VER = 3.2
  PARAMETER HW_INSTANCE = psu_ttc_0
 END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = ttcps
- PARAMETER DRIVER_VER = 3.1
+ PARAMETER DRIVER_VER = 3.2
  PARAMETER HW_INSTANCE = psu_ttc_1
 END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = ttcps
- PARAMETER DRIVER_VER = 3.1
+ PARAMETER DRIVER_VER = 3.2
  PARAMETER HW_INSTANCE = psu_ttc_2
 END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = ttcps
- PARAMETER DRIVER_VER = 3.1
+ PARAMETER DRIVER_VER = 3.2
  PARAMETER HW_INSTANCE = psu_ttc_3
 END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = uartps
- PARAMETER DRIVER_VER = 3.1
+ PARAMETER DRIVER_VER = 3.3
  PARAMETER HW_INSTANCE = psu_uart_0
 END
 
 BEGIN DRIVER
  PARAMETER DRIVER_NAME = uartps
- PARAMETER DRIVER_VER = 3.1
+ PARAMETER DRIVER_VER = 3.3
  PARAMETER HW_INSTANCE = psu_uart_1
 END
 
 BEGIN DRIVER
- PARAMETER DRIVER_NAME = generic
- PARAMETER DRIVER_VER = 2.0
+ PARAMETER DRIVER_NAME = usbpsu
+ PARAMETER DRIVER_VER = 1.1
  PARAMETER HW_INSTANCE = psu_usb_0
 END
 
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/xbram_g.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/xbram_g.c
index aa923f4f9..e9d647916 100644
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/xbram_g.c
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/bram_v4_1/src/xbram_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite_g.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite_g.c
index a082ce0fd..b478e5d05 100644
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite_g.c
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/emaclite_v4_2/src/xemaclite_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio_g.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio_g.c
index 219b80d7f..0c8b226fc 100644
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio_g.c
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/gpio_v4_1/src/xgpio_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_5/src/xintc_g.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_5/src/xintc_g.c
index 85c993d2d..f44563f9f 100644
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_5/src/xintc_g.c
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_5/src/xintc_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/bspconfig.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/bspconfig.h
index 4dd178f04..8671e3fbe 100644
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/bspconfig.h
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/bspconfig.h
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_exceptions_g.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_exceptions_g.h
index fb9e56339..17fa89370 100644
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_exceptions_g.h
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_exceptions_g.h
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_interrupts_g.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_interrupts_g.c
index 51801c5eb..0c9c7875d 100644
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_interrupts_g.c
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src/microblaze_interrupts_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v4_1/src/xtmrctr_g.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v4_1/src/xtmrctr_g.c
index 9f75b9763..464f2099e 100644
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v4_1/src/xtmrctr_g.c
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/tmrctr_v4_1/src/xtmrctr_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite_g.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite_g.c
index 1edd414e3..90a346f75 100644
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite_g.c
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/uartlite_v3_2/src/xuartlite_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/.cproject b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/.cproject
index dc2b71035..cd548fd9f 100644
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/.cproject
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/.cproject
@@ -116,7 +116,7 @@
 						</toolChain>
 					</folderInfo>
 					<sourceEntries>
-						<entry excluding="src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/fsdata.c|src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata|src/platform.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+						<entry excluding="src/printf-stdarg.c|src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/fsdata.c|src/lwIP_Demo/lwIP_Apps/apps/httpserver_raw_from_lwIP_download/makefsdata|src/platform.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
 					</sourceEntries>
 				</configuration>
 			</storageModule>
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/.project b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/.project
index 9fb066b6b..04040ffb0 100644
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/.project
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/.project
@@ -129,7 +129,7 @@
 			</matcher>
 		</filter>
 		<filter>
-			<id>1426001044021</id>
+			<id>1484796638366</id>
 			<name>src/Full_Demo/Common_Demo_Source/Minimal</name>
 			<type>5</type>
 			<matcher>
@@ -138,7 +138,7 @@
 			</matcher>
 		</filter>
 		<filter>
-			<id>1426001044028</id>
+			<id>1484796638369</id>
 			<name>src/Full_Demo/Common_Demo_Source/Minimal</name>
 			<type>5</type>
 			<matcher>
@@ -147,7 +147,7 @@
 			</matcher>
 		</filter>
 		<filter>
-			<id>1426001044037</id>
+			<id>1484796638372</id>
 			<name>src/Full_Demo/Common_Demo_Source/Minimal</name>
 			<type>5</type>
 			<matcher>
@@ -156,7 +156,7 @@
 			</matcher>
 		</filter>
 		<filter>
-			<id>1426001044046</id>
+			<id>1484796638376</id>
 			<name>src/Full_Demo/Common_Demo_Source/Minimal</name>
 			<type>5</type>
 			<matcher>
@@ -165,7 +165,7 @@
 			</matcher>
 		</filter>
 		<filter>
-			<id>1426001044057</id>
+			<id>1484796638381</id>
 			<name>src/Full_Demo/Common_Demo_Source/Minimal</name>
 			<type>5</type>
 			<matcher>
@@ -174,7 +174,7 @@
 			</matcher>
 		</filter>
 		<filter>
-			<id>1426001044063</id>
+			<id>1484796638385</id>
 			<name>src/Full_Demo/Common_Demo_Source/Minimal</name>
 			<type>5</type>
 			<matcher>
@@ -183,7 +183,7 @@
 			</matcher>
 		</filter>
 		<filter>
-			<id>1426001044071</id>
+			<id>1484796638389</id>
 			<name>src/Full_Demo/Common_Demo_Source/Minimal</name>
 			<type>5</type>
 			<matcher>
@@ -192,7 +192,7 @@
 			</matcher>
 		</filter>
 		<filter>
-			<id>1426001044076</id>
+			<id>1484796638392</id>
 			<name>src/Full_Demo/Common_Demo_Source/Minimal</name>
 			<type>5</type>
 			<matcher>
@@ -201,7 +201,7 @@
 			</matcher>
 		</filter>
 		<filter>
-			<id>1426001044081</id>
+			<id>1484796638396</id>
 			<name>src/Full_Demo/Common_Demo_Source/Minimal</name>
 			<type>5</type>
 			<matcher>
@@ -210,7 +210,7 @@
 			</matcher>
 		</filter>
 		<filter>
-			<id>1426001044088</id>
+			<id>1484796638399</id>
 			<name>src/Full_Demo/Common_Demo_Source/Minimal</name>
 			<type>5</type>
 			<matcher>
@@ -219,7 +219,7 @@
 			</matcher>
 		</filter>
 		<filter>
-			<id>1426001044094</id>
+			<id>1484796638402</id>
 			<name>src/Full_Demo/Common_Demo_Source/Minimal</name>
 			<type>5</type>
 			<matcher>
@@ -228,7 +228,7 @@
 			</matcher>
 		</filter>
 		<filter>
-			<id>1426001044098</id>
+			<id>1484796638406</id>
 			<name>src/Full_Demo/Common_Demo_Source/Minimal</name>
 			<type>5</type>
 			<matcher>
@@ -237,7 +237,7 @@
 			</matcher>
 		</filter>
 		<filter>
-			<id>1426001044103</id>
+			<id>1484796638409</id>
 			<name>src/Full_Demo/Common_Demo_Source/Minimal</name>
 			<type>5</type>
 			<matcher>
@@ -246,7 +246,7 @@
 			</matcher>
 		</filter>
 		<filter>
-			<id>1426001044107</id>
+			<id>1484796638413</id>
 			<name>src/Full_Demo/Common_Demo_Source/Minimal</name>
 			<type>5</type>
 			<matcher>
@@ -255,6 +255,15 @@
 			</matcher>
 		</filter>
 		<filter>
+			<id>1484796638416</id>
+			<name>src/Full_Demo/Common_Demo_Source/Minimal</name>
+			<type>5</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-AbortDelay.c</arguments>
+			</matcher>
+		</filter>
+		<filter>
 			<id>1426008787023</id>
 			<name>src/lwIP_Demo/lwIP-1.4.0/src/core</name>
 			<type>10</type>
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/FreeRTOSConfig.h b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/FreeRTOSConfig.h
index 21130bdad..546d99ff0 100644
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/FreeRTOSConfig.h
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/FreeRTOSConfig.h
@@ -161,6 +161,8 @@ referenced anyway. */
 #define INCLUDE_xTaskGetSchedulerState			0
 #define INCLUDE_xSemaphoreGetMutexHolder		0
 #define INCLUDE_xTimerPendFunctionCall			1
+#define INCLUDE_xTaskAbortDelay					1
+#define INCLUDE_xTaskGetHandle					1
 
 /* This demo does not make use of example stats formatting functions.  These
 format the raw data provided by the uxTaskGetSystemState() function in to human
diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/Full_Demo/main_full.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/Full_Demo/main_full.c
index 6964298f2..d4562fae6 100644
--- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/Full_Demo/main_full.c
+++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/Full_Demo/main_full.c
@@ -140,6 +140,7 @@
 #include "EventGroupsDemo.h"
 #include "TaskNotify.h"
 #include "IntSemTest.h"
+#include "AbortDelay.h"
 
 /* Priorities for the demo application tasks. */
 #define mainSEM_TEST_PRIORITY				( tskIDLE_PRIORITY + 1UL )
@@ -251,6 +252,7 @@ void main_full( void )
 	vStartEventGroupTasks();
 	vStartTaskNotifyTask();
 	vStartInterruptSemaphoreTasks();
+	vCreateAbortDelayTasks();
 
 	/* Note - the set of standard demo tasks contains two versions of
 	vStartMathTasks.c.  One is defined in flop.c, and uses double precision
@@ -371,17 +373,22 @@ unsigned long ulErrorFound = pdFALSE;
 			ulErrorFound |= 1UL << 14UL;
 		}
 
+		if( xAreAbortDelayTestTasksStillRunning() != pdTRUE )
+		{
+			ulErrorFound |= 1UL << 15UL;
+		}
+
 		/* Check that the register test 1 task is still running. */
 		if( ulLastRegTest1Value == ulRegTest1LoopCounter )
 		{
-			ulErrorFound |= 1UL << 15UL;
+			ulErrorFound |= 1UL << 16UL;
 		}
 		ulLastRegTest1Value = ulRegTest1LoopCounter;
 
 		/* Check that the register test 2 task is still running. */
 		if( ulLastRegTest2Value == ulRegTest2LoopCounter )
 		{
-			ulErrorFound |= 1UL << 16UL;
+			ulErrorFound |= 1UL << 17UL;
 		}
 		ulLastRegTest2Value = ulRegTest2LoopCounter;
 
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/port.c b/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/port.c
index 51c750825..0b780d6ff 100644
--- a/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/port.c
+++ b/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/port.c
@@ -136,12 +136,18 @@ context. */
 #define portNO_FLOATING_POINT_CONTEXT	( ( StackType_t ) 0 )
 
 /* Constants required to setup the initial task context. */
-#define portEL3							( ( StackType_t ) 0x0c )
 #define portSP_ELx						( ( StackType_t ) 0x01 )
 #define portSP_EL0						( ( StackType_t ) 0x00 )
 
-/* At the time of writing, the BSP only supports EL3. */
-#define portINITIAL_PSTATE				( portEL3 | portSP_EL0 )
+#if GUEST
+	#define portEL1						( ( StackType_t ) 0x04 )
+	#define portINITIAL_PSTATE				( portEL1 | portSP_EL0 )
+#else
+	#define portEL3						( ( StackType_t ) 0x0c )
+	/* At the time of writing, the BSP only supports EL3. */
+	#define portINITIAL_PSTATE			( portEL3 | portSP_EL0 )
+#endif
+
 
 /* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
 point is zero. */
@@ -329,7 +335,9 @@ uint32_t ulAPSR;
 
 		/* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
 		value. */
-		configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY );
+
+		configASSERT( ucMaxPriorityValue >= portLOWEST_INTERRUPT_PRIORITY );
+
 
 		/* Restore the clobbered interrupt priority register to its original
 		value. */
@@ -341,9 +349,13 @@ uint32_t ulAPSR;
 	/* At the time of writing, the BSP only supports EL3. */
 	__asm volatile ( "MRS %0, CurrentEL" : "=r" ( ulAPSR ) );
 	ulAPSR &= portAPSR_MODE_BITS_MASK;
+#if GUEST
+	configASSERT( ulAPSR == portEL1 );
+	if( ulAPSR == portEL1 )
+#else
 	configASSERT( ulAPSR == portEL3 );
-
 	if( ulAPSR == portEL3 )
+#endif
 	{
 		/* Only continue if the binary point value is set to its lowest possible
 		setting.  See the comments in vPortValidateInterruptPriority() below for
@@ -423,7 +435,11 @@ void vPortExitCritical( void )
 void FreeRTOS_Tick_Handler( void )
 {
 	/* Must be the lowest possible priority. */
-	configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER == ( uint32_t ) ( portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
+	#if( !QEMU )
+	{
+		configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER == ( uint32_t ) ( portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
+	}
+	#endif
 
 	/* Interrupts should not be enabled before this point. */
 	#if( configASSERT_DEFINED == 1 )
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portASM.S b/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portASM.S
index ad12a68a8..c55aff563 100644
--- a/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portASM.S
+++ b/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portASM.S
@@ -111,10 +111,14 @@
 	STP 	X30, XZR, [SP, #-0x10]!
 
 	/* Save the SPSR. */
+#if GUEST
+	MRS		X3, SPSR_EL1
+	MRS		X2, ELR_EL1
+#else
 	MRS		X3, SPSR_EL3
-
 	/* Save the ELR. */
 	MRS		X2, ELR_EL3
+#endif
 
 	STP 	X2, X3, [SP, #-0x10]!
 
@@ -217,11 +221,17 @@
 1:
 	LDP 	X2, X3, [SP], #0x10  /* SPSR and ELR. */
 
+#if GUEST
+	/* Restore the SPSR. */
+	MSR		SPSR_EL1, X3
+	/* Restore the ELR. */
+	MSR		ELR_EL1, X2
+#else
 	/* Restore the SPSR. */
 	MSR		SPSR_EL3, X3 /*_RB_ Assumes started in EL3. */
-
 	/* Restore the ELR. */
 	MSR		ELR_EL3, X2
+#endif
 
 	LDP 	X30, XZR, [SP], #0x10
 	LDP 	X28, X29, [SP], #0x10
@@ -256,10 +266,19 @@
 FreeRTOS_SWI_Handler:
 	/* Save the context of the current task and select a new task to run. */
 	portSAVE_CONTEXT
-
+#if GUEST
+	MRS		X0, ESR_EL1
+#else
 	MRS		X0, ESR_EL3
+#endif
+
 	LSR		X1, X0, #26
-	CMP		X1, #0x17 /* 0x17 = SMC instruction. */
+
+#if GUEST
+	CMP		X1, #0x15 	/* 0x15 = SVC instruction. */
+#else
+	CMP		X1, #0x17 	/* 0x17 = SMC instruction. */
+#endif
 	B.NE	FreeRTOS_Abort
 	BL 		vTaskSwitchContext
 
@@ -279,7 +298,11 @@ vPortRestoreTaskContext:
 
 	/* Install the FreeRTOS interrupt handlers. */
 	LDR		X1, =freertos_vector_base
+#if GUEST
+	MSR		VBAR_EL1, X1
+#else
 	MSR		VBAR_EL3, X1
+#endif
 	DSB		SY
 	ISB		SY
 
@@ -307,8 +330,13 @@ FreeRTOS_IRQ_Handler:
 	STP		X29, X30, [SP, #-0x10]!
 
 	/* Save the SPSR and ELR. */
+#if GUEST
+	MRS		X3, SPSR_EL1
+	MRS		X2, ELR_EL1
+#else
 	MRS		X3, SPSR_EL3
 	MRS		X2, ELR_EL3
+#endif
 	STP 	X2, X3, [SP, #-0x10]!
 
 	/* Increment the interrupt nesting counter. */
@@ -365,8 +393,13 @@ FreeRTOS_IRQ_Handler:
 
 	/* Restore volatile registers. */
 	LDP 	X4, X5, [SP], #0x10  /* SPSR and ELR. */
+#if GUEST
+	MSR		SPSR_EL1, X5
+	MSR		ELR_EL1, X4
+#else
 	MSR		SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */
 	MSR		ELR_EL3, X4
+#endif
 	DSB		SY
 	ISB		SY
 
@@ -390,8 +423,13 @@ FreeRTOS_IRQ_Handler:
 Exit_IRQ_No_Context_Switch:
 	/* Restore volatile registers. */
 	LDP 	X4, X5, [SP], #0x10  /* SPSR and ELR. */
+#if GUEST
+	MSR		SPSR_EL1, X5
+	MSR		ELR_EL1, X4
+#else
 	MSR		SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */
 	MSR		ELR_EL3, X4
+#endif
 	DSB		SY
 	ISB		SY
 
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h
index a617b829b..3fe8cf645 100644
--- a/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h
+++ b/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h
@@ -128,8 +128,11 @@ extern uint64_t ullPortYieldRequired;			\
 }
 
 #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-#define portYIELD() __asm volatile ( "SMC 0" )
-
+#if GUEST
+	#define portYIELD() __asm volatile ( "SVC 0" )
+#else
+	#define portYIELD() __asm volatile ( "SMC 0" )
+#endif
 /*-----------------------------------------------------------
  * Critical section control
  *----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c b/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c
index ff0abc740..856ff0d29 100644
--- a/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c
+++ b/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c
@@ -475,7 +475,7 @@ void xPortSysTickHandler( void )
 
 	__attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
 	{
-	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickCTRL;
+	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
 	TickType_t xModifiableIdleTime;
 
 		/* Make sure the SysTick reload value does not overflow the counter. */
@@ -551,18 +551,21 @@ void xPortSysTickHandler( void )
 			}
 			configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
 
-			/* Stop SysTick.  Again, the time the SysTick is stopped for is
-			accounted for as best it can be, but using the tickless mode will
-			inevitably result in some tiny drift of the time maintained by the
-			kernel with respect to calendar time. */
-			ulSysTickCTRL = portNVIC_SYSTICK_CTRL_REG;
-			portNVIC_SYSTICK_CTRL_REG = ( ulSysTickCTRL & ~portNVIC_SYSTICK_ENABLE_BIT );
-
 			/* Re-enable interrupts - see comments above the cpsid instruction()
 			above. */
 			__asm volatile( "cpsie i" );
-
-			if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+			
+			/* Disable the SysTick clock without reading the 
+			portNVIC_SYSTICK_CTRL_REG register to ensure the 
+			portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. */
+			portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+			/* Determine if the SysTick clock has already counted to zero and
+			been set back to the current reload value (the reload back being
+			correct for the entire expected idle time) or if the SysTick is yet
+			to count to zero (in which case an interrupt other than the SysTick
+			must have brought the system out of sleep mode). */
+			if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
 			{
 				uint32_t ulCalculatedLoadValue;
 
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CR5/portASM.S b/FreeRTOS/Source/portable/GCC/ARM_CR5/portASM.S
index 13b971342..50380967e 100644
--- a/FreeRTOS/Source/portable/GCC/ARM_CR5/portASM.S
+++ b/FreeRTOS/Source/portable/GCC/ARM_CR5/portASM.S
@@ -230,16 +230,17 @@ FreeRTOS_IRQ_Handler:
 	LDR		r0, [r2]
 
 	/* Ensure bit 2 of the stack pointer is clear.  r2 holds the bit 2 value for
-	future use. */
+	future use.  _RB_ Is this ever needed provided the start of the stack is
+	alligned on an 8-byte boundary? */
 	MOV		r2, sp
 	AND		r2, r2, #4
 	SUB		sp, sp, r2
 
 	/* Call the interrupt handler. */
-	PUSH	{r0-r3, lr}
+	PUSH	{r0-r4, lr}
 	LDR		r1, vApplicationIRQHandlerConst
 	BLX		r1
-	POP		{r0-r3, lr}
+	POP		{r0-r4, lr}
 	ADD		sp, sp, r2
 
 	CPSID	i
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CA9/portASM.s b/FreeRTOS/Source/portable/IAR/ARM_CA9/portASM.s
index cc9a2c721..918d0f960 100644
--- a/FreeRTOS/Source/portable/IAR/ARM_CA9/portASM.s
+++ b/FreeRTOS/Source/portable/IAR/ARM_CA9/portASM.s
@@ -128,16 +128,16 @@ FreeRTOS_IRQ_Handler
 	LDR		r0, [r2]
 
 	; Ensure bit 2 of the stack pointer is clear.  r2 holds the bit 2 value for
-	; future use.
+	; future use.  _RB_ Is this ever necessary if start of stack is 8-byte aligned?
 	MOV		r2, sp
 	AND		r2, r2, #4
 	SUB		sp, sp, r2
 
-	; Call the interrupt handler
-	PUSH	{r0-r3, lr}
+	; Call the interrupt handler.  r4 is pushed to maintain alignment.
+	PUSH	{r0-r4, lr}
 	LDR		r1, =vApplicationIRQHandler
 	BLX		r1
-	POP		{r0-r3, lr}
+	POP		{r0-r4, lr}
 	ADD		sp, sp, r2
 
 	CPSID	i
author	rtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>	2017-01-19 04:11:21 +0000
committer	rtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>	2017-01-19 04:11:21 +0000
commit	4e30ef7c7f124be2098e1547438d5fd7cb067830 (patch)
tree	8195f00ea5a59be9acbc668a0422ee252a8456c0
parent	64addb5a73e5f925fec27252c63a290f8ba4cc3b (diff)
download	freertos-4e30ef7c7f124be2098e1547438d5fd7cb067830.tar.gz