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* Roll up the minor changes checked into svn since V10.0.0 into new V10.0.1 ↵rtel2017-12-181596-4759/+3167
| | | | | | ready for release. git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2524 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Update license information text files for the CLI, TCP and UDP products to ↵rtel2017-12-133-7/+57
| | | | | | be correct for V10. git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2523 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* FreeRTOS+TCP: Added ipconfigSOCKET_HAS_USER_WAKE_CALLBACK configuration ↵rtel2017-12-1210-81/+174
| | | | | | | | | | | option so the user can specify a callback to execute when data arrives. FreeRTOS+TCP: Improve print output when using WinPCap to assist in selecting the correct network interface. FreeRTOS kernel: Fix extern "C" { in stream_buffer.h. FreeRTOS kernel: Correct tskKERNEL_VERSION_NUMBER and tskKERNEL_VERSION_MAJOR constants for V10. Ensure the currently executing task is printed correctly in vTaskList(). git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2522 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Update to MIT licensed FreeRTOS V10.0.0 - see ↵rtel2017-11-291862-205598/+68775
| | | | | | https://www.freertos.org/History.txt git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2519 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Add missing +TCP code.rtel2017-08-1718-499/+11693
| | | | git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2518 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Added +TCP code to main repo.rtel2017-08-17114-446/+46629
| | | | git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2517 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Update TriCore port to work with latest GCC compiler.rtel2017-08-093-11/+11
| | | | git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2516 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Update trace recorder source to fix some compile time warnings.rtel2017-06-0121-5935/+3
| | | | git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2515 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Add MSVC .vs directory to keep the IDE's windows layout.rtel2017-06-011-0/+0
| | | | git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2514 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Correct long time mis-spelled portINITIAL_EXEC_RETURN to portINITIAL_EXC_RETURNrtel2017-05-3016-68/+68
| | | | git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2513 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Update linker script so main stack starts on 8-byte alignment.rtel2017-05-301-1/+1
| | | | git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2512 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Update IAR project for MSP432 to IAR version 8.11.rtel2017-05-305-117/+90
| | | | git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2511 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* FreeRTOS.h changes to go with the last tasks.c checkin.rtel2017-05-291-0/+4
| | | | git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2510 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Remove obsolete code from prvCheckTasksWaitingTermination().rtel2017-05-292-26/+19
| | | | git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2509 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Fix typo in comment that got copied into multiple main.c file.srtel2017-05-294-12/+12
| | | | git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2508 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Update the FreeRTOS_Plus_CLI_with_Trace_Windows_Simulator demo to use the ↵rtel2017-05-299-488/+595
| | | | | | latest FreeRTOS+Trace recorder code. git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2507 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Update the MSVC and MingW demos to use the latest FreeRTOS+Trace recorder ↵rtel2017-05-2913-919/+1194
| | | | | | library. git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2506 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Update to the latest trace recorder library.rtel2017-05-2934-6229/+12895
| | | | git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2505 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Remove configurations other than 'debug' from the Win32 demo.rtel2017-05-072-133/+5
| | | | git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2504 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Cosmetic changes only.rtel2017-04-266-59/+59
| | | | git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2503 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Updated name of CORTEX_MPU_CEC_MEC_17xx_Keil_GCC to ↵rtel2017-04-2043-0/+0
| | | | | | CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC. git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2502 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Added traceQUEUE_CREATE_FAILED() trace macros into the queue create functions.rtel2017-04-101-0/+8
| | | | git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2501 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Add more "memory" clobbers into the MPU ports to make them robust to more ↵rtel2017-04-102-47/+93
| | | | | | aggressive optimisation in newer GCC version. git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2500 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Add more "memory" clobbers into asm code of GCC/ARM_CRx_No_GIC port to make ↵rtel2017-04-102-6/+6
| | | | | | it robust with higher optimisation in newer versions of GCC. git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2499 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Updates to prevent warnings when compiled with LLVM.rtel2017-04-104-25/+79
| | | | git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2498 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Ensure the PIC32 interrupt stack is 8 byte aligned for all values of ↵rtel2017-04-094-8/+14
| | | | | | configISR_STACK_SIZE. git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2497 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* PIC32MZ project using later MPLAB X tools.rtel2017-04-096-103/+111
| | | | git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2496 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Change name of the CEC and MEC directory to ↵rtel2017-04-0483-0/+0
| | | | | | CORTEX_CEC_MEC_17xx_51xx_Keil_GCC as it is also applicable to the MEC5105 part. git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2495 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Change name of the CEC and MEC directory to ↵rtel2017-04-0443-0/+0
| | | | | | CORTEX_MPU_CEC_MEC_17xx_51xx_Keil_GCC as it is also applicable to the MEC5105 part. git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2494 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Updates to the Cortex-M tickless idle code to reduce clock slippage.rtel2017-03-2816-516/+697
| | | | | | Updates to prevent the vTaskSwitchContext() function being removed from GCC builds when link time optimisation is used. git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2493 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Enable button interrupts in the MSP432 demos in order to test code paths ↵rtel2017-03-282-2/+44
| | | | | | when an MCU exits low power mode for a reason other than a tick interrupt. git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2492 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Ensure vTaskGetInfo() sets the sate of the currently running task to ↵rtel2017-03-271-23/+30
| | | | | | eRunning - previously it was set to eReady. git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2491 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Maintenance on MSP432 demo.rtel2017-03-099-7961/+9332
| | | | git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2490 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Housekeeping check-in, no code changes.rtel2017-03-0822-22/+22
| | | | git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2489 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Add CEC and MEC 17xx demo that is completely statically allocated. NOT ↵rtel2017-03-0840-0/+16555
| | | | | | FULLY TESTED YET. git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2488 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Add additional memory barriers into ARM GCC asm code to ensure no ↵rtel2017-03-0716-98/+100
| | | | | | re-ordering across asm code as optimisers get more aggressive. git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2487 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Introduce vTaskInternalSetTimeOutState() which does not have a critical ↵rtel2017-02-246-10/+33
| | | | | | section, and add a critical section to the public version of the same. git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2486 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Add SimpleLink CC3220SF demo.rtel2017-02-24138-0/+75502
| | | | git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2485 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Update Reliance Edge fail safe file system to the latest version.rtel2017-01-2430-5544/+5877
| | | | git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2484 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Update version number in preparation for maintenance release.rtel2017-01-221369-1394/+1395
| | | | git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2483 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Update UltraScale R5 hardware definition and BSP for 2016.4 SDK tools.rtel2017-01-2111-2971/+10914
| | | | git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2482 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Update Zynq MPSoC hardware definition and BSP files to be those shipped with ↵rtel2017-01-19229-5051/+19067
| | | | | | the 2016.4 SDK. git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2481 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Update BSP source files for UltraScale Cortex-A53 and Cortex-R5 and ↵rtel2017-01-19267-2156/+8326
| | | | | | | | | | Microblaze to the 2016.4 versions. Correct alignment issue in GCC Cortex-R port that was preventing full floating point usage in interrupts (other ports will be updated likewise). Update the UltraScale R5 demo to test the GCC Cortex-A9 port layer modification mentioned on the line above. git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2480 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Correct alignment issue in GCC and RVDS Cortex-A9 port that was preventing ↵rtel2017-01-1822-309/+78
| | | | | | | | full floating point usage in interrupts (other ports will be updated likewise). Update the Zynq demo to test the GCC Cortex-A9 port layer modification mentioned on the line above. git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2479 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Enhanced priority dis-inheritance functionality in the case where a task ↵rtel2017-01-167-52/+521
| | | | | | | | | that caused another task to inherit its priority times out before obtain a mutex. Added test code to GenQTest to test the new priority dis-inheritance functionality. Allow the default names given to the Idle and Timer tasks to be overwridden by definitions in FreeRTOSConfig.h. git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2478 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Rename the CORTEX_MPU_MEC17xx_KEIL_GCC directory to ↵rtel2017-01-0944-1/+4
| | | | | | CORTEX_MPU_CEC_MEC_Keil_GCC as it is also applicable to the CEC17xx parts. git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2477 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Change how volatile is used in some of the standard demos to remove compiler ↵rtel2017-01-045-17/+18
| | | | | | warnings in the latest GCC versions. git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2476 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Increase the priority of the Windows threads used by the FreeRTOS Windows ↵rtel2017-01-042-45/+49
| | | | | | port, and, because the threads have high priority and run on the same core, prevent the port running on single core hosts so as to avoid locking up the host. git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2475 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Add MPU project for multiple MEC17xx devices.rtel2016-12-1143-0/+19030
| | | | git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2474 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
* Update TaskNotify.c to test the condition where a direct to task ↵rtel2016-11-2514-221/+1594
| | | | | | | | | | | | | notification is sent to a suspended task. Introduce configSTACK_DEPTH_TYPE so the application writer change the type used to specify a stack size from uint16_t to whatever they like. Defaults to uint16_t if not defined. Introduce configINITIAL_TICK_COUNT to allow users to start the tick count at something other than 0. Used for testing, but overflows can be better tested by setting configUSE_16_BIT_TICKS to 1. Split xQueueGenericReceive() into xQueueReceive(), xQueuePeek() and xQueueSemaphoreTake() as the first step in refactoring xQueueGenericReceive(). Add Cortex-M3 port layer for Code Composer Studio - previously there was only a Cortex-M4F port. Introduce configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING() to allow applications to prevent portSUPPRESS_TICKS_AND_SLEEP() being called. Previously the portPRE_SLEEP_PROCESSING() macro could only be used to abort entry into sleep time after clocks had been re-programmed for the distant wake time. git-svn-id: http://svn.code.sf.net/p/freertos/code/trunk@2473 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
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