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* Demo project only: rtel2014-10-0111-69/+2214
* Demo project only: Cyclone V SoC now running from external RAM.rtel2014-10-012-2/+14
* Added project for Altera Cyclone V SoC, currently running from internal RAM.rtel2014-09-30108-0/+431276
* Core kernel code:rtel2014-09-169-163/+493
* SAM4L tickless implementation: Bug fix and update the demo project to exerci...rtel2014-09-167-159/+715
* Demo project only:rtel2014-09-125-4/+14
* Demo tasks only, with the aim of improving test coverage:rtel2014-09-114-101/+488
* Update version number to 8.1.2 after moving the defaulting of configUSE_PORT_...rtel2014-09-021210-1220/+1274
* Demo code only:rtel2014-09-0211-411/+1409
* Correct potential compiler warning when configUSE_MUTEXES is set to 0.rtel2014-08-304-24/+25
* Update version number to 8.1.1 for patch release that re-enables mutexes to b...rtel2014-08-291217-1241/+12205
* Core kernel code:rtel2014-08-2913-173/+376
* Lower the minimum stack size used by the ATSAMA5 demo.rtel2014-08-261-2/+2
* Minor edits prior to tagging V8.1.0.rtel2014-08-2612-1398/+125
* ***IMMINENT RELEASE NOTICE***rtel2014-08-161213-1219/+1220
* Demo application related:rtel2014-08-1637-120/+259
* General maintenance - changing comments and correcting spellings only.rtel2014-08-044-3/+10
* Common demo tasks:rtel2014-08-0421-596/+213
* Cortex-A5 IAR port:rtel2014-08-031-6/+5
* Cortex-A5 IAR port baseline prior to removing all SAMA5 specifics to make it ...rtel2014-08-034-14/+15
* Continue working on the GIC-less Cortex-A5 port for IAR:rtel2014-07-293-19/+26
* Carry on working on SAMA5D3 demo:rtel2014-07-2914-85/+205
* SAMA5D3 demo: Add CDC driver code and use CDC to create a simple command con...rtel2014-07-2350-509/+8851
* Re-test Zynq demo now it is using the latest tools.rtel2014-07-145-9/+12
* Add back Zynq demo - this time using SDK V14.2.rtel2014-07-14381-0/+269762
* Remove Zynq demo project ready to recreate the project using the 14.2 version...rtel2014-07-1481-182982/+0
* Add 'full' demo to the SAMA5 Xplained demo - but so far without interrupt nes...rtel2014-07-1211-39/+1270
* Rename ARM_CAx_No_GIC ARM_CA5_No_GIC and add FreeRTOSConfig setting to specif...rtel2014-07-124-0/+4
* SAMA5D3 Xplained demo blinky running.rtel2014-07-1215-368/+112
* Add new port layer for Cortex-A devices without the means to mask interrupt p...rtel2014-07-124-0/+856
* Start of SAMA5D3 XPlained demo.rtel2014-07-09277-0/+67714
* Make the parameters to vPortDefineHeapRegions() const.rtel2014-07-045-6/+44
* Update the MSVC simulator demo to demonstrate heap_5 allocator and pdTICKS_TO...rtel2014-07-035-30/+87
* Simply some of the alignment calculations in heap_4.c to match those used in ...rtel2014-07-033-38/+50
* Check in the portable.h version required to use heap_5.c.rtel2014-07-021-0/+21
* Check in the new memory allocator that allows the heap to span multiple blocks.rtel2014-07-021-0/+519
* Update timer demo in PIC32MZ demo to remove multiple extern definition create...rtel2014-06-161-1/+0
* Implementation of mutex held counting in tasks.c - needs optimisation before ...rtel2014-06-161-20/+64
* Default the definition of portASSERT_IF_IN_ISR() to nothing if it is not defi...rtel2014-06-167-26/+79
* Add code to assert() if non ISR safe API function is called from ISR in Taski...rtel2014-06-152-0/+17
* Add code to assert() if non ISR safe API function is called from ISR in IAR a...rtel2014-06-147-5/+62
* Simplify the assert that checks if a non-ISR safe function is called from an ...rtel2014-06-131-12/+9
* Add additional comments to the Zynq lwIP demo.rtel2014-06-132-2/+16
* Added portASSERT_IF_IN_INTERRUPT() macro to the GCC Cortex A9 port layer.rtel2014-06-121-4/+15
* Zynq demo: Fix Xilinx network driver by deferring the function that allocate...rtel2014-06-127-36/+78
* Remove some of the lwip asserts to allow use with 64-bit alignment.rtel2014-06-102-2/+4
* Switch to using the private watchdog as the run time stats timer in the Zynq ...rtel2014-06-107-20/+56
* Reorganise Zynq project after spitting lwIP example into a separate configura...rtel2014-06-0955-155/+88
* Move the Zynq's lwIP example from the Full demo into its own configuration as...rtel2014-06-099-53/+273
* Update lwIP byte alignment to make Zynq pings more reliable.rtel2014-06-094-17/+33
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