diff options
| author | rsandifo <rsandifo@138bc75d-0d04-0410-961f-82ee72b054a4> | 2015-09-25 11:54:22 +0000 |
|---|---|---|
| committer | rsandifo <rsandifo@138bc75d-0d04-0410-961f-82ee72b054a4> | 2015-09-25 11:54:22 +0000 |
| commit | e9fd1d1b34815215aa1398fd7be361dd8d6d5593 (patch) | |
| tree | fb1e10e7a1da69a790d20a6e1ded81fbfd66b4aa | |
| parent | 3f6183e5e3f1466640a80fd1cdc982dff415f226 (diff) | |
| download | gcc-e9fd1d1b34815215aa1398fd7be361dd8d6d5593.tar.gz | |
[AArch64] Force __builtin_aarch64_fp[sc]r argument into a REG
The testcase triggered an ICE because the builtin expansion
code passed the output of expand_normal directly to the SET_FP[SC]R
generator, without forcing it into a register first.
gcc/
* config/aarch64/aarch64-builtins.c (aarch64_expand_builtin): Force
__builtin_aarch64_fp[sc]r arguments into a register.
gcc/testsuite/
* gcc.target/aarch64/fpcr_fpsr_1.c: New file.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@228116 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64-builtins.c | 2 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/fpcr_fpsr_1.c | 26 |
4 files changed, 36 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index fbc353d381d..97b6cdc4fe7 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2015-09-25 Richard Sandiford <richard.sandiford@arm.com> + + * config/aarch64/aarch64-builtins.c (aarch64_expand_builtin): Force + __builtin_aarch64_fp[sc]r arguments into a register. + 2015-09-25 H.J. Lu <hongjiu.lu@intel.com> * config.gcc (x86_archs): Replace lakemount with lakemont. diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c index 4ed2a8b6cb0..80916a9fca2 100644 --- a/gcc/config/aarch64/aarch64-builtins.c +++ b/gcc/config/aarch64/aarch64-builtins.c @@ -1171,7 +1171,7 @@ aarch64_expand_builtin (tree exp, icode = (fcode == AARCH64_BUILTIN_SET_FPSR) ? CODE_FOR_set_fpsr : CODE_FOR_set_fpcr; arg0 = CALL_EXPR_ARG (exp, 0); - op0 = expand_normal (arg0); + op0 = force_reg (SImode, expand_normal (arg0)); pat = GEN_FCN (icode) (op0); } emit_insn (pat); diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 325a692f15a..07858088f7d 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2015-09-25 Richard Sandiford <richard.sandiford@arm.com> + + * gcc.target/aarch64/fpcr_fpsr_1.c: New file. + 2015-09-25 H.J. Lu <hongjiu.lu@intel.com> * gcc.target/i386/pr66749.c (dg-options): Replace diff --git a/gcc/testsuite/gcc.target/aarch64/fpcr_fpsr_1.c b/gcc/testsuite/gcc.target/aarch64/fpcr_fpsr_1.c new file mode 100644 index 00000000000..29aa1f4cc96 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fpcr_fpsr_1.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +void +f1 (int *x) +{ + __builtin_aarch64_set_fpsr (*x); +} + +void +f2 (int *x) +{ + __builtin_aarch64_set_fpcr (*x); +} + +void +f3 (int *x) +{ + *x = __builtin_aarch64_get_fpsr (); +} + +void +f4 (int *x) +{ + *x = __builtin_aarch64_get_fpcr (); +} |