Support scheduling for ColdFire V1 and V3 microarchitecture.

	Improve scheduling of multiplication instructions.

	* config/m68k/m68k.md (cpu): Add cfv1 and cfv3.  Rename cf_v2 to cfv1.
	(mac): New instruction attribute.
	* config/m68k/m68k.c (override_options): Handle cfv1, cfv3 and mac.
	(m68k_sched_mac): New variable.
	(m68k_sched_attr_type2, m68k_sched_md_init_global): Update.
	Handle cfv1 and cfv3.
	(max_insn_size): New static variable.
	(struct _sched_ib): New type.
	(sched_ib): New static variable.
	(sched_ib_size, sched_ib_filled, sched_ib_insn): Convert variables
	to fields of 'struct _sched_ib sched_ib'.  Update all uses.
	(m68k_sched_variable_issue): Add modeling of cfv3 instruction buffer.
	Update.
	(m68k_sched_md_init_global, m68k_sched_md_finish_global,
	m68k_sched_md_init, m68k_sched_md_finish): Handle cfv1 and cfv3.  Init
	new variables.  Update.
	(m68k_sched_dfa_pre_advance_cycle, m68k_sched_dfa_post_advance_cycle):
	Add modeling of cfv3 instruction buffer.  Update.
	* config/m68k/m68k-protos.h (m68k_sched_mac): Declare.
	* config/m68k/m68k.h (TUNE_CFV3): New macro.
	* config/m68k/cf.md: Change substrings 'cf_v2' to 'cfv12' or 'cfv123'.
	(cf_* reservations): Rename to cfv12 or cfv123 to indicate cores
	a particular reservation applies to.
	(type2): Reorganize attribute values.  Rename alu to alu_reg,
	alu_l to alu, move_l to omove.  Join move to alu.  Split mul
	to mul_l and mul_w.
	(cf_ib_*): Simplify description of instruction buffer.
	(cf_ib_w0, cf_ib_w4, cf_ib_w5, cf_ib_w6): Remove.
	(cf_mem): Split into cf_mem1 and cf_mem2.
	(cf_v2_move_??): Rename to cfv12_alu_??.
	(cf_v2_move_l_??): Rename to cfv12_omove_??.
	(cf_v2_mul_??): Remove reservations.
	(cfv12_mul_l_??, cfv12_mul_w_??, cfv12_mac_w_??, cfv12_mac_l_??,
	cfv12_emac_??, cfv12_emac_w_i0): New reservations.
	(cfv12_rts, cfv12_call, cfv12_bcc, cfv12_bra, cfv12_jmp): Move to
	appropriate place.
	(cfv3_alu_10, cfv3_omove_10, cfv3_alu_i0, cfv3_omove_i0, cfv3_alu_01,
	cfv3_alu_0i, cfv3_alu_11, cfv3_omove_11, cfv3_alu_i1, cfv3_omove_i1,
	cfv3_alu_1i, cfv3_omove_1i, cfv3_pea_11, cfv3_pea_i1, cfv3_mul_w_10,
	cfv3_mul_l_10, cfv3_mul_w_i0, cfv3_mac_w_10, cfv3_mac_l_10,
	cfv3_mac_w_i0, cfv3_emac_10, cfv3_emac_w_i0, cfv3_rts, cfv3_call,
	cfv3_bcc, cfv3_bra, cfv3_jmp): New reservations.
	(cfv3_*_1, cfv3_*_2, cfv3_*_3): New instruction reservations that are
	expansions of the above reservations for instructions of sizes
	1, 2 and 3 words.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@134552 138bc75d-0d04-0410-961f-82ee72b054a4

6 files changed, 1434 insertions, 397 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6396413c6c8..3a1566b9d3e 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,56 @@
 2008-04-22  Maxim Kuvyrkov  <maxim@codesourcery.com>
 
+	Support scheduling for ColdFire V1 and V3 microarchitecture.
+	Improve scheduling of multiplication instructions.
+
+	* config/m68k/m68k.md (cpu): Add cfv1 and cfv3.  Rename cf_v2 to cfv1.
+	(mac): New instruction attribute.
+	* config/m68k/m68k.c (override_options): Handle cfv1, cfv3 and mac.
+	(m68k_sched_mac): New variable.
+	(m68k_sched_attr_type2, m68k_sched_md_init_global): Update.
+	Handle cfv1 and cfv3.
+	(max_insn_size): New static variable.
+	(struct _sched_ib): New type.
+	(sched_ib): New static variable.
+	(sched_ib_size, sched_ib_filled, sched_ib_insn): Convert variables
+	to fields of 'struct _sched_ib sched_ib'.  Update all uses.
+	(m68k_sched_variable_issue): Add modeling of cfv3 instruction buffer.
+	Update.
+	(m68k_sched_md_init_global, m68k_sched_md_finish_global,
+	m68k_sched_md_init, m68k_sched_md_finish): Handle cfv1 and cfv3.  Init
+	new variables.  Update.
+	(m68k_sched_dfa_pre_advance_cycle, m68k_sched_dfa_post_advance_cycle):
+	Add modeling of cfv3 instruction buffer.  Update.
+	* config/m68k/m68k-protos.h (m68k_sched_mac): Declare.
+	* config/m68k/m68k.h (TUNE_CFV3): New macro.
+	* config/m68k/cf.md: Change substrings 'cf_v2' to 'cfv12' or 'cfv123'.
+	(cf_* reservations): Rename to cfv12 or cfv123 to indicate cores
+	a particular reservation applies to.
+	(type2): Reorganize attribute values.  Rename alu to alu_reg,
+	alu_l to alu, move_l to omove.  Join move to alu.  Split mul
+	to mul_l and mul_w.
+	(cf_ib_*): Simplify description of instruction buffer.
+	(cf_ib_w0, cf_ib_w4, cf_ib_w5, cf_ib_w6): Remove.
+	(cf_mem): Split into cf_mem1 and cf_mem2.
+	(cf_v2_move_??): Rename to cfv12_alu_??.
+	(cf_v2_move_l_??): Rename to cfv12_omove_??.
+	(cf_v2_mul_??): Remove reservations.
+	(cfv12_mul_l_??, cfv12_mul_w_??, cfv12_mac_w_??, cfv12_mac_l_??,
+	cfv12_emac_??, cfv12_emac_w_i0): New reservations.
+	(cfv12_rts, cfv12_call, cfv12_bcc, cfv12_bra, cfv12_jmp): Move to
+	appropriate place.
+	(cfv3_alu_10, cfv3_omove_10, cfv3_alu_i0, cfv3_omove_i0, cfv3_alu_01,
+	cfv3_alu_0i, cfv3_alu_11, cfv3_omove_11, cfv3_alu_i1, cfv3_omove_i1,
+	cfv3_alu_1i, cfv3_omove_1i, cfv3_pea_11, cfv3_pea_i1, cfv3_mul_w_10,
+	cfv3_mul_l_10, cfv3_mul_w_i0, cfv3_mac_w_10, cfv3_mac_l_10,
+	cfv3_mac_w_i0, cfv3_emac_10, cfv3_emac_w_i0, cfv3_rts, cfv3_call,
+	cfv3_bcc, cfv3_bra, cfv3_jmp): New reservations.
+	(cfv3_*_1, cfv3_*_2, cfv3_*_3): New instruction reservations that are
+	expansions of the above reservations for instructions of sizes
+	1, 2 and 3 words.
+
+2008-04-22  Maxim Kuvyrkov  <maxim@codesourcery.com>
+
 	* rtl-factoring.c (collect_patterns_seqs): Handle CC0 targets.
 
 2008-04-21  Adam Nemet  <anemet@caviumnetworks.com>
diff --git a/gcc/config/m68k/cf.md b/gcc/config/m68k/cf.md
index b9c135c9901..546e99557db 100644
--- a/gcc/config/m68k/cf.md
+++ b/gcc/config/m68k/cf.md
@@ -1,4 +1,4 @@
-;; ColdFire V2 DFA description.
+;; ColdFire V1, V2 and V3 DFA description.
 ;; Copyright (C) 2007 Free Software Foundation, Inc.
 ;; Contributed by CodeSourcery Inc.
 ;;
@@ -19,171 +19,322 @@
 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
 ;; Boston, MA 02110-1301, USA.
 
+;; Intruction types recognized by DFA.
+;; This attribute correspond to type1 attribute with the exceptions below.
+;; omove - optimized move.  All explicit loads on cfv1 and long explicit
+;;         loads on cfv2 execute one cycle faster then they should.
+;;         Supposedly, that is due to combined instruction decoding
+;;         and address generation phases.
 ;; ??? To let genattrtab live, implement this attribute in C.
 (define_attr "type2"
-  "alu, alu_l, bcc, bra, call, jmp, lea, move, move_l, mul, pea, rts, unlk,
-   unknown"
+  "alu, alu_reg, bcc, bra, call, jmp, lea, mul_l, mul_w, omove, pea,
+   rts, unlk, unknown"
   (symbol_ref "m68k_sched_attr_type2 (insn)"))
 
 ;; Instruction Buffer
-(define_automaton "cf_v2_ib")
-
-;; If one of these cpu units is occupied, that means that corresponding
-;; word in the buffer is empty.
-(define_cpu_unit "cf_v2_ib_w0, cf_v2_ib_w1, cf_v2_ib_w2, cf_v2_ib_w3, cf_v2_ib_w4, cf_v2_ib_w5" "cf_v2_ib")
-
-(final_presence_set "cf_v2_ib_w1, cf_v2_ib_w2, cf_v2_ib_w3, cf_v2_ib_w4, cf_v2_ib_w5" "cf_v2_ib_w0")
-(final_presence_set "cf_v2_ib_w2, cf_v2_ib_w3, cf_v2_ib_w4, cf_v2_ib_w5" "cf_v2_ib_w1")
-(final_presence_set "cf_v2_ib_w3, cf_v2_ib_w4, cf_v2_ib_w5" "cf_v2_ib_w2")
-(final_presence_set "cf_v2_ib_w4, cf_v2_ib_w5" "cf_v2_ib_w3")
-(final_presence_set "cf_v2_ib_w5" "cf_v2_ib_w4")
-
-;; Occupy 1 word.
-(define_reservation "cf_v2_ib1" "cf_v2_ib_w0|cf_v2_ib_w1|cf_v2_ib_w2|cf_v2_ib_w3|cf_v2_ib_w4|cf_v2_ib_w5")
-
-;; Occupy 2 words.
-(define_reservation "cf_v2_ib2" "(cf_v2_ib_w0+cf_v2_ib_w1)|(cf_v2_ib_w1+cf_v2_ib_w2)|(cf_v2_ib_w2+cf_v2_ib_w3)|(cf_v2_ib_w3+cf_v2_ib_w4)|(cf_v2_ib_w4+cf_v2_ib_w5)")
-
-;; Occupy 3 words.
-(define_reservation "cf_v2_ib3" "(cf_v2_ib_w0+cf_v2_ib_w1+cf_v2_ib_w2)|(cf_v2_ib_w1+cf_v2_ib_w2+cf_v2_ib_w3)|(cf_v2_ib_w2+cf_v2_ib_w3+cf_v2_ib_w4)|(cf_v2_ib_w3+cf_v2_ib_w4+cf_v2_ib_w5)")
-
-;; Reservation to subscribe 1 word in the instruction buffer.  If a given
-;; word in the instruction buffer is subscribed, that means it is empty.
-;; This reservation is used at the start of each cycle to setup the number
-;; of prefetched instruction words in the instruction buffer.
-;; At each cycle, given that memory bus is available (i.e. there is no
-;; pending memory operation), IFP prefetches two instruction words into IB.
-(define_insn_reservation "cf_v2_ib" 0
-  (and (eq_attr "cpu" "cf_v2")
+(define_automaton "cf_ib")
+
+;; These pseudo units are used to model instruction buffer of ColdFire cores.
+;; Instruction of size N can be issued only when cf_ib_wN is available.
+(define_cpu_unit "cf_ib_w1, cf_ib_w2, cf_ib_w3" "cf_ib")
+
+;; Instruction occupies 1 word in the instruction buffer.
+(define_reservation "cf_ib1" "cf_ib_w1")
+;; Instruction occupies 2 words in the instruction buffer.
+(define_reservation "cf_ib2" "cf_ib_w1+cf_ib_w2")
+;; Instruction occupies 3 words in the instruction buffer.
+(define_reservation "cf_ib3" "cf_ib_w1+cf_ib_w2+cf_ib_w3")
+
+;; This reservation is used at the start of each cycle to setup the maximal
+;; length of instruction that can be issued on current cycle.
+;; E.g., when this reservation is applied for the first time, cf_ib_w3
+;; resource is marked busy, thus filtering out all 3-word insns.
+;;
+;; This reservation requires deterministic automaton.
+;;
+;; At each cycle, given that memory bus is available (i.e., there is no
+;; pending memory operation), instruction fetch pipeline (IFP) prefetches
+;; two instruction words into instruction buffer (IB).
+(define_insn_reservation "cf_ib1" 0
+  (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
        (eq_attr "type" "ib"))
-  "cf_v2_ib1")
+  "cf_ib_w3|cf_ib_w2|cf_ib_w1")
 
 ;; Operand Execution Pipeline
-(define_automaton "cf_v2_oep")
+(define_automaton "cf_oep")
 
-(define_cpu_unit "cf_v2_dsoc, cf_v2_agex" "cf_v2_oep")
+(define_cpu_unit "cf_dsoc, cf_agex" "cf_oep")
 
 ;; A memory unit that is reffered to as 'certain hardware resources' in
 ;; ColdFire reference manuals.  This unit remains occupied for two cycles
 ;; after last dsoc cycle of a store - hence there is a 2 cycle delay between
 ;; two consecutive stores.
-(define_automaton "cf_v2_chr")
+(define_automaton "cf_chr")
 
-(define_cpu_unit "cf_v2_chr" "cf_v2_chr")
+(define_cpu_unit "cf_chr" "cf_chr")
 
 ;; Memory bus
-(define_automaton "cf_v2_mem")
+(define_automaton "cf_mem")
 
 ;; When memory bus is subscribed, that implies that instruction buffer won't
-;; get its portion this cycle.  To model that we query if cf_v2_mem unit is
+;; get its portion this cycle.  To model that we query if cf_mem unit is
 ;; subscribed and adjust number of prefetched instruction words accordingly.
 ;; 
-(define_query_cpu_unit "cf_v2_mem" "cf_v2_mem")
+(define_query_cpu_unit "cf_mem1, cf_mem2" "cf_mem")
+
+(define_reservation "cf_mem" "cf_mem1+cf_mem2")
 
 ;; Register to register move.
 ;; Takes 1 cycle.
-(define_reservation "cf_v2_move_00"
-  "cf_v2_dsoc+cf_v2_agex")
+(define_reservation "cfv123_alu_00"
+  "cf_dsoc,cf_agex")
 
 ;; Load from a memory location.
 ;; Takes 3 cycles.
-(define_reservation "cf_v2_move_10"
-  "cf_v2_dsoc,cf_v2_agex,cf_v2_dsoc+cf_v2_mem,cf_v2_agex")
-
-;; Long load from a memory location.
+(define_reservation "cfv12_alu_10"
+  "cf_dsoc,cf_agex,cf_dsoc+cf_mem,cf_agex")
 ;; Takes 2 cycles.
-(define_reservation "cf_v2_move_l_10"
-  "cf_v2_dsoc+cf_v2_agex,cf_v2_dsoc+cf_v2_mem,cf_v2_agex")
+(define_reservation "cfv12_omove_10"
+  "cf_dsoc+cf_agex,cf_dsoc+cf_mem,cf_agex")
+;; Takes 4 cycles.
+(define_reservation "cfv3_alu_10"
+  "cf_dsoc,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex")
+;; Takes 3 cycles.
+(define_reservation "cfv3_omove_10"
+  "cf_dsoc+cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex")
 
 ;; Load from an indexed location.
 ;; Takes 4 cycles.
-(define_reservation "cf_v2_move_i0"
-  "cf_v2_dsoc,cf_v2_agex,cf_v2_agex,cf_v2_dsoc+cf_v2_mem,cf_v2_agex")
-
-;; Long load from an indexed location.
+(define_reservation "cfv12_alu_i0"
+  "cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem,cf_agex")
 ;; Takes 3 cycles.
-(define_reservation "cf_v2_move_l_i0"
-  "cf_v2_dsoc+cf_v2_agex,cf_v2_agex,cf_v2_dsoc+cf_v2_mem,cf_v2_agex")
+(define_reservation "cfv12_omove_i0"
+  "cf_dsoc+cf_agex,cf_agex,cf_dsoc+cf_mem,cf_agex")
+;; Takes 5 cycles.
+(define_reservation "cfv3_alu_i0"
+  "cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex")
+;; Takes 4 cycles.
+(define_reservation "cfv3_omove_i0"
+  "cf_dsoc+cf_agex,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex")
 
 ;; Store to a memory location.
 ;; Takes 1 cycle.
-(define_reservation "cf_v2_move_01"
-  "cf_v2_dsoc+cf_v2_agex+cf_v2_chr,cf_v2_mem+cf_v2_chr,cf_v2_chr")
+(define_reservation "cfv12_alu_01"
+  "cf_dsoc+cf_agex+cf_chr,cf_mem+cf_chr,cf_chr")
+;; Takes 1 cycle.
+(define_reservation "cfv3_alu_01"
+  "cf_dsoc+cf_agex+cf_chr,cf_mem1+cf_chr,cf_mem2+cf_chr")
 
 ;; Store to an indexed location.
-;; Takes 2 cycle.
-(define_reservation "cf_v2_move_0i"
-  "cf_v2_dsoc+cf_v2_agex,cf_v2_agex+cf_v2_chr,cf_v2_mem+cf_v2_chr,cf_v2_chr")
+;; Takes 2 cycles.
+(define_reservation "cfv12_alu_0i"
+  "cf_dsoc+cf_agex,cf_agex+cf_chr,cf_mem+cf_chr,cf_chr")
+;; Takes 2 cycles.
+(define_reservation "cfv3_alu_0i"
+  "cf_dsoc+cf_agex,cf_agex+cf_chr,cf_mem1+cf_chr,cf_mem2+cf_chr")
 
 ;; Load from a memory location and store to a memory location.
 ;; Takes 3 cycles
-(define_reservation "cf_v2_move_11"
-  "cf_v2_dsoc,cf_v2_agex,cf_v2_dsoc+cf_v2_agex+cf_v2_mem+cf_v2_chr,cf_v2_mem+cf_v2_chr,cf_v2_chr")
-
-;; Long load from a memory location and store to a memory location.
+(define_reservation "cfv12_alu_11"
+  "cf_dsoc,cf_agex,cf_dsoc+cf_mem,cf_agex+cf_chr,cf_mem+cf_chr,cf_chr")
 ;; Takes 2 cycles.
-(define_reservation "cf_v2_move_l_11"
-  "cf_v2_dsoc+cf_v2_agex,cf_v2_dsoc+cf_v2_agex+cf_v2_mem+cf_v2_chr,cf_v2_mem+cf_v2_chr,cf_v2_chr")
+(define_reservation "cfv12_omove_11"
+  "cf_dsoc+cf_agex,cf_dsoc+cf_mem,cf_agex+cf_chr,cf_mem+cf_chr,cf_chr")
+;; Takes 4 cycles
+(define_reservation "cfv3_alu_11"
+  "cf_dsoc,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex+cf_chr,cf_mem1+cf_chr,cf_mem2+cf_chr")
+;; Takes 3 cycles.
+(define_reservation "cfv3_omove_11"
+  "cf_dsoc+cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex+cf_chr,cf_mem1+cf_chr,cf_mem2+cf_chr")
 
 ;; Load from an indexed location and store to a memory location.
 ;; Takes 4 cycles.
-(define_reservation "cf_v2_move_i1"
-  "cf_v2_dsoc,cf_v2_agex,cf_v2_agex,cf_v2_dsoc+cf_v2_agex+cf_v2_mem+cf_v2_chr,cf_v2_mem+cf_v2_chr,cf_v2_chr")
-
-;; Long load from an indexed location and store to a memory location.
+(define_reservation "cfv12_alu_i1"
+  "cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem,cf_agex+cf_chr,cf_mem+cf_chr,cf_chr")
 ;; Takes 3 cycles.
-(define_reservation "cf_v2_move_l_i1"
-  "cf_v2_dsoc+cf_v2_agex,cf_v2_agex,cf_v2_dsoc+cf_v2_agex+cf_v2_mem+cf_v2_chr,cf_v2_mem+cf_v2_chr,cf_v2_chr")
+(define_reservation "cfv12_omove_i1"
+  "cf_dsoc+cf_agex,cf_agex,cf_dsoc+cf_mem,cf_agex+cf_chr,cf_mem+cf_chr,cf_chr")
+;; Takes 5 cycles.
+(define_reservation "cfv3_alu_i1"
+  "cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex+cf_chr,cf_mem1+cf_chr,cf_mem2+cf_chr")
+;; Takes 4 cycles.
+(define_reservation "cfv3_omove_i1"
+  "cf_dsoc+cf_agex,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex+cf_chr,cf_mem1+cf_chr,cf_mem2+cf_chr")
 
 ;; Load from a memory location and store to an indexed location.
 ;; Takes 4 cycles.
-(define_reservation "cf_v2_move_1i"
-  "cf_v2_dsoc,cf_v2_agex,cf_v2_dsoc+cf_v2_agex+cf_v2_mem,cf_v2_agex,cf_v2_mem")
-
-;; Long load from a memory location and store to an indexed location.
+(define_reservation "cfv12_alu_1i"
+  "cf_dsoc,cf_agex,cf_dsoc+cf_mem,cf_agex,cf_agex+cf_chr,cf_mem+cf_chr,cf_chr")
 ;; Takes 3 cycles.
-(define_reservation "cf_v2_move_l_1i"
-  "cf_v2_dsoc+cf_v2_agex,cf_v2_dsoc+cf_v2_agex+cf_v2_mem,cf_v2_agex,cf_v2_mem")
+(define_reservation "cfv12_omove_1i"
+  "cf_dsoc+cf_agex,cf_dsoc+cf_mem,cf_agex,cf_agex+cf_chr,cf_mem+cf_chr,cf_chr")
+;; Takes 5 cycles.
+(define_reservation "cfv3_alu_1i"
+  "cf_dsoc,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex,cf_agex+cf_chr,cf_mem1+cf_chr,cf_mem2+cf_chr")
+;; Takes 4 cycles.
+(define_reservation "cfv3_omove_1i"
+  "cf_dsoc+cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex,cf_agex+cf_chr,cf_mem1+cf_chr,cf_mem2+cf_chr")
 
 ;; Lea operation for a memory location.
 ;; Takes 1 cycle.
-(define_reservation "cf_v2_lea_10"
-  "cf_v2_dsoc+cf_v2_agex")
+(define_reservation "cfv123_lea_10"
+  "cf_dsoc,cf_agex")
 
 ;; Lea operation for an indexed location.
 ;; Takes 2 cycles.
-(define_reservation "cf_v2_lea_i0"
-  "cf_v2_dsoc+cf_v2_agex,cf_v2_agex")
+(define_reservation "cfv123_lea_i0"
+  "cf_dsoc,cf_agex,cf_agex")
 
 ;; Pea operation for a memory location.
-;; Takes 2 cycle.
-(define_reservation "cf_v2_pea_11"
-  "cf_v2_dsoc+cf_v2_agex,cf_v2_agex+cf_v2_chr,cf_v2_mem+cf_v2_chr,cf_v2_chr")
+;; Takes 2 cycles.
+(define_reservation "cfv12_pea_11"
+  "cf_dsoc,cf_agex,cf_agex+cf_chr,cf_mem+cf_chr,cf_chr")
+;; Takes 2 cycles.
+(define_reservation "cfv3_pea_11"
+  "cf_dsoc,cf_agex,cf_agex+cf_chr,cf_mem1+cf_chr,cf_mem2+cf_chr")
 
 ;; Pea operation for an indexed location.
 ;; Takes 3 cycles.
-(define_reservation "cf_v2_pea_i1"
-  "cf_v2_dsoc+cf_v2_agex,cf_v2_agex,cf_v2_agex+cf_v2_chr,cf_v2_mem+cf_v2_chr,cf_v2_chr")
+(define_reservation "cfv12_pea_i1"
+  "cf_dsoc,cf_agex,cf_agex,cf_agex+cf_chr,cf_mem+cf_chr,cf_chr")
+;; Takes 3 cycles.
+(define_reservation "cfv3_pea_i1"
+  "cf_dsoc,cf_agex,cf_agex,cf_agex+cf_chr,cf_mem1+cf_chr,cf_mem2+cf_chr")
+
+;; Long multiplication with no mac.
+;; Takes 9-18 cycles.
+(define_reservation "cfv123_mul_l_00"
+  "cf_dsoc,(cf_agex+cf_dsoc)*17,cf_agex")
+
+;; Word multiplication with no mac.
+;; Takes 9 cycles.
+(define_reservation "cfv123_mul_w_00"
+  "cf_dsoc,(cf_agex+cf_dsoc)*8,cf_agex")
+
+;; Long multiplication with no mac.
+;; Takes 11-20 cycles.
+(define_reservation "cfv12_mul_l_10"
+  "cf_dsoc,cf_agex,cf_dsoc+cf_mem,(cf_agex+cf_dsoc)*17,cf_agex")
+;; Takes 12-21 cycles.
+(define_reservation "cfv3_mul_l_10"
+  "cf_dsoc,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,(cf_agex+cf_dsoc)*17,cf_agex")
+
+;; Word multiplication with no mac.
+;; Takes 11 cycles.
+(define_reservation "cfv12_mul_w_10"
+  "cf_dsoc,cf_agex,cf_dsoc+cf_mem,(cf_agex+cf_dsoc)*8,cf_agex")
+;; Takes 12 cycles.
+(define_reservation "cfv3_mul_w_10"
+  "cf_dsoc,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,(cf_agex+cf_dsoc)*8,cf_agex")
+
+;; Word multiplication with no mac.
+;; Takes 12 cycles.
+(define_reservation "cfv12_mul_w_i0"
+  "cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem,(cf_agex+cf_dsoc)*8,cf_agex")
+;; Takes 13 cycles.
+(define_reservation "cfv3_mul_w_i0"
+  "cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,(cf_agex+cf_dsoc)*8,cf_agex")
+
+(define_automaton "cf_mac")
+
+(define_cpu_unit "cf_mac1,cf_mac2,cf_mac3,cf_mac4"
+  "cf_mac")
+
+;; Long multiplication with mac.
+;; Takes 5 cycles.
+(define_reservation "cfv123_mac_l_00"
+  "cf_dsoc,cf_agex,cf_mac1,cf_mac2,cf_mac3,cf_mac4")
+
+;; Word multiplication with mac.
+;; Takes 3 cycles.
+(define_reservation "cfv123_mac_w_00"
+  "cf_dsoc,cf_agex,cf_mac1,cf_mac2")
 
-(define_automaton "cf_v2_emac")
+;; Long multiplication with mac.
+;; Takes 7 cycles.
+(define_reservation "cfv12_mac_l_10"
+  "cf_dsoc,cf_agex,cf_dsoc+cf_mem,cf_agex,cf_mac1,cf_mac2,cf_mac3,cf_mac4")
+;; Takes 8 cycles.
+(define_reservation "cfv3_mac_l_10"
+  "cf_dsoc,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex,cf_mac1,cf_mac2,cf_mac3,cf_mac4")
+
+;; Word multiplication with mac.
+;; Takes 5 cycles.
+(define_reservation "cfv12_mac_w_10"
+  "cf_dsoc,cf_agex,cf_dsoc+cf_mem,cf_agex,cf_mac1,cf_mac2")
+;; Takes 6 cycles.
+(define_reservation "cfv3_mac_w_10"
+  "cf_dsoc,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex,cf_mac1,cf_mac2")
 
-(define_cpu_unit "cf_v2_emac1,cf_v2_emac2,cf_v2_emac3,cf_v2_emac4"
-  "cf_v2_emac")
+;; Word multiplication with mac.
+;; Takes 6 cycles.
+(define_reservation "cfv12_mac_w_i0"
+  "cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem,cf_agex,cf_mac1,cf_mac2")
+;; Takes 7 cycles.
+(define_reservation "cfv3_mac_w_i0"
+  "cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex,cf_mac1,cf_mac2")
 
-;; Mul operation with register operands.
+;; Multiplication with emac.
 ;; Takes 4 cycles.
-(define_reservation "cf_v2_mul_00"
-  "cf_v2_dsoc,cf_v2_agex+cf_v2_emac1,cf_v2_emac2,cf_v2_emac3,cf_v2_emac4")
+(define_reservation "cfv123_emac_00"
+  "cf_dsoc,cf_agex+cf_mac1,cf_mac2,cf_mac3,cf_mac4")
 
-;; Mul operation with implicit load from a memory location.
+;; Multiplication with emac.
 ;; Takes 6 cycles.
-(define_reservation "cf_v2_mul_10"
-  "cf_v2_dsoc,cf_v2_agex,cf_v2_dsoc+cf_v2_mem,cf_v2_agex+cf_v2_emac1,cf_v2_emac2,cf_v2_emac3,cf_v2_emac4")
+(define_reservation "cfv12_emac_10"
+  "cf_dsoc,cf_agex,cf_dsoc+cf_mem,cf_agex+cf_mac1,cf_mac2,cf_mac3,cf_mac4")
+;; Takes 7 cycles.
+(define_reservation "cfv3_emac_10"
+  "cf_dsoc,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex+cf_mac1,cf_mac2,cf_mac3,cf_mac4")
 
-;; Mul operation with implicit load from an indexed location.
+;; Word multiplication with emac.
 ;; Takes 7 cycles.
-(define_reservation "cf_v2_mul_i0"
-  "cf_v2_dsoc,cf_v2_agex,cf_v2_agex,cf_v2_dsoc+cf_v2_mem,cf_v2_agex+cf_v2_emac1,cf_v2_emac2,cf_v2_emac3,cf_v2_emac4")
+(define_reservation "cfv12_emac_w_i0"
+  "cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem,cf_agex+cf_mac1,cf_mac2,cf_mac3,cf_mac4")
+;; Takes 8 cycles.
+(define_reservation "cfv3_emac_w_i0"
+  "cf_dsoc,cf_agex,cf_agex,cf_dsoc+cf_mem1,cf_dsoc+cf_mem2,cf_agex+cf_mac1,cf_mac2,cf_mac3,cf_mac4")
+
+;; Return instruction.
+;; ??? As return reads target address from stack, use a mem-read reservation
+;; ??? for it.
+;; ??? It's not clear what the core does during these 5 cycles.
+;; ??? Luckily, we don't care that much about an insn that won't be moved.
+;; Takes 5 cycles.
+(define_reservation "cfv12_rts" "cfv12_alu_10")
+;; Takes 8 cycles.
+(define_reservation "cfv3_rts" "cfv3_alu_10")
+
+;; Call instruction.
+;; ??? It's not clear what reservation is best to use for calls.
+;; ??? For now we use mem-write + return reservations to reflect the fact of
+;; ??? pushing and poping return address to and from the stack.
+;; Takes 3 cycles.
+(define_reservation "cfv12_call" "cfv12_alu_01,cfv12_rts")
+;; Takes 1/5 cycles.
+(define_reservation "cfv3_call" "cfv3_alu_01,cfv3_rts")
+
+;; Conditional branch instruction.
+;; ??? Branch reservations are unclear to me so far.  Luckily, we don't care
+;; ??? that much about branches.
+;; Takes 2 cycles.
+(define_reservation "cfv12_bcc" "cfv123_alu_00")
+;; Takes 1 cycles.
+(define_reservation "cfv3_bcc" "cfv123_alu_00")
+
+;; Unconditional branch instruciton.
+;; Takes 2 cycles.
+(define_reservation "cfv12_bra" "cfv12_alu_01")
+;; Takes 1 cycles.
+(define_reservation "cfv3_bra" "cfv3_alu_01")
+
+;; Computed jump instruction.
+;; Takes 3 cycles.
+(define_reservation "cfv12_jmp"
+  "(cf_dsoc+cf_agex)*3")
+;; Takes 5 cycles.
+(define_reservation "cfv3_jmp"
+  "(cf_dsoc+cf_agex)*5")
 
 ;; Instruction reservations.
 
@@ -192,488 +343,1186 @@
 ;; for each instruction size.
 ;; A number in the end of reservation's name is the size of the instruction.
 
-(define_insn_reservation "cf_v2_move_00_1" 1
-  (and (and (and (eq_attr "cpu" "cf_v2")
-		 (eq_attr "type2" "alu,alu_l,move,move_l"))
+(define_insn_reservation "cfv123_alu_00_1" 1
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
+		 (eq_attr "type2" "alu,alu_reg,omove"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
        (eq_attr "op_mem" "00"))
-  "cf_v2_ib1+cf_v2_move_00")
+  "cf_ib1+cfv123_alu_00")
 
-(define_insn_reservation "cf_v2_move_00_2" 1
-  (and (and (and (eq_attr "cpu" "cf_v2")
-		 (eq_attr "type2" "alu,alu_l,move,move_l"))
+(define_insn_reservation "cfv123_alu_00_2" 1
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
+		 (eq_attr "type2" "alu,alu_reg,omove"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
        (eq_attr "op_mem" "00"))
-  "cf_v2_ib2+cf_v2_move_00")
+  "cf_ib2+cfv123_alu_00")
 
-(define_insn_reservation "cf_v2_move_00_3" 1
-  (and (and (and (eq_attr "cpu" "cf_v2")
-		 (eq_attr "type2" "alu,alu_l,move,move_l"))
+(define_insn_reservation "cfv123_alu_00_3" 1
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
+		 (eq_attr "type2" "alu,alu_reg,omove"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
        (eq_attr "op_mem" "00"))
-  "cf_v2_ib3+cf_v2_move_00")
+  "cf_ib3+cfv123_alu_00")
+
+(define_insn_reservation "cfv12_alu_10_1" 3
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		 (eq_attr "type2" "alu"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
+       (eq_attr "op_mem" "10"))
+  "cf_ib1+cfv12_alu_10")
+
+(define_insn_reservation "cfv12_alu_10_2" 3
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		 (eq_attr "type2" "alu"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+       (eq_attr "op_mem" "10"))
+  "cf_ib2+cfv12_alu_10")
 
-(define_insn_reservation "cf_v2_move_10_1" 4
-  (and (and (and (eq_attr "cpu" "cf_v2")
-		 (eq_attr "type2" "alu_l,move"))
+(define_insn_reservation "cfv12_alu_10_3" 3
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		 (eq_attr "type2" "alu"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+       (eq_attr "op_mem" "10"))
+  "cf_ib3+cfv12_alu_10")
+
+(define_insn_reservation "cfv12_omove_10_1" 2
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		 (eq_attr "type2" "omove"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
        (eq_attr "op_mem" "10"))
-  "cf_v2_ib1+cf_v2_move_10")
+  "cf_ib1+cfv12_omove_10")
 
-(define_insn_reservation "cf_v2_move_10_2" 4
-  (and (and (and (eq_attr "cpu" "cf_v2")
-		 (eq_attr "type2" "alu_l,move"))
+(define_insn_reservation "cfv12_omove_10_2" 2
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		 (eq_attr "type2" "omove"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
        (eq_attr "op_mem" "10"))
-  "cf_v2_ib2+cf_v2_move_10")
+  "cf_ib2+cfv12_omove_10")
 
-(define_insn_reservation "cf_v2_move_10_3" 4
-  (and (and (and (eq_attr "cpu" "cf_v2")
-		 (eq_attr "type2" "alu_l,move"))
+(define_insn_reservation "cfv12_omove_10_3" 2
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		 (eq_attr "type2" "omove"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
        (eq_attr "op_mem" "10"))
-  "cf_v2_ib3+cf_v2_move_10")
+  "cf_ib3+cfv12_omove_10")
 
-(define_insn_reservation "cf_v2_move_l_10_1" 3
-  (and (and (and (eq_attr "cpu" "cf_v2")
-		 (eq_attr "type2" "move_l"))
+(define_insn_reservation "cfv3_alu_10_1" 4
+  (and (and (and (eq_attr "cpu" "cfv3")
+		 (eq_attr "type2" "alu"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
        (eq_attr "op_mem" "10"))
-  "cf_v2_ib1+cf_v2_move_l_10")
+  "cf_ib1+cfv3_alu_10")
 
-(define_insn_reservation "cf_v2_move_l_10_2" 3
-  (and (and (and (eq_attr "cpu" "cf_v2")
-		 (eq_attr "type2" "move_l"))
+(define_insn_reservation "cfv3_alu_10_2" 4
+  (and (and (and (eq_attr "cpu" "cfv3")
+		 (eq_attr "type2" "alu"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
        (eq_attr "op_mem" "10"))
-  "cf_v2_ib2+cf_v2_move_l_10")
+  "cf_ib2+cfv3_alu_10")
 
-(define_insn_reservation "cf_v2_move_l_10_3" 3
-  (and (and (and (eq_attr "cpu" "cf_v2")
-		 (eq_attr "type2" "move_l"))
+(define_insn_reservation "cfv3_alu_10_3" 4
+  (and (and (and (eq_attr "cpu" "cfv3")
+		 (eq_attr "type2" "alu"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
        (eq_attr "op_mem" "10"))
-  "cf_v2_ib3+cf_v2_move_l_10")
+  "cf_ib3+cfv3_alu_10")
+
+(define_insn_reservation "cfv3_omove_10_1" 3
+  (and (and (and (eq_attr "cpu" "cfv3")
+		 (eq_attr "type2" "omove"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
+       (eq_attr "op_mem" "10"))
+  "cf_ib1+cfv3_omove_10")
+
+(define_insn_reservation "cfv3_omove_10_2" 3
+  (and (and (and (eq_attr "cpu" "cfv3")
+		 (eq_attr "type2" "omove"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+       (eq_attr "op_mem" "10"))
+  "cf_ib2+cfv3_omove_10")
+
+(define_insn_reservation "cfv3_omove_10_3" 3
+  (and (and (and (eq_attr "cpu" "cfv3")
+		 (eq_attr "type2" "omove"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+       (eq_attr "op_mem" "10"))
+  "cf_ib3+cfv3_omove_10")
+
+(define_insn_reservation "cfv12_alu_i0_2" 4
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		 (eq_attr "type2" "alu"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+       (eq_attr "op_mem" "i0"))
+  "cf_ib2+cfv12_alu_i0")
+
+(define_insn_reservation "cfv12_alu_i0_3" 4
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		 (eq_attr "type2" "alu"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+       (eq_attr "op_mem" "i0"))
+  "cf_ib3+cfv12_alu_i0")
 
-(define_insn_reservation "cf_v2_move_i0_2" 5
-  (and (and (and (eq_attr "cpu" "cf_v2")
-		 (eq_attr "type2" "alu_l,move"))
+(define_insn_reservation "cfv12_omove_i0_2" 3
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		 (eq_attr "type2" "omove"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
        (eq_attr "op_mem" "i0"))
-  "cf_v2_ib2+cf_v2_move_i0")
+  "cf_ib2+cfv12_omove_i0")
 
-(define_insn_reservation "cf_v2_move_i0_3" 5
-  (and (and (and (eq_attr "cpu" "cf_v2")
-		 (eq_attr "type2" "alu_l,move"))
+(define_insn_reservation "cfv12_omove_i0_3" 3
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		 (eq_attr "type2" "omove"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
        (eq_attr "op_mem" "i0"))
-  "cf_v2_ib3+cf_v2_move_i0")
+  "cf_ib3+cfv12_omove_i0")
 
-(define_insn_reservation "cf_v2_move_l_i0_2" 4
-  (and (and (and (eq_attr "cpu" "cf_v2")
-		 (eq_attr "type2" "move_l"))
+(define_insn_reservation "cfv3_alu_i0_2" 5
+  (and (and (and (eq_attr "cpu" "cfv3")
+		 (eq_attr "type2" "alu"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
        (eq_attr "op_mem" "i0"))
-  "cf_v2_ib2+cf_v2_move_l_i0")
+  "cf_ib2+cfv3_alu_i0")
 
-(define_insn_reservation "cf_v2_move_l_i0_3" 4
-  (and (and (and (eq_attr "cpu" "cf_v2")
-		 (eq_attr "type2" "move_l"))
+(define_insn_reservation "cfv3_alu_i0_3" 5
+  (and (and (and (eq_attr "cpu" "cfv3")
+		 (eq_attr "type2" "alu"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
        (eq_attr "op_mem" "i0"))
-  "cf_v2_ib3+cf_v2_move_l_i0")
+  "cf_ib3+cfv3_alu_i0")
+
+(define_insn_reservation "cfv3_omove_i0_2" 4
+  (and (and (and (eq_attr "cpu" "cfv3")
+		 (eq_attr "type2" "omove"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+       (eq_attr "op_mem" "i0"))
+  "cf_ib2+cfv3_omove_i0")
 
-(define_insn_reservation "cf_v2_move_01_1" 0
-  (and (and (and (eq_attr "cpu" "cf_v2")
-		 (eq_attr "type2" "alu_l,move,move_l"))
+(define_insn_reservation "cfv3_omove_i0_3" 4
+  (and (and (and (eq_attr "cpu" "cfv3")
+		 (eq_attr "type2" "omove"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+       (eq_attr "op_mem" "i0"))
+  "cf_ib3+cfv3_omove_i0")
+
+(define_insn_reservation "cfv12_alu_01_1" 0
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		 (eq_attr "type2" "alu,omove"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
        (eq_attr "op_mem" "01"))
-  "cf_v2_ib1+cf_v2_move_01")
+  "cf_ib1+cfv12_alu_01")
 
-(define_insn_reservation "cf_v2_move_01_2" 0
-  (and (and (and (eq_attr "cpu" "cf_v2")
-		 (eq_attr "type2" "alu_l,move,move_l"))
+(define_insn_reservation "cfv12_alu_01_2" 0
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		 (eq_attr "type2" "alu,omove"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
        (eq_attr "op_mem" "01"))
-  "cf_v2_ib2+cf_v2_move_01")
+  "cf_ib2+cfv12_alu_01")
 
-(define_insn_reservation "cf_v2_move_01_3" 0
-  (and (and (and (eq_attr "cpu" "cf_v2")
-		 (eq_attr "type2" "alu_l,move,move_l"))
+(define_insn_reservation "cfv12_alu_01_3" 0
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		 (eq_attr "type2" "alu,omove"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
        (eq_attr "op_mem" "01"))
-  "cf_v2_ib3+cf_v2_move_01")
+  "cf_ib3+cfv12_alu_01")
+
+(define_insn_reservation "cfv3_alu_01_1" 0
+  (and (and (and (eq_attr "cpu" "cfv3")
+		 (eq_attr "type2" "alu,omove"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
+       (eq_attr "op_mem" "01"))
+  "cf_ib1+cfv3_alu_01")
+
+(define_insn_reservation "cfv3_alu_01_2" 0
+  (and (and (and (eq_attr "cpu" "cfv3")
+		 (eq_attr "type2" "alu,omove"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+       (eq_attr "op_mem" "01"))
+  "cf_ib2+cfv3_alu_01")
+
+(define_insn_reservation "cfv3_alu_01_3" 0
+  (and (and (and (eq_attr "cpu" "cfv3")
+		 (eq_attr "type2" "alu,omove"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+       (eq_attr "op_mem" "01"))
+  "cf_ib3+cfv3_alu_01")
+
+(define_insn_reservation "cfv12_alu_0i_2" 0
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		 (eq_attr "type2" "alu,omove"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+       (eq_attr "op_mem" "0i"))
+  "cf_ib2+cfv12_alu_0i")
+
+(define_insn_reservation "cfv12_alu_0i_3" 0
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		 (eq_attr "type2" "alu,omove"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+       (eq_attr "op_mem" "0i"))
+  "cf_ib3+cfv12_alu_0i")
 
-(define_insn_reservation "cf_v2_move_0i_2" 0
-  (and (and (and (eq_attr "cpu" "cf_v2")
-		 (eq_attr "type2" "alu_l,move,move_l"))
+(define_insn_reservation "cfv3_alu_0i_2" 0
+  (and (and (and (eq_attr "cpu" "cfv3")
+		 (eq_attr "type2" "alu,omove"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
        (eq_attr "op_mem" "0i"))
-  "cf_v2_ib2+cf_v2_move_0i")
+  "cf_ib2+cfv3_alu_0i")
 
-(define_insn_reservation "cf_v2_move_0i_3" 0
-  (and (and (and (eq_attr "cpu" "cf_v2")
-		 (eq_attr "type2" "alu_l,move,move_l"))
+(define_insn_reservation "cfv3_alu_0i_3" 0
+  (and (and (and (eq_attr "cpu" "cfv3")
+		 (eq_attr "type2" "alu,omove"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
        (eq_attr "op_mem" "0i"))
-  "cf_v2_ib3+cf_v2_move_0i")
+  "cf_ib3+cfv3_alu_0i")
 
-(define_insn_reservation "cf_v2_move_11_1" 0
-  (and (and (and (eq_attr "cpu" "cf_v2")
-		 (eq_attr "type2" "alu_l,move"))
+(define_insn_reservation "cfv12_alu_11_1" 0
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		 (eq_attr "type2" "alu"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
        (eq_attr "op_mem" "11"))
-  "cf_v2_ib1+cf_v2_move_11")
+  "cf_ib1+cfv12_alu_11")
 
-(define_insn_reservation "cf_v2_move_11_2" 0
-  (and (and (and (eq_attr "cpu" "cf_v2")
-		 (eq_attr "type2" "alu_l,move"))
+(define_insn_reservation "cfv12_alu_11_2" 0
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		 (eq_attr "type2" "alu"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
        (eq_attr "op_mem" "11"))
-  "cf_v2_ib2+cf_v2_move_11")
+  "cf_ib2+cfv12_alu_11")
 
-(define_insn_reservation "cf_v2_move_11_3" 0
-  (and (and (and (eq_attr "cpu" "cf_v2")
-		 (eq_attr "type2" "alu_l,move"))
+(define_insn_reservation "cfv12_alu_11_3" 0
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		 (eq_attr "type2" "alu"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
        (eq_attr "op_mem" "11"))
-  "cf_v2_ib3+cf_v2_move_11")
+  "cf_ib3+cfv12_alu_11")
 
-(define_insn_reservation "cf_v2_move_l_11_1" 0
-  (and (and (and (eq_attr "cpu" "cf_v2")
-		 (eq_attr "type2" "move_l"))
+(define_insn_reservation "cfv12_omove_11_1" 0
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		 (eq_attr "type2" "omove"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
        (eq_attr "op_mem" "11"))
-  "cf_v2_ib1+cf_v2_move_l_11")
+  "cf_ib1+cfv12_omove_11")
 
-(define_insn_reservation "cf_v2_move_l_11_2" 0
-  (and (and (and (eq_attr "cpu" "cf_v2")
-		 (eq_attr "type2" "move_l"))
+(define_insn_reservation "cfv12_omove_11_2" 0
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		 (eq_attr "type2" "omove"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
        (eq_attr "op_mem" "11"))
-  "cf_v2_ib2+cf_v2_move_l_11")
+  "cf_ib2+cfv12_omove_11")
 
-(define_insn_reservation "cf_v2_move_l_11_3" 0
-  (and (and (and (eq_attr "cpu" "cf_v2")
-		 (eq_attr "type2" "move_l"))
+(define_insn_reservation "cfv12_omove_11_3" 0
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		 (eq_attr "type2" "omove"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
        (eq_attr "op_mem" "11"))
-  "cf_v2_ib3+cf_v2_move_l_11")
+  "cf_ib3+cfv12_omove_11")
+
+(define_insn_reservation "cfv3_alu_11_1" 0
+  (and (and (and (eq_attr "cpu" "cfv3")
+		 (eq_attr "type2" "alu"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
+       (eq_attr "op_mem" "11"))
+  "cf_ib1+cfv3_alu_11")
+
+(define_insn_reservation "cfv3_alu_11_2" 0
+  (and (and (and (eq_attr "cpu" "cfv3")
+		 (eq_attr "type2" "alu"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+       (eq_attr "op_mem" "11"))
+  "cf_ib2+cfv3_alu_11")
+
+(define_insn_reservation "cfv3_alu_11_3" 0
+  (and (and (and (eq_attr "cpu" "cfv3")
+		 (eq_attr "type2" "alu"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+       (eq_attr "op_mem" "11"))
+  "cf_ib3+cfv3_alu_11")
+
+(define_insn_reservation "cfv3_omove_11_1" 0
+  (and (and (and (eq_attr "cpu" "cfv3")
+		 (eq_attr "type2" "omove"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
+       (eq_attr "op_mem" "11"))
+  "cf_ib1+cfv3_omove_11")
+
+(define_insn_reservation "cfv3_omove_11_2" 0
+  (and (and (and (eq_attr "cpu" "cfv3")
+		 (eq_attr "type2" "omove"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+       (eq_attr "op_mem" "11"))
+  "cf_ib2+cfv3_omove_11")
+
+(define_insn_reservation "cfv3_omove_11_3" 0
+  (and (and (and (eq_attr "cpu" "cfv3")
+		 (eq_attr "type2" "omove"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+       (eq_attr "op_mem" "11"))
+  "cf_ib3+cfv3_omove_11")
+
+(define_insn_reservation "cfv12_alu_i1_2" 0
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		 (eq_attr "type2" "alu"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+       (eq_attr "op_mem" "i1"))
+  "cf_ib2+cfv12_alu_i1")
+
+(define_insn_reservation "cfv12_alu_i1_3" 0
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		 (eq_attr "type2" "alu"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+       (eq_attr "op_mem" "i1"))
+  "cf_ib3+cfv12_alu_i1")
 
-(define_insn_reservation "cf_v2_move_i1_2" 0
-  (and (and (and (eq_attr "cpu" "cf_v2")
-		 (eq_attr "type2" "alu_l,move"))
+(define_insn_reservation "cfv12_omove_i1_2" 0
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		 (eq_attr "type2" "omove"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
        (eq_attr "op_mem" "i1"))
-  "cf_v2_ib2+cf_v2_move_i1")
+  "cf_ib2+cfv12_omove_i1")
 
-(define_insn_reservation "cf_v2_move_i1_3" 0
-  (and (and (and (eq_attr "cpu" "cf_v2")
-		 (eq_attr "type2" "alu_l,move"))
+(define_insn_reservation "cfv12_omove_i1_3" 0
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		 (eq_attr "type2" "omove"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
        (eq_attr "op_mem" "i1"))
-  "cf_v2_ib3+cf_v2_move_i1")
+  "cf_ib3+cfv12_omove_i1")
 
-(define_insn_reservation "cf_v2_move_l_i1_2" 0
-  (and (and (and (eq_attr "cpu" "cf_v2")
-		 (eq_attr "type2" "move_l"))
+(define_insn_reservation "cfv3_alu_i1_2" 0
+  (and (and (and (eq_attr "cpu" "cfv3")
+		 (eq_attr "type2" "alu"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
        (eq_attr "op_mem" "i1"))
-  "cf_v2_ib2+cf_v2_move_l_i1")
+  "cf_ib2+cfv3_alu_i1")
 
-(define_insn_reservation "cf_v2_move_l_i1_3" 0
-  (and (and (and (eq_attr "cpu" "cf_v2")
-		 (eq_attr "type2" "move_l"))
+(define_insn_reservation "cfv3_alu_i1_3" 0
+  (and (and (and (eq_attr "cpu" "cfv3")
+		 (eq_attr "type2" "alu"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
        (eq_attr "op_mem" "i1"))
-  "cf_v2_ib3+cf_v2_move_l_i1")
+  "cf_ib3+cfv3_alu_i1")
+
+(define_insn_reservation "cfv3_omove_i1_2" 0
+  (and (and (and (eq_attr "cpu" "cfv3")
+		 (eq_attr "type2" "omove"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+       (eq_attr "op_mem" "i1"))
+  "cf_ib2+cfv3_omove_i1")
+
+(define_insn_reservation "cfv3_omove_i1_3" 0
+  (and (and (and (eq_attr "cpu" "cfv3")
+		 (eq_attr "type2" "omove"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+       (eq_attr "op_mem" "i1"))
+  "cf_ib3+cfv3_omove_i1")
+
+(define_insn_reservation "cfv12_alu_1i_2" 0
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		 (eq_attr "type2" "alu"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+       (eq_attr "op_mem" "1i"))
+  "cf_ib2+cfv12_alu_1i")
+
+(define_insn_reservation "cfv12_alu_1i_3" 0
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		 (eq_attr "type2" "alu"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+       (eq_attr "op_mem" "1i"))
+  "cf_ib3+cfv12_alu_1i")
+
+(define_insn_reservation "cfv12_omove_1i_2" 0
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		 (eq_attr "type2" "omove"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+       (eq_attr "op_mem" "1i"))
+  "cf_ib2+cfv12_omove_1i")
+
+(define_insn_reservation "cfv12_omove_1i_3" 0
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		 (eq_attr "type2" "omove"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+       (eq_attr "op_mem" "1i"))
+  "cf_ib3+cfv12_omove_1i")
 
-(define_insn_reservation "cf_v2_move_1i_2" 0
-  (and (and (and (eq_attr "cpu" "cf_v2")
-		 (eq_attr "type2" "alu_l,move"))
+(define_insn_reservation "cfv3_alu_1i_2" 0
+  (and (and (and (eq_attr "cpu" "cfv3")
+		 (eq_attr "type2" "alu"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
        (eq_attr "op_mem" "1i"))
-  "cf_v2_ib2+cf_v2_move_1i")
+  "cf_ib2+cfv3_alu_1i")
 
-(define_insn_reservation "cf_v2_move_1i_3" 0
-  (and (and (and (eq_attr "cpu" "cf_v2")
-		 (eq_attr "type2" "alu_l,move"))
+(define_insn_reservation "cfv3_alu_1i_3" 0
+  (and (and (and (eq_attr "cpu" "cfv3")
+		 (eq_attr "type2" "alu"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
        (eq_attr "op_mem" "1i"))
-  "cf_v2_ib3+cf_v2_move_1i")
+  "cf_ib3+cfv3_alu_1i")
 
-(define_insn_reservation "cf_v2_move_l_1i_2" 0
-  (and (and (and (eq_attr "cpu" "cf_v2")
-		 (eq_attr "type2" "move_l"))
+(define_insn_reservation "cfv3_omove_1i_2" 0
+  (and (and (and (eq_attr "cpu" "cfv3")
+		 (eq_attr "type2" "omove"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
        (eq_attr "op_mem" "1i"))
-  "cf_v2_ib2+cf_v2_move_l_1i")
+  "cf_ib2+cfv3_omove_1i")
 
-(define_insn_reservation "cf_v2_move_l_1i_3" 0
-  (and (and (and (eq_attr "cpu" "cf_v2")
-		 (eq_attr "type2" "move_l"))
+(define_insn_reservation "cfv3_omove_1i_3" 0
+  (and (and (and (eq_attr "cpu" "cfv3")
+		 (eq_attr "type2" "omove"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
        (eq_attr "op_mem" "1i"))
-  "cf_v2_ib3+cf_v2_move_l_1i")
+  "cf_ib3+cfv3_omove_1i")
 
-(define_insn_reservation "cf_v2_lea_10_1" 1
-  (and (and (and (eq_attr "cpu" "cf_v2")
+(define_insn_reservation "cfv123_lea_10_1" 1
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
 		 (eq_attr "type2" "lea"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
        (eq_attr "op_mem" "10"))
-  "cf_v2_ib1+cf_v2_lea_10")
+  "cf_ib1+cfv123_lea_10")
 
-(define_insn_reservation "cf_v2_lea_10_2" 1
-  (and (and (and (eq_attr "cpu" "cf_v2")
+(define_insn_reservation "cfv123_lea_10_2" 1
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
 		 (eq_attr "type2" "lea"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
        (eq_attr "op_mem" "10"))
-  "cf_v2_ib2+cf_v2_lea_10")
+  "cf_ib2+cfv123_lea_10")
 
-(define_insn_reservation "cf_v2_lea_10_3" 1
-  (and (and (and (eq_attr "cpu" "cf_v2")
+(define_insn_reservation "cfv123_lea_10_3" 1
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
 		 (eq_attr "type2" "lea"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
        (eq_attr "op_mem" "10"))
-  "cf_v2_ib3+cf_v2_lea_10")
+  "cf_ib3+cfv123_lea_10")
 
-(define_insn_reservation "cf_v2_lea_i0_2" 2
-  (and (and (and (eq_attr "cpu" "cf_v2")
+(define_insn_reservation "cfv123_lea_i0_2" 2
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
 		 (eq_attr "type2" "lea"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
        (eq_attr "op_mem" "i0"))
-  "cf_v2_ib2+cf_v2_lea_i0")
+  "cf_ib2+cfv123_lea_i0")
 
-(define_insn_reservation "cf_v2_lea_i0_3" 2
-  (and (and (and (eq_attr "cpu" "cf_v2")
+(define_insn_reservation "cfv123_lea_i0_3" 2
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
 		 (eq_attr "type2" "lea"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
        (eq_attr "op_mem" "i0"))
-  "cf_v2_ib3+cf_v2_lea_i0")
+  "cf_ib3+cfv123_lea_i0")
 
-(define_insn_reservation "cf_v2_pea_11_1" 0
-  (and (and (and (eq_attr "cpu" "cf_v2")
+(define_insn_reservation "cfv12_pea_11_1" 0
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2")
 		 (eq_attr "type2" "pea"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
        (eq_attr "op_mem" "11"))
-  "cf_v2_ib1+cf_v2_pea_11")
+  "cf_ib1+cfv12_pea_11")
 
-(define_insn_reservation "cf_v2_pea_11_2" 0
-  (and (and (and (eq_attr "cpu" "cf_v2")
+(define_insn_reservation "cfv12_pea_11_2" 0
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2")
 		 (eq_attr "type2" "pea"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
        (eq_attr "op_mem" "11"))
-  "cf_v2_ib2+cf_v2_pea_11")
+  "cf_ib2+cfv12_pea_11")
 
-(define_insn_reservation "cf_v2_pea_11_3" 0
-  (and (and (and (eq_attr "cpu" "cf_v2")
+(define_insn_reservation "cfv12_pea_11_3" 0
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2")
 		 (eq_attr "type2" "pea"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
        (eq_attr "op_mem" "11"))
-  "cf_v2_ib3+cf_v2_pea_11")
+  "cf_ib3+cfv12_pea_11")
+
+(define_insn_reservation "cfv3_pea_11_1" 0
+  (and (and (and (eq_attr "cpu" "cfv3")
+		 (eq_attr "type2" "pea"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
+       (eq_attr "op_mem" "11"))
+  "cf_ib1+cfv3_pea_11")
+
+(define_insn_reservation "cfv3_pea_11_2" 0
+  (and (and (and (eq_attr "cpu" "cfv3")
+		 (eq_attr "type2" "pea"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+       (eq_attr "op_mem" "11"))
+  "cf_ib2+cfv3_pea_11")
+
+(define_insn_reservation "cfv3_pea_11_3" 0
+  (and (and (and (eq_attr "cpu" "cfv3")
+		 (eq_attr "type2" "pea"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+       (eq_attr "op_mem" "11"))
+  "cf_ib3+cfv3_pea_11")
+
+(define_insn_reservation "cfv12_pea_i1_2" 0
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		 (eq_attr "type2" "pea"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+       (eq_attr "op_mem" "i1"))
+  "cf_ib2+cfv12_pea_i1")
+
+(define_insn_reservation "cfv12_pea_i1_3" 0
+  (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		 (eq_attr "type2" "pea"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+       (eq_attr "op_mem" "i1"))
+  "cf_ib3+cfv12_pea_i1")
 
-(define_insn_reservation "cf_v2_pea_i1_2" 0
-  (and (and (and (eq_attr "cpu" "cf_v2")
+(define_insn_reservation "cfv3_pea_i1_2" 0
+  (and (and (and (eq_attr "cpu" "cfv3")
 		 (eq_attr "type2" "pea"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
        (eq_attr "op_mem" "i1"))
-  "cf_v2_ib2+cf_v2_pea_i1")
+  "cf_ib2+cfv3_pea_i1")
 
-(define_insn_reservation "cf_v2_pea_i1_3" 0
-  (and (and (and (eq_attr "cpu" "cf_v2")
+(define_insn_reservation "cfv3_pea_i1_3" 0
+  (and (and (and (eq_attr "cpu" "cfv3")
 		 (eq_attr "type2" "pea"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
        (eq_attr "op_mem" "i1"))
-  "cf_v2_ib3+cf_v2_pea_i1")
+  "cf_ib3+cfv3_pea_i1")
+
+(define_insn_reservation "cfv123_mul_l_00_1" 18
+  (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
+		      (eq_attr "mac" "no"))
+		 (eq_attr "type2" "mul_l"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
+       (eq_attr "op_mem" "00"))
+  "cf_ib1+cfv123_mul_l_00")
+
+(define_insn_reservation "cfv123_mul_l_00_2" 18
+  (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
+		      (eq_attr "mac" "no"))
+		 (eq_attr "type2" "mul_l"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+       (eq_attr "op_mem" "00"))
+  "cf_ib2+cfv123_mul_l_00")
+
+(define_insn_reservation "cfv123_mul_l_00_3" 18
+  (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
+		      (eq_attr "mac" "no"))
+		 (eq_attr "type2" "mul_l"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+       (eq_attr "op_mem" "00"))
+  "cf_ib3+cfv123_mul_l_00")
+
+(define_insn_reservation "cfv123_mul_w_00_1" 9
+  (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
+		      (eq_attr "mac" "no"))
+		 (eq_attr "type2" "mul_w"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
+       (eq_attr "op_mem" "00"))
+  "cf_ib1+cfv123_mul_w_00")
+
+(define_insn_reservation "cfv123_mul_w_00_2" 9
+  (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
+		      (eq_attr "mac" "no"))
+		 (eq_attr "type2" "mul_w"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+       (eq_attr "op_mem" "00"))
+  "cf_ib2+cfv123_mul_w_00")
+
+(define_insn_reservation "cfv123_mul_w_00_3" 9
+  (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
+		      (eq_attr "mac" "no"))
+		 (eq_attr "type2" "mul_w"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+       (eq_attr "op_mem" "00"))
+  "cf_ib3+cfv123_mul_w_00")
+
+(define_insn_reservation "cfv12_mul_l_10_1" 20
+  (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		      (eq_attr "mac" "no"))
+		 (eq_attr "type2" "mul_l"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
+       (eq_attr "op_mem" "10"))
+  "cf_ib1+cfv12_mul_l_10")
 
-(define_insn_reservation "cf_v2_mul_00_1" 4
-  (and (and (and (eq_attr "cpu" "cf_v2")
-		 (eq_attr "type2" "mul"))
+(define_insn_reservation "cfv12_mul_l_10_2" 20
+  (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		      (eq_attr "mac" "no"))
+		 (eq_attr "type2" "mul_l"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+       (eq_attr "op_mem" "10"))
+  "cf_ib2+cfv12_mul_l_10")
+
+(define_insn_reservation "cfv12_mul_l_10_3" 20
+  (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		      (eq_attr "mac" "no"))
+		 (eq_attr "type2" "mul_l"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+       (eq_attr "op_mem" "10"))
+  "cf_ib3+cfv12_mul_l_10")
+
+(define_insn_reservation "cfv3_mul_l_10_1" 21
+  (and (and (and (and (eq_attr "cpu" "cfv3")
+		      (eq_attr "mac" "no"))
+		 (eq_attr "type2" "mul_l"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
+       (eq_attr "op_mem" "10"))
+  "cf_ib1+cfv3_mul_l_10")
+
+(define_insn_reservation "cfv3_mul_l_10_2" 21
+  (and (and (and (and (eq_attr "cpu" "cfv3")
+		      (eq_attr "mac" "no"))
+		 (eq_attr "type2" "mul_l"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+       (eq_attr "op_mem" "10"))
+  "cf_ib2+cfv3_mul_l_10")
+
+(define_insn_reservation "cfv3_mul_l_10_3" 21
+  (and (and (and (and (eq_attr "cpu" "cfv3")
+		      (eq_attr "mac" "no"))
+		 (eq_attr "type2" "mul_l"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+       (eq_attr "op_mem" "10"))
+  "cf_ib3+cfv3_mul_l_10")
+
+(define_insn_reservation "cfv12_mul_w_10_1" 11
+  (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		      (eq_attr "mac" "no"))
+		 (eq_attr "type2" "mul_w"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
+       (eq_attr "op_mem" "10"))
+  "cf_ib1+cfv12_mul_w_10")
+
+(define_insn_reservation "cfv12_mul_w_10_2" 11
+  (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		      (eq_attr "mac" "no"))
+		 (eq_attr "type2" "mul_w"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+       (eq_attr "op_mem" "10"))
+  "cf_ib2+cfv12_mul_w_10")
+
+(define_insn_reservation "cfv12_mul_w_10_3" 11
+  (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		      (eq_attr "mac" "no"))
+		 (eq_attr "type2" "mul_w"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+       (eq_attr "op_mem" "10"))
+  "cf_ib3+cfv12_mul_w_10")
+
+(define_insn_reservation "cfv3_mul_w_10_1" 12
+  (and (and (and (and (eq_attr "cpu" "cfv3")
+		      (eq_attr "mac" "no"))
+		 (eq_attr "type2" "mul_w"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
+       (eq_attr "op_mem" "10"))
+  "cf_ib1+cfv3_mul_w_10")
+
+(define_insn_reservation "cfv3_mul_w_10_2" 12
+  (and (and (and (and (eq_attr "cpu" "cfv3")
+		      (eq_attr "mac" "no"))
+		 (eq_attr "type2" "mul_w"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+       (eq_attr "op_mem" "10"))
+  "cf_ib2+cfv3_mul_w_10")
+
+(define_insn_reservation "cfv3_mul_w_10_3" 12
+  (and (and (and (and (eq_attr "cpu" "cfv3")
+		      (eq_attr "mac" "no"))
+		 (eq_attr "type2" "mul_w"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+       (eq_attr "op_mem" "10"))
+  "cf_ib3+cfv3_mul_w_10")
+
+(define_insn_reservation "cfv12_mul_w_i0_2" 12
+  (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		      (eq_attr "mac" "no"))
+		 (eq_attr "type2" "mul_w"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+       (eq_attr "op_mem" "i0"))
+  "cf_ib2+cfv12_mul_w_i0")
+
+(define_insn_reservation "cfv12_mul_w_i0_3" 12
+  (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		      (eq_attr "mac" "no"))
+		 (eq_attr "type2" "mul_w"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+       (eq_attr "op_mem" "i0"))
+  "cf_ib3+cfv12_mul_w_i0")
+
+
+(define_insn_reservation "cfv3_mul_w_i0_2" 13
+  (and (and (and (and (eq_attr "cpu" "cfv3")
+		      (eq_attr "mac" "no"))
+		 (eq_attr "type2" "mul_w"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+       (eq_attr "op_mem" "i0"))
+  "cf_ib2+cfv3_mul_w_i0")
+
+(define_insn_reservation "cfv3_mul_w_i0_3" 13
+  (and (and (and (and (eq_attr "cpu" "cfv3")
+		      (eq_attr "mac" "no"))
+		 (eq_attr "type2" "mul_w"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+       (eq_attr "op_mem" "i0"))
+  "cf_ib3+cfv3_mul_w_i0")
+
+(define_insn_reservation "cfv123_mac_l_00_1" 5
+  (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
+		      (eq_attr "mac" "cf_mac"))
+		 (eq_attr "type2" "mul_l"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
        (eq_attr "op_mem" "00"))
-  "cf_v2_ib1+cf_v2_mul_00")
+  "cf_ib1+cfv123_mac_l_00")
 
-(define_insn_reservation "cf_v2_mul_00_2" 4
-  (and (and (and (eq_attr "cpu" "cf_v2")
-		 (eq_attr "type2" "mul"))
+(define_insn_reservation "cfv123_mac_l_00_2" 5
+  (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
+		      (eq_attr "mac" "cf_mac"))
+		 (eq_attr "type2" "mul_l"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
        (eq_attr "op_mem" "00"))
-  "cf_v2_ib2+cf_v2_mul_00")
+  "cf_ib2+cfv123_mac_l_00")
 
-(define_insn_reservation "cf_v2_mul_00_3" 4
-  (and (and (and (eq_attr "cpu" "cf_v2")
-		 (eq_attr "type2" "mul"))
+(define_insn_reservation "cfv123_mac_l_00_3" 5
+  (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
+		      (eq_attr "mac" "cf_mac"))
+		 (eq_attr "type2" "mul_l"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
        (eq_attr "op_mem" "00"))
-  "cf_v2_ib3+cf_v2_mul_00")
+  "cf_ib3+cfv123_mac_l_00")
+
+(define_insn_reservation "cfv123_mac_w_00_1" 3
+  (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
+		      (eq_attr "mac" "cf_mac"))
+		 (eq_attr "type2" "mul_w"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
+       (eq_attr "op_mem" "00"))
+  "cf_ib1+cfv123_mac_w_00")
+
+(define_insn_reservation "cfv123_mac_w_00_2" 3
+  (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
+		      (eq_attr "mac" "cf_mac"))
+		 (eq_attr "type2" "mul_w"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+       (eq_attr "op_mem" "00"))
+  "cf_ib2+cfv123_mac_w_00")
+
+(define_insn_reservation "cfv123_mac_w_00_3" 3
+  (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
+		      (eq_attr "mac" "cf_mac"))
+		 (eq_attr "type2" "mul_w"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+       (eq_attr "op_mem" "00"))
+  "cf_ib3+cfv123_mac_w_00")
+
+(define_insn_reservation "cfv12_mac_l_10_1" 7
+  (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		      (eq_attr "mac" "cf_mac"))
+		 (eq_attr "type2" "mul_l"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
+       (eq_attr "op_mem" "10"))
+  "cf_ib1+cfv12_mac_l_10")
+
+(define_insn_reservation "cfv12_mac_l_10_2" 7
+  (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		      (eq_attr "mac" "cf_mac"))
+		 (eq_attr "type2" "mul_l"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+       (eq_attr "op_mem" "10"))
+  "cf_ib2+cfv12_mac_l_10")
+
+(define_insn_reservation "cfv12_mac_l_10_3" 7
+  (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		      (eq_attr "mac" "cf_mac"))
+		 (eq_attr "type2" "mul_l"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+       (eq_attr "op_mem" "10"))
+  "cf_ib3+cfv12_mac_l_10")
 
-(define_insn_reservation "cf_v2_mul_10_1" 6
-  (and (and (and (eq_attr "cpu" "cf_v2")
-		 (eq_attr "type2" "mul"))
+(define_insn_reservation "cfv3_mac_l_10_1" 8
+  (and (and (and (and (eq_attr "cpu" "cfv3")
+		      (eq_attr "mac" "cf_mac"))
+		 (eq_attr "type2" "mul_l"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
        (eq_attr "op_mem" "10"))
-  "cf_v2_ib1+cf_v2_mul_10")
+  "cf_ib1+cfv3_mac_l_10")
 
-(define_insn_reservation "cf_v2_mul_10_2" 6
-  (and (and (and (eq_attr "cpu" "cf_v2")
-		 (eq_attr "type2" "mul"))
+(define_insn_reservation "cfv3_mac_l_10_2" 8
+  (and (and (and (and (eq_attr "cpu" "cfv3")
+		      (eq_attr "mac" "cf_mac"))
+		 (eq_attr "type2" "mul_l"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
        (eq_attr "op_mem" "10"))
-  "cf_v2_ib2+cf_v2_mul_10")
+  "cf_ib2+cfv3_mac_l_10")
 
-(define_insn_reservation "cf_v2_mul_10_3" 6
-  (and (and (and (eq_attr "cpu" "cf_v2")
-		 (eq_attr "type2" "mul"))
+(define_insn_reservation "cfv3_mac_l_10_3" 8
+  (and (and (and (and (eq_attr "cpu" "cfv3")
+		      (eq_attr "mac" "cf_mac"))
+		 (eq_attr "type2" "mul_l"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
        (eq_attr "op_mem" "10"))
-  "cf_v2_ib3+cf_v2_mul_10")
+  "cf_ib3+cfv3_mac_l_10")
+
+(define_insn_reservation "cfv12_mac_w_10_1" 5
+  (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		      (eq_attr "mac" "cf_mac"))
+		 (eq_attr "type2" "mul_w"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
+       (eq_attr "op_mem" "10"))
+  "cf_ib1+cfv12_mac_w_10")
 
-(define_insn_reservation "cf_v2_mul_i0_2" 7
-  (and (and (and (eq_attr "cpu" "cf_v2")
-		 (eq_attr "type2" "mul"))
+(define_insn_reservation "cfv12_mac_w_10_2" 5
+  (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		      (eq_attr "mac" "cf_mac"))
+		 (eq_attr "type2" "mul_w"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+       (eq_attr "op_mem" "10"))
+  "cf_ib2+cfv12_mac_w_10")
+
+(define_insn_reservation "cfv12_mac_w_10_3" 5
+  (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		      (eq_attr "mac" "cf_mac"))
+		 (eq_attr "type2" "mul_w"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+       (eq_attr "op_mem" "10"))
+  "cf_ib3+cfv12_mac_w_10")
+
+(define_insn_reservation "cfv3_mac_w_10_1" 6
+  (and (and (and (and (eq_attr "cpu" "cfv3")
+		      (eq_attr "mac" "cf_mac"))
+		 (eq_attr "type2" "mul_w"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
+       (eq_attr "op_mem" "10"))
+  "cf_ib1+cfv3_mac_w_10")
+
+(define_insn_reservation "cfv3_mac_w_10_2" 6
+  (and (and (and (and (eq_attr "cpu" "cfv3")
+		      (eq_attr "mac" "cf_mac"))
+		 (eq_attr "type2" "mul_w"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+       (eq_attr "op_mem" "10"))
+  "cf_ib2+cfv3_mac_w_10")
+
+(define_insn_reservation "cfv3_mac_w_10_3" 6
+  (and (and (and (and (eq_attr "cpu" "cfv3")
+		      (eq_attr "mac" "cf_mac"))
+		 (eq_attr "type2" "mul_w"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+       (eq_attr "op_mem" "10"))
+  "cf_ib3+cfv3_mac_w_10")
+
+(define_insn_reservation "cfv12_mac_w_i0_2" 6
+  (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		      (eq_attr "mac" "cf_mac"))
+		 (eq_attr "type2" "mul_w"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
        (eq_attr "op_mem" "i0"))
-  "cf_v2_ib2+cf_v2_mul_i0")
+  "cf_ib2+cfv12_mac_w_i0")
 
-(define_insn_reservation "cf_v2_mul_i0_3" 7
-  (and (and (and (eq_attr "cpu" "cf_v2")
-		 (eq_attr "type2" "mul"))
+(define_insn_reservation "cfv12_mac_w_i0_3" 6
+  (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		      (eq_attr "mac" "cf_mac"))
+		 (eq_attr "type2" "mul_w"))
 	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
        (eq_attr "op_mem" "i0"))
-  "cf_v2_ib3+cf_v2_mul_i0")
+  "cf_ib3+cfv12_mac_w_i0")
 
-;; ??? As return reads target address from stack, use a mem-read reservation
-;; for it.
-(define_reservation "cf_v2_rts" "cf_v2_move_10")
+(define_insn_reservation "cfv3_mac_w_i0_2" 7
+  (and (and (and (and (eq_attr "cpu" "cfv3")
+		      (eq_attr "mac" "cf_mac"))
+		 (eq_attr "type2" "mul_w"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+       (eq_attr "op_mem" "i0"))
+  "cf_ib2+cfv3_mac_w_i0")
 
-;; ??? It's not clear what the core does during these 5 cycles.
-;; Luckily, we don't care that much about an insn that won't be moved.
-(define_insn_reservation "cf_v2_rts_1" 5
-  (and (and (eq_attr "cpu" "cf_v2")
+(define_insn_reservation "cfv3_mac_w_i0_3" 7
+  (and (and (and (and (eq_attr "cpu" "cfv3")
+		      (eq_attr "mac" "cf_mac"))
+		 (eq_attr "type2" "mul_w"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+       (eq_attr "op_mem" "i0"))
+  "cf_ib3+cfv3_mac_w_i0")
+
+(define_insn_reservation "cfv123_emac_00_1" 4
+  (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
+		      (eq_attr "mac" "cf_emac"))
+		 (eq_attr "type2" "mul_l,mul_w"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
+       (eq_attr "op_mem" "00"))
+  "cf_ib1+cfv123_emac_00")
+
+(define_insn_reservation "cfv123_emac_00_2" 4
+  (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
+		      (eq_attr "mac" "cf_emac"))
+		 (eq_attr "type2" "mul_l,mul_w"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+       (eq_attr "op_mem" "00"))
+  "cf_ib2+cfv123_emac_00")
+
+(define_insn_reservation "cfv123_emac_00_3" 4
+  (and (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
+		      (eq_attr "mac" "cf_emac"))
+		 (eq_attr "type2" "mul_l,mul_w"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+       (eq_attr "op_mem" "00"))
+  "cf_ib3+cfv123_emac_00")
+
+(define_insn_reservation "cfv12_emac_10_1" 6
+  (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		      (eq_attr "mac" "cf_emac"))
+		 (eq_attr "type2" "mul_l,mul_w"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
+       (eq_attr "op_mem" "10"))
+  "cf_ib1+cfv12_emac_10")
+
+(define_insn_reservation "cfv12_emac_10_2" 6
+  (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		      (eq_attr "mac" "cf_emac"))
+		 (eq_attr "type2" "mul_l,mul_w"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+       (eq_attr "op_mem" "10"))
+  "cf_ib2+cfv12_emac_10")
+
+(define_insn_reservation "cfv12_emac_10_3" 6
+  (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		      (eq_attr "mac" "cf_emac"))
+		 (eq_attr "type2" "mul_l,mul_w"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+       (eq_attr "op_mem" "10"))
+  "cf_ib3+cfv12_emac_10")
+
+(define_insn_reservation "cfv3_emac_10_1" 7
+  (and (and (and (and (eq_attr "cpu" "cfv3")
+		      (eq_attr "mac" "cf_emac"))
+		 (eq_attr "type2" "mul_l,mul_w"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
+       (eq_attr "op_mem" "10"))
+  "cf_ib1+cfv3_emac_10")
+
+(define_insn_reservation "cfv3_emac_10_2" 7
+  (and (and (and (and (eq_attr "cpu" "cfv3")
+		      (eq_attr "mac" "cf_emac"))
+		 (eq_attr "type2" "mul_l,mul_w"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+       (eq_attr "op_mem" "10"))
+  "cf_ib2+cfv3_emac_10")
+
+(define_insn_reservation "cfv3_emac_10_3" 7
+  (and (and (and (and (eq_attr "cpu" "cfv3")
+		      (eq_attr "mac" "cf_emac"))
+		 (eq_attr "type2" "mul_l,mul_w"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+       (eq_attr "op_mem" "10"))
+  "cf_ib3+cfv3_emac_10")
+
+(define_insn_reservation "cfv12_emac_w_i0_2" 7
+  (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		      (eq_attr "mac" "cf_emac"))
+		 (eq_attr "type2" "mul_w"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+       (eq_attr "op_mem" "i0"))
+  "cf_ib2+cfv12_emac_w_i0")
+
+(define_insn_reservation "cfv12_emac_w_i0_3" 7
+  (and (and (and (and (eq_attr "cpu" "cfv1,cfv2")
+		      (eq_attr "mac" "cf_emac"))
+		 (eq_attr "type2" "mul_w"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+       (eq_attr "op_mem" "i0"))
+  "cf_ib3+cfv12_emac_w_i0")
+
+(define_insn_reservation "cfv3_emac_w_i0_2" 8
+  (and (and (and (and (eq_attr "cpu" "cfv3")
+		      (eq_attr "mac" "cf_emac"))
+		 (eq_attr "type2" "mul_w"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+       (eq_attr "op_mem" "i0"))
+  "cf_ib2+cfv3_emac_w_i0")
+
+(define_insn_reservation "cfv3_emac_w_i0_3" 8
+  (and (and (and (and (eq_attr "cpu" "cfv3")
+		      (eq_attr "mac" "cf_emac"))
+		 (eq_attr "type2" "mul_w"))
+	    (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+       (eq_attr "op_mem" "i0"))
+  "cf_ib3+cfv3_emac_w_i0")
+
+(define_insn_reservation "cfv12_rts_1" 5
+  (and (and (eq_attr "cpu" "cfv1,cfv2")
 	    (eq_attr "type2" "rts"))
        (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
-  "cf_v2_ib1+cf_v2_rts")
+  "cf_ib1+cfv12_rts")
 
-;; Call instructions reservations.
+(define_insn_reservation "cfv3_rts_1" 8
+  (and (and (eq_attr "cpu" "cfv3")
+	    (eq_attr "type2" "rts"))
+       (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
+  "cf_ib1+cfv3_rts")
 
-;; ??? It's not clear what reservation is best to use for calls.
-;; For now we use mem-write + return reservations to reflect the fact of
-;; pushing and poping return address to and from the stack.
+(define_insn_reservation "cfv12_call_1" 3
+  (and (and (eq_attr "cpu" "cfv1,cfv2")
+	    (eq_attr "type2" "call"))
+       (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
+  "cf_ib1+cfv12_call")
 
-(define_insn_reservation "cf_v2_call_1" 3
-  (and (and (eq_attr "cpu" "cf_v2")
+(define_insn_reservation "cfv12_call_2" 3
+  (and (and (eq_attr "cpu" "cfv1,cfv2")
+	    (eq_attr "type2" "call"))
+       (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+  "cf_ib2+cfv12_call")
+
+(define_insn_reservation "cfv12_call_3" 3
+  (and (and (eq_attr "cpu" "cfv1,cfv2")
+	    (eq_attr "type2" "call"))
+       (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+  "cf_ib3+cfv12_call")
+
+(define_insn_reservation "cfv3_call_1" 1
+  (and (and (eq_attr "cpu" "cfv3")
 	    (eq_attr "type2" "call"))
        (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
-  "cf_v2_ib1+cf_v2_move_10,cf_v2_rts")
+  "cf_ib1+cfv3_call")
 
-(define_insn_reservation "cf_v2_call_2" 3
-  (and (and (eq_attr "cpu" "cf_v2")
+(define_insn_reservation "cfv3_call_2" 1
+  (and (and (eq_attr "cpu" "cfv3")
 	    (eq_attr "type2" "call"))
        (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
-  "cf_v2_ib2+cf_v2_move_10,cf_v2_rts")
+  "cf_ib2+cfv3_call")
 
-(define_insn_reservation "cf_v2_call_3" 3
-  (and (and (eq_attr "cpu" "cf_v2")
+(define_insn_reservation "cfv3_call_3" 1
+  (and (and (eq_attr "cpu" "cfv3")
 	    (eq_attr "type2" "call"))
        (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
-  "cf_v2_ib3+cf_v2_move_10,cf_v2_rts")
+  "cf_ib3+cfv3_call")
 
-;; Branch reservations.
+(define_insn_reservation "cfv12_bcc_1" 2
+  (and (and (eq_attr "cpu" "cfv1,cfv2")
+	    (eq_attr "type2" "bcc"))
+       (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
+  "cf_ib1+cfv12_bcc")
 
-;; ??? Branch reservations are unclear to me so far.  Luckily, we don't care
-;; ??? that much about branches.
-(define_reservation "cf_v2_bcc" "cf_v2_move_00")
+(define_insn_reservation "cfv12_bcc_2" 2
+  (and (and (eq_attr "cpu" "cfv1,cfv2")
+	    (eq_attr "type2" "bcc"))
+       (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+  "cf_ib2+cfv12_bcc")
+
+(define_insn_reservation "cfv12_bcc_3" 2
+  (and (and (eq_attr "cpu" "cfv1,cfv2")
+	    (eq_attr "type2" "bcc"))
+       (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+  "cf_ib3+cfv12_bcc")
 
-(define_insn_reservation "cf_v2_bcc_1" 2
-  (and (and (eq_attr "cpu" "cf_v2")
+(define_insn_reservation "cfv3_bcc_1" 1
+  (and (and (eq_attr "cpu" "cfv3")
 	    (eq_attr "type2" "bcc"))
        (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
-  "cf_v2_ib1+cf_v2_bcc")
+  "cf_ib1+cfv3_bcc")
 
-(define_insn_reservation "cf_v2_bcc_2" 2
-  (and (and (eq_attr "cpu" "cf_v2")
+(define_insn_reservation "cfv3_bcc_2" 1
+  (and (and (eq_attr "cpu" "cfv3")
 	    (eq_attr "type2" "bcc"))
        (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
-  "cf_v2_ib2+cf_v2_bcc")
+  "cf_ib2+cfv3_bcc")
 
-(define_insn_reservation "cf_v2_bcc_3" 2
-  (and (and (eq_attr "cpu" "cf_v2")
+(define_insn_reservation "cfv3_bcc_3" 1
+  (and (and (eq_attr "cpu" "cfv3")
 	    (eq_attr "type2" "bcc"))
        (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
-  "cf_v2_ib3+cf_v2_bcc")
+  "cf_ib3+cfv3_bcc")
+
+(define_insn_reservation "cfv12_bra_1" 2
+  (and (and (eq_attr "cpu" "cfv1,cfv2")
+	    (eq_attr "type2" "bra"))
+       (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
+  "cf_ib1+cfv12_bra")
 
-(define_reservation "cf_v2_bra" "cf_v2_move_01")
+(define_insn_reservation "cfv12_bra_2" 2
+  (and (and (eq_attr "cpu" "cfv1,cfv2")
+	    (eq_attr "type2" "bra"))
+       (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+  "cf_ib2+cfv12_bra")
 
-(define_insn_reservation "cf_v2_bra_1" 2
-  (and (and (eq_attr "cpu" "cf_v2")
+(define_insn_reservation "cfv12_bra_3" 2
+  (and (and (eq_attr "cpu" "cfv1,cfv2")
+	    (eq_attr "type2" "bra"))
+       (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+  "cf_ib3+cfv12_bra")
+
+(define_insn_reservation "cfv3_bra_1" 1
+  (and (and (eq_attr "cpu" "cfv3")
 	    (eq_attr "type2" "bra"))
        (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
-  "cf_v2_ib1+cf_v2_bra")
+  "cf_ib1+cfv3_bra")
 
-(define_insn_reservation "cf_v2_bra_2" 2
-  (and (and (eq_attr "cpu" "cf_v2")
+(define_insn_reservation "cfv3_bra_2" 1
+  (and (and (eq_attr "cpu" "cfv3")
 	    (eq_attr "type2" "bra"))
        (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
-  "cf_v2_ib2+cf_v2_bra")
+  "cf_ib2+cfv3_bra")
 
-(define_insn_reservation "cf_v2_bra_3" 2
-  (and (and (eq_attr "cpu" "cf_v2")
+(define_insn_reservation "cfv3_bra_3" 1
+  (and (and (eq_attr "cpu" "cfv3")
 	    (eq_attr "type2" "bra"))
        (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
-  "cf_v2_ib3+cf_v2_bra")
+  "cf_ib3+cfv3_bra")
 
-;; Computed jump.
-;; Takes 3 cycles.
-(define_reservation "cf_v2_jmp"
-  "cf_v2_dsoc,cf_v2_agex,cf_v2_dsoc,cf_v2_agex")
+(define_insn_reservation "cfv12_jmp_1" 3
+  (and (and (eq_attr "cpu" "cfv1,cfv2")
+	    (eq_attr "type2" "jmp"))
+       (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
+  "cf_ib1+cfv12_jmp")
+
+(define_insn_reservation "cfv12_jmp_2" 3
+  (and (and (eq_attr "cpu" "cfv1,cfv2")
+	    (eq_attr "type2" "jmp"))
+       (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
+  "cf_ib2+cfv12_jmp")
+
+(define_insn_reservation "cfv12_jmp_3" 3
+  (and (and (eq_attr "cpu" "cfv1,cfv2")
+	    (eq_attr "type2" "jmp"))
+       (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
+  "cf_ib3+cfv12_jmp")
 
-(define_insn_reservation "cf_v2_jmp_1" 3
-  (and (and (eq_attr "cpu" "cf_v2")
+(define_insn_reservation "cfv3_jmp_1" 5
+  (and (and (eq_attr "cpu" "cfv3")
 	    (eq_attr "type2" "jmp"))
        (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
-  "cf_v2_ib1+cf_v2_jmp")
+  "cf_ib1+cfv3_jmp")
 
-(define_insn_reservation "cf_v2_jmp_2" 3
-  (and (and (eq_attr "cpu" "cf_v2")
+(define_insn_reservation "cfv3_jmp_2" 5
+  (and (and (eq_attr "cpu" "cfv3")
 	    (eq_attr "type2" "jmp"))
        (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
-  "cf_v2_ib2+cf_v2_jmp")
+  "cf_ib2+cfv3_jmp")
 
-(define_insn_reservation "cf_v2_jmp_3" 3
-  (and (and (eq_attr "cpu" "cf_v2")
+(define_insn_reservation "cfv3_jmp_3" 5
+  (and (and (eq_attr "cpu" "cfv3")
 	    (eq_attr "type2" "jmp"))
        (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
-  "cf_v2_ib3+cf_v2_jmp")
+  "cf_ib3+cfv3_jmp")
 
 ;; Misc reservations.
 
-(define_insn_reservation "cf_v2_unlk_1" 2
-  (and (and (eq_attr "cpu" "cf_v2")
+(define_insn_reservation "cfv12_unlk_1" 2
+  (and (and (eq_attr "cpu" "cfv1,cfv2")
+	    (eq_attr "type2" "unlk"))
+       (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
+  "cf_ib1+cfv12_alu_10")
+
+(define_insn_reservation "cfv3_unlk_1" 3
+  (and (and (eq_attr "cpu" "cfv3")
 	    (eq_attr "type2" "unlk"))
        (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
-  "cf_v2_ib1+cf_v2_move_l_10")
+  "cf_ib1+cfv3_alu_10")
 
 ;; This automaton is used to gather statistics on insns that need reservations.
-(define_automaton "cf_v2_guess")
+(define_automaton "cf_guess")
 
-(define_query_cpu_unit "cf_v2_guess" "cf_v2_guess")
+(define_query_cpu_unit "cf_guess" "cf_guess")
 
 ;; Dummy reservation for instructions that are not handled yet.
 
-(define_insn_reservation "cf_v2_guess_1" 1
-  (and (and (eq_attr "cpu" "cf_v2")
+(define_insn_reservation "cf_guess_1" 1
+  (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
 	    (eq_attr "guess" "yes"))
        (eq (symbol_ref "get_attr_size (insn)") (const_int 1)))
-  "cf_v2_ib1+cf_v2_guess+cf_v2_dsoc+cf_v2_agex")
+  "cf_ib1+cf_guess+cf_dsoc+cf_agex")
 
-(define_insn_reservation "cf_v2_guess_2" 1
-  (and (and (eq_attr "cpu" "cf_v2")
+(define_insn_reservation "cf_guess_2" 1
+  (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
 	    (eq_attr "guess" "yes"))
        (eq (symbol_ref "get_attr_size (insn)") (const_int 2)))
-  "cf_v2_ib2+cf_v2_guess+cf_v2_dsoc+cf_v2_agex")
+  "cf_ib2+cf_guess+cf_dsoc+cf_agex")
 
-(define_insn_reservation "cf_v2_guess_3" 1
-  (and (and (eq_attr "cpu" "cf_v2")
+(define_insn_reservation "cf_guess_3" 1
+  (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
 	    (eq_attr "guess" "yes"))
        (eq (symbol_ref "get_attr_size (insn)") (const_int 3)))
-  "cf_v2_ib3+cf_v2_guess+cf_v2_dsoc+cf_v2_agex")
+  "cf_ib3+cf_guess+cf_dsoc+cf_agex")
diff --git a/gcc/config/m68k/m68k-protos.h b/gcc/config/m68k/m68k-protos.h
index bd039077b7d..8948065668a 100644
--- a/gcc/config/m68k/m68k-protos.h
+++ b/gcc/config/m68k/m68k-protos.h
@@ -67,6 +67,7 @@ extern const char *m68k_output_movem (rtx *, rtx, HOST_WIDE_INT, bool);
 
 #ifdef HAVE_ATTR_cpu
 extern enum attr_cpu m68k_sched_cpu;
+extern enum attr_mac m68k_sched_mac;
 
 extern enum attr_opx_type m68k_sched_attr_opx_type (rtx, int);
 extern enum attr_opy_type m68k_sched_attr_opy_type (rtx, int);
diff --git a/gcc/config/m68k/m68k.c b/gcc/config/m68k/m68k.c
index 6160237ede6..0c38fbdfd19 100644
--- a/gcc/config/m68k/m68k.c
+++ b/gcc/config/m68k/m68k.c
@@ -666,8 +666,12 @@ override_options (void)
   SUBTARGET_OVERRIDE_OPTIONS;
 
   /* Setup scheduling options.  */
-  if (TUNE_CFV2)
-    m68k_sched_cpu = CPU_CF_V2;
+  if (TUNE_CFV1)
+    m68k_sched_cpu = CPU_CFV1;
+  else if (TUNE_CFV2)
+    m68k_sched_cpu = CPU_CFV2;
+  else if (TUNE_CFV3)
+    m68k_sched_cpu = CPU_CFV3;
   else
     {
       m68k_sched_cpu = CPU_UNKNOWN;
@@ -675,6 +679,16 @@ override_options (void)
       flag_schedule_insns_after_reload = 0;
       flag_modulo_sched = 0;
     }
+
+  if (m68k_sched_cpu != CPU_UNKNOWN)
+    {
+      if ((m68k_cpu_flags & (FL_CF_EMAC | FL_CF_EMAC_B)) != 0)
+	m68k_sched_mac = MAC_CF_EMAC;
+      else if ((m68k_cpu_flags & FL_CF_MAC) != 0)
+	m68k_sched_mac = MAC_CF_MAC;
+      else
+	m68k_sched_mac = MAC_NO;
+    }
 }
 
 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
@@ -4556,6 +4570,9 @@ m68k_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
 /* CPU to schedule the program for.  */
 enum attr_cpu m68k_sched_cpu;
 
+/* MAC to schedule the program for.  */
+enum attr_mac m68k_sched_mac;
+
 /* Operand type.  */
 enum attr_op_type
   {
@@ -5011,14 +5028,14 @@ m68k_sched_attr_type2 (rtx insn)
 {
   switch (get_attr_type1 (insn))
     {
-    case TYPE1_ALU_REG1:
-    case TYPE1_ALU_REGX:
-      return TYPE2_ALU;
-
     case TYPE1_ALU_L:
     case TYPE1_ALUQ_L:
     case TYPE1_CMP_L:
-      return TYPE2_ALU_L;
+      return TYPE2_ALU;
+
+    case TYPE1_ALU_REG1:
+    case TYPE1_ALU_REGX:
+      return TYPE2_ALU_REG;
 
     case TYPE1_BCC:
       return TYPE2_BCC;
@@ -5041,15 +5058,29 @@ m68k_sched_attr_type2 (rtx insn)
     case TYPE1_MOVE:
     case TYPE1_MOVEQ_L:
     case TYPE1_TST:
-      return TYPE2_MOVE;
+      switch (m68k_sched_cpu)
+	{
+	case CPU_CFV1:
+	  return TYPE2_OMOVE;
 
-    case TYPE1_MOVE_L:
-    case TYPE1_TST_L:
-      return TYPE2_MOVE_L;
+	case CPU_CFV2:
+	case CPU_CFV3:
+	  return TYPE2_ALU;
+
+	default:
+	  gcc_assert (get_attr_guess (insn) == GUESS_YES);
+	  return TYPE2_UNKNOWN;
+	}
 
-    case TYPE1_MUL_W:
     case TYPE1_MUL_L:
-      return TYPE2_MUL;
+      return TYPE2_MUL_L;
+
+    case TYPE1_MUL_W:
+      return TYPE2_MUL_W;
+
+    case TYPE1_MOVE_L:
+    case TYPE1_TST_L:
+      return TYPE2_OMOVE;
 
     case TYPE1_PEA:
       return TYPE2_PEA;
@@ -5095,14 +5126,39 @@ m68k_sched_adjust_cost (rtx insn, rtx link ATTRIBUTE_UNUSED, rtx def_insn,
   return cost;
 }
 
-/* Size of the instruction buffer in words.  */
-static int sched_ib_size;
+/* Maximal length of instruction for current CPU.
+   E.g. it is 3 for any ColdFire core.  */
+static int max_insn_size;
+
+/* Data to model instruction buffer of CPU.  */
+struct _sched_ib
+{
+  /* Size of the instruction buffer in words.  */
+  int size;
+
+  /* Number of filled words in the instruction buffer.  */
+  int filled;
+
+  /* Additional information about instruction buffer for CPUs that have
+     a buffer of instruction records, rather then a plain buffer
+     of instruction words.  */
+  struct _sched_ib_records
+  {
+    /* Size of buffer in records.  */
+    int n_insns;
 
-/* Number of filled words in the instruction buffer.  */
-static int sched_ib_filled;
+    /* Array to hold data on adjustements made to the size of the buffer.  */
+    int *adjust;
 
-/* An insn that reserves (marks empty) one word in the instruction buffer.  */
-static rtx sched_ib_insn;
+    /* Index of the above array.  */
+    int adjust_index;
+  } records;
+
+  /* An insn that reserves (marks empty) one word in the instruction buffer.  */
+  rtx insn;
+};
+
+static struct _sched_ib sched_ib;
 
 /* ID of memory unit.  */
 static int sched_mem_unit_code;
@@ -5121,19 +5177,58 @@ m68k_sched_variable_issue (FILE *sched_dump ATTRIBUTE_UNUSED,
 
   if (recog_memoized (insn) >= 0)
     {
-      insn_size = get_attr_size (insn);
+      switch (m68k_sched_cpu)
+	{
+	case CPU_CFV1:
+	case CPU_CFV2:
+	  insn_size = get_attr_size (insn);
+	  break;
+
+	case CPU_CFV3:
+	  insn_size = get_attr_size (insn);
+	  
+	  /* ColdFire V3 and V4 cores have instruction buffers that can
+	     accumulate up to 8 instructions regardless of instructions'
+	     sizes.  So we should take care not to "prefetch" 24 one-word
+	     or 12 two-words instructions.
+	     To model this behavior we temporarily decrease size of the
+	     buffer by (max_insn_size - insn_size) for next 7 instructions.  */
+	  {
+	    int adjust;
+
+	    adjust = max_insn_size - insn_size;
+	    sched_ib.size -= adjust;
+
+	    if (sched_ib.filled > sched_ib.size)
+	      sched_ib.filled = sched_ib.size;
+
+	    sched_ib.records.adjust[sched_ib.records.adjust_index] = adjust;
+	  }
+
+	  ++sched_ib.records.adjust_index;
+	  if (sched_ib.records.adjust_index == sched_ib.records.n_insns)
+	    sched_ib.records.adjust_index = 0;
+
+	  /* Undo adjustement we did 7 instructions ago.  */
+	  sched_ib.size
+	    += sched_ib.records.adjust[sched_ib.records.adjust_index];
+
+	  break;
 
-      gcc_assert (insn_size <= sched_ib_filled);
+	default:
+	  gcc_unreachable ();
+	}
 
+      gcc_assert (insn_size <= sched_ib.filled);
       --can_issue_more;
     }
   else if (GET_CODE (PATTERN (insn)) == ASM_INPUT
 	   || asm_noperands (PATTERN (insn)) >= 0)
-    insn_size = sched_ib_filled;
+    insn_size = sched_ib.filled;
   else
     insn_size = 0;
 
-  sched_ib_filled -= insn_size;
+  sched_ib.filled -= insn_size;
 
   return can_issue_more;
 }
@@ -5357,7 +5452,7 @@ m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED,
       m68k_sched_dump (sched_dump_split_class, "m68k_sched_split",
 		       sched_dump);
 
-      sched_dump_dfa_guess_unit_code = get_cpu_unit_code ("cf_v2_guess");
+      sched_dump_dfa_guess_unit_code = get_cpu_unit_code ("cf_guess");
       sched_dump_dfa_state = alloca (state_size ());
 
       m68k_sched_dump (sched_dump_dfa_class, "m68k_sched_dfa",
@@ -5370,21 +5465,32 @@ m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED,
   /* Setup target cpu.  */
   switch (m68k_sched_cpu)
     {
-    case CPU_CF_V2:
-      sched_ib_size = 6;
-      sched_mem_unit_code = get_cpu_unit_code ("cf_v2_mem");
+    case CPU_CFV1:
+    case CPU_CFV2:
+      max_insn_size = 3;
+      sched_ib.records.n_insns = 0;
+      sched_ib.records.adjust = NULL;
+      break;
+
+    case CPU_CFV3:
+      max_insn_size = 3;
+      sched_ib.records.n_insns = 8;
+      sched_ib.records.adjust = xmalloc (sched_ib.records.n_insns
+					 * sizeof (*sched_ib.records.adjust));
       break;
 
     default:
       gcc_unreachable ();
     }
 
+  sched_mem_unit_code = get_cpu_unit_code ("cf_mem1");
+
   sched_adjust_cost_state = xmalloc (state_size ());
   state_reset (sched_adjust_cost_state);
 
   start_sequence ();
   emit_insn (gen_ib ());
-  sched_ib_insn = get_insns ();
+  sched_ib.insn = get_insns ();
   end_sequence ();
 }
 
@@ -5393,13 +5499,17 @@ static void
 m68k_sched_md_finish_global (FILE *dump ATTRIBUTE_UNUSED,
 			     int verbose ATTRIBUTE_UNUSED)
 {
-  sched_ib_insn = NULL;
+  sched_ib.insn = NULL;
 
   free (sched_adjust_cost_state);
   sched_adjust_cost_state = NULL;
 
   sched_mem_unit_code = 0;
-  sched_ib_size = 0;
+
+  free (sched_ib.records.adjust);
+  sched_ib.records.adjust = NULL;
+  sched_ib.records.n_insns = 0;
+  max_insn_size = 0;
 
   free (sched_branch_type);
   sched_branch_type = NULL;
@@ -5413,9 +5523,28 @@ m68k_sched_md_init (FILE *sched_dump ATTRIBUTE_UNUSED,
 		    int sched_verbose ATTRIBUTE_UNUSED,
 		    int n_insns ATTRIBUTE_UNUSED)
 {
+  switch (m68k_sched_cpu)
+    {
+    case CPU_CFV1:
+    case CPU_CFV2:
+      sched_ib.size = 6;
+      break;
+
+    case CPU_CFV3:
+      sched_ib.size = sched_ib.records.n_insns * max_insn_size;
+
+      memset (sched_ib.records.adjust, 0,
+	      sched_ib.records.n_insns * sizeof (*sched_ib.records.adjust));
+      sched_ib.records.adjust_index = 0;
+      break;
+
+    default:
+      gcc_unreachable ();
+    }
+
   /* haifa-sched.c: schedule_block () calls advance_cycle () just before
      the first cycle.  Workaround that.  */
-  sched_ib_filled = -2;
+  sched_ib.filled = -2;
 }
 
 /* Implementation of targetm.sched.dfa_pre_advance_cycle () hook.
@@ -5426,10 +5555,10 @@ m68k_sched_dfa_pre_advance_cycle (void)
 {
   if (!cpu_unit_reservation_p (curr_state, sched_mem_unit_code))
     {
-      sched_ib_filled += 2;
+      sched_ib.filled += 2;
 
-      if (sched_ib_filled > sched_ib_size)
-	sched_ib_filled = sched_ib_size;
+      if (sched_ib.filled > sched_ib.size)
+	sched_ib.filled = sched_ib.size;
     }
 }
 
@@ -5442,13 +5571,14 @@ static void
 m68k_sched_dfa_post_advance_cycle (void)
 {
   int i;
-  int n;
 
   /* Setup number of prefetched instruction words in the instruction
      buffer.  */
-  for (i = sched_ib_filled, n = sched_ib_size; i < n; ++i)
+  i = max_insn_size - sched_ib.filled;
+
+  while (--i >= 0)
     {
-      if (state_transition (curr_state, sched_ib_insn) >= 0)
+      if (state_transition (curr_state, sched_ib.insn) >= 0)
 	gcc_unreachable ();
     }
 }
diff --git a/gcc/config/m68k/m68k.h b/gcc/config/m68k/m68k.h
index d5d89832643..32b5c243999 100644
--- a/gcc/config/m68k/m68k.h
+++ b/gcc/config/m68k/m68k.h
@@ -266,6 +266,7 @@ along with GCC; see the file COPYING3.  If not see
 #define TUNE_CPU32	(m68k_tune == ucpu32)
 #define TUNE_CFV1       (m68k_tune == ucfv1)
 #define TUNE_CFV2	(m68k_tune == ucfv2)
+#define TUNE_CFV3       (m68k_tune == ucfv3)
 
 #define OVERRIDE_OPTIONS   override_options()
 
diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
index 523b039acd0..abe363ee285 100644
--- a/gcc/config/m68k/m68k.md
+++ b/gcc/config/m68k/m68k.md
@@ -144,7 +144,12 @@
 ;; ::::::::::::::::::::
 
 ;; Processor type.
-(define_attr "cpu" "cf_v2, unknown" (const (symbol_ref "m68k_sched_cpu")))
+(define_attr "cpu" "cfv1, cfv2, cfv3, unknown"
+  (const (symbol_ref "m68k_sched_cpu")))
+
+;; MAC type.
+(define_attr "mac" "no, cf_mac, cf_emac"
+  (const (symbol_ref "m68k_sched_mac")))
 
 ;; Instruction type.
 ;; Basically, an asm pattern.