diff options
author | Aldy Hernandez <aldyh@redhat.com> | 2004-07-15 21:02:15 +0000 |
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committer | Aldy Hernandez <aldyh@gcc.gnu.org> | 2004-07-15 21:02:15 +0000 |
commit | 24fab1d3dbaafe4a08db0990399feae3ddc0a44f (patch) | |
tree | 86d37bc99191f1d96250044d0f9ff9bf3f290a16 | |
parent | 523456dbde953a6f2dac504b2fd2ff1ddc8ec03d (diff) | |
download | gcc-24fab1d3dbaafe4a08db0990399feae3ddc0a44f.tar.gz |
rs6000.md ("*cceq_ior_compare"): Allow unconditionally.
* config/rs6000/rs6000.md ("*cceq_ior_compare"): Allow
unconditionally.
* config/rs6000/spe.md ("e500_cceq_ior_compare"): Remove.
From-SVN: r84775
-rw-r--r-- | gcc/ChangeLog | 6 | ||||
-rw-r--r-- | gcc/config/rs6000/rs6000.md | 2 | ||||
-rw-r--r-- | gcc/config/rs6000/spe.md | 18 |
3 files changed, 7 insertions, 19 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c19e9963dc5..e9e5235807d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2004-07-15 Aldy Hernandez <aldyh@redhat.com> + + * config/rs6000/rs6000.md ("*cceq_ior_compare"): Allow + unconditionally. + * config/rs6000/spe.md ("e500_cceq_ior_compare"): Remove. + 2004-07-15 Richard Sandiford <rsandifo@redhat.com> * config/mips/mips.c (mips_adjust_insn_length): Fix handling of diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 2874e6d2a0e..432ceff7019 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -13748,7 +13748,7 @@ "cc_reg_operand" "0,y") (const_int 0)])]) (const_int 1)))] - "!(TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS)" + "" "cr%q1 %E0,%j2,%j4" [(set_attr "type" "cr_logical,delayed_cr")]) diff --git a/gcc/config/rs6000/spe.md b/gcc/config/rs6000/spe.md index 4b311c70fee..06eeb314f80 100644 --- a/gcc/config/rs6000/spe.md +++ b/gcc/config/rs6000/spe.md @@ -2457,24 +2457,6 @@ ;; FP comparison stuff. -(define_insn "e500_cceq_ior_compare" - [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y") - (compare:CCEQ (match_operator:SI 1 "boolean_operator" - [(match_operator:SI 2 - "branch_positive_comparison_operator" - [(match_operand 3 - "cc_reg_operand" "y,y") - (const_int 0)]) - (match_operator:SI 4 - "branch_positive_comparison_operator" - [(match_operand 5 - "cc_reg_operand" "0,y") - (const_int 0)])]) - (const_int 1)))] - "TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS" - "cr%q1 %c0,%j2,%j4" - [(set_attr "type" "cr_logical,delayed_cr")]) - ;; Flip the GT bit. (define_insn "e500_flip_gt_bit" [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") |