* config/mips/mips.md: Remove mips16 define_peepholes.

From-SVN: r84803

2 files changed, 4 insertions, 115 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index b58678f1615..ae093686d96 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2004-07-16  Richard Sandiford  <rsandifo@redhat.com>
+
+	* config/mips/mips.md: Remove mips16 define_peepholes.
+
 2004-07-16  Daniel Berlin  <dberlin@dberlin.org>
 
 	* tree-ssa-pre.c (init_pre): Connect infinite loops to exit.
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 79d90609738..b94c759e94c 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -7634,121 +7634,6 @@ dsrl\t%3,%3,1\n\
   ".align\t%0"
   [(set (attr "length") (symbol_ref "(1 << INTVAL (operands[0])) - 1"))])
 
-;;
-;;  ....................
-;;
-;;	mips16 peepholes
-;;
-;;  ....................
-;;
-
-;; On the mips16, reload will sometimes decide that a pseudo register
-;; should go into $24, and then later on have to reload that register.
-;; When that happens, we get a load of a general register followed by
-;; a move from the general register to $24 followed by a branch.
-;; These peepholes catch the common case, and fix it to just use the
-;; general register for the branch.
-
-(define_peephole
-  [(set (match_operand:SI 0 "register_operand" "=t")
-	(match_operand:SI 1 "register_operand" "d"))
-   (set (pc)
-	(if_then_else (match_operator:SI 2 "equality_op" [(match_dup 0)
-							  (const_int 0)])
-		      (match_operand 3 "pc_or_label_operand" "")
-		      (match_operand 4 "pc_or_label_operand" "")))]
-  "TARGET_MIPS16
-   && GET_CODE (operands[0]) == REG
-   && REGNO (operands[0]) == 24
-   && dead_or_set_p (insn, operands[0])
-   && GET_CODE (operands[1]) == REG
-   && M16_REG_P (REGNO (operands[1]))"
-{
-  if (operands[3] != pc_rtx)
-    return "b%C2z\t%1,%3";
-  else
-    return "b%N2z\t%1,%4";
-}
-  [(set_attr "type"	"branch")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"8")])
-
-(define_peephole
-  [(set (match_operand:DI 0 "register_operand" "=t")
-	(match_operand:DI 1 "register_operand" "d"))
-   (set (pc)
-	(if_then_else (match_operator:DI 2 "equality_op" [(match_dup 0)
-							  (const_int 0)])
-		      (match_operand 3 "pc_or_label_operand" "")
-		      (match_operand 4 "pc_or_label_operand" "")))]
-  "TARGET_MIPS16 && TARGET_64BIT
-   && GET_CODE (operands[0]) == REG
-   && REGNO (operands[0]) == 24
-   && dead_or_set_p (insn, operands[0])
-   && GET_CODE (operands[1]) == REG
-   && M16_REG_P (REGNO (operands[1]))"
-{
-  if (operands[3] != pc_rtx)
-    return "b%C2z\t%1,%3";
-  else
-    return "b%N2z\t%1,%4";
-}
-  [(set_attr "type"	"branch")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"8")])
-
-;; We can also have the reverse reload: reload will spill $24 into
-;; another register, and then do a branch on that register when it
-;; could have just stuck with $24.
-
-(define_peephole
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(match_operand:SI 1 "register_operand" "t"))
-   (set (pc)
-	(if_then_else (match_operator:SI 2 "equality_op" [(match_dup 0)
-							  (const_int 0)])
-		      (match_operand 3 "pc_or_label_operand" "")
-		      (match_operand 4 "pc_or_label_operand" "")))]
-  "TARGET_MIPS16
-   && GET_CODE (operands[1]) == REG
-   && REGNO (operands[1]) == 24
-   && GET_CODE (operands[0]) == REG
-   && M16_REG_P (REGNO (operands[0]))
-   && dead_or_set_p (insn, operands[0])"
-{
-  if (operands[3] != pc_rtx)
-    return "bt%C2z\t%3";
-  else
-    return "bt%N2z\t%4";
-}
-  [(set_attr "type"	"branch")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"8")])
-
-(define_peephole
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(match_operand:DI 1 "register_operand" "t"))
-   (set (pc)
-	(if_then_else (match_operator:DI 2 "equality_op" [(match_dup 0)
-							  (const_int 0)])
-		      (match_operand 3 "pc_or_label_operand" "")
-		      (match_operand 4 "pc_or_label_operand" "")))]
-  "TARGET_MIPS16 && TARGET_64BIT
-   && GET_CODE (operands[1]) == REG
-   && REGNO (operands[1]) == 24
-   && GET_CODE (operands[0]) == REG
-   && M16_REG_P (REGNO (operands[0]))
-   && dead_or_set_p (insn, operands[0])"
-{
-  if (operands[3] != pc_rtx)
-    return "bt%C2z\t%3";
-  else
-    return "bt%N2z\t%4";
-}
-  [(set_attr "type"	"branch")
-   (set_attr "mode"	"none")
-   (set_attr "length"	"8")])
-
 (define_split
   [(match_operand 0 "small_data_pattern")]
   "reload_completed"