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| author | Nick Clifton <nickc@gcc.gnu.org> | 2015-05-19 11:42:44 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@gcc.gnu.org> | 2015-05-19 11:42:44 +0000 |
| commit | bdafd67926619844219607d658d0632d0eda313c (patch) | |
| tree | 9c51835e4e81bf31d6a6e086b9de18e3c97d4fe7 | |
| parent | 057c74c7c5e43dc6fe23545051f77ff1da4116db (diff) | |
| download | gcc-bdafd67926619844219607d658d0632d0eda313c.tar.gz | |
re PR rtl-optimization/66156 ([msp430] wrong code generated with -O2 -mlarge (zero extension HI -> SI))
PR target/66156
* config/msp430/msp430.md (zero_extendhisi2): Add support for
separate source and destination registers.
From-SVN: r223354
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/msp430/msp430.md | 8 |
2 files changed, 12 insertions, 4 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ed64b470784..2f90beaa2a9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2015-05-19 Nick Clifton <nickc@redhat.com> + + PR target/66156 + * config/msp430/msp430.md (zero_extendhisi2): Add support for + separate source and destination registers. + 2015-05-19 Richard Biener <rguenther@suse.de> PR tree-optimization/66165 @@ -32,7 +38,7 @@ * calls.c: Always define STACK_GROWS_DOWNWARD as 0 or 1. (mem_overlaps_already_clobbered_arg_p): Rewrite ifdef STACK_GROWS_DOWNWARD as normal if. - (expand_call): Likewise. + (expand_call): Likewise. 2015-05-19 Oleg Endo <olegendo@gcc.gnu.org> diff --git a/gcc/config/msp430/msp430.md b/gcc/config/msp430/msp430.md index 91742fc38b5..64fdc459b78 100644 --- a/gcc/config/msp430/msp430.md +++ b/gcc/config/msp430/msp430.md @@ -588,10 +588,12 @@ ;; patterns. Doing these manually allows for alternate optimization ;; paths. (define_insn "zero_extendhisi2" - [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") - (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0")))] + [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r") + (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0,r")))] "msp430x" - "MOV.W\t#0,%H0" + "@ + MOV.W\t#0,%H0 + MOV.W\t%1,%L0 { MOV.W\t#0,%H0" ) (define_insn "zero_extendhisipsi2" |