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| author | ktkachov <ktkachov@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-10-18 17:20:49 +0000 |
|---|---|---|
| committer | ktkachov <ktkachov@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-10-18 17:20:49 +0000 |
| commit | f2f653da531b4042f9dcc183ae94cee4469fbf3e (patch) | |
| tree | 8513345c906c7545fa3b749fe623c63802b0a4f8 | |
| parent | 63ffcb80a66eefad1b7d4f44e5229be8af008467 (diff) | |
| download | gcc-f2f653da531b4042f9dcc183ae94cee4469fbf3e.tar.gz | |
[gcc/]
2013-10-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm.c (cortexa9_extra_costs): New table.
(arm_cortex_a9_tune): Use cortexa9_extra_costs.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@203828 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/arm/arm.c | 104 |
2 files changed, 108 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e18ad6f70c8..4249ae29fe7 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2013-10-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + * config/arm/arm.c (cortexa9_extra_costs): New table. + (arm_cortex_a9_tune): Use cortexa9_extra_costs. + 2013-10-18 Jeff Law <law@redhat.com> * tree-ssa-threadupdate.c: Do not include "tm.h" or "tm_p.h". diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 4cdac60fd8a..f4ce58bc935 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -1050,6 +1050,108 @@ const struct cpu_cost_table generic_extra_costs = } }; + +const struct cpu_cost_table cortexa9_extra_costs = +{ + /* ALU */ + { + 0, /* Arith. */ + 0, /* Logical. */ + 0, /* Shift. */ + COSTS_N_INSNS (1), /* Shift_reg. */ + COSTS_N_INSNS (1), /* Arith_shift. */ + COSTS_N_INSNS (2), /* Arith_shift_reg. */ + 0, /* Log_shift. */ + COSTS_N_INSNS (1), /* Log_shift_reg. */ + COSTS_N_INSNS (1), /* Extend. */ + COSTS_N_INSNS (2), /* Extend_arith. */ + COSTS_N_INSNS (1), /* Bfi. */ + COSTS_N_INSNS (1), /* Bfx. */ + 0, /* Clz. */ + 0, /* non_exec. */ + true /* non_exec_costs_exec. */ + }, + { + /* MULT SImode */ + { + COSTS_N_INSNS (3), /* Simple. */ + COSTS_N_INSNS (3), /* Flag_setting. */ + COSTS_N_INSNS (4), /* Extend. */ + COSTS_N_INSNS (3), /* Add. */ + COSTS_N_INSNS (4), /* Extend_add. */ + COSTS_N_INSNS (30) /* Idiv. No HW div on Cortex A9. */ + }, + /* MULT DImode */ + { + 0, /* Simple (N/A). */ + 0, /* Flag_setting (N/A). */ + 0, /* Extend (N/A). */ + 0, /* Add (N/A). */ + 0, /* Extend_add (N/A). */ + 0 /* Idiv (N/A). */ + } + }, + /* LD/ST */ + { + COSTS_N_INSNS (2), /* Load. */ + COSTS_N_INSNS (2), /* Load_sign_extend. */ + COSTS_N_INSNS (2), /* Ldrd. */ + COSTS_N_INSNS (2), /* Ldm_1st. */ + 1, /* Ldm_regs_per_insn_1st. */ + 2, /* Ldm_regs_per_insn_subsequent. */ + COSTS_N_INSNS (5), /* Loadf. */ + COSTS_N_INSNS (5), /* Loadd. */ + COSTS_N_INSNS (1), /* Load_unaligned. */ + COSTS_N_INSNS (2), /* Store. */ + COSTS_N_INSNS (2), /* Strd. */ + COSTS_N_INSNS (2), /* Stm_1st. */ + 1, /* Stm_regs_per_insn_1st. */ + 2, /* Stm_regs_per_insn_subsequent. */ + COSTS_N_INSNS (1), /* Storef. */ + COSTS_N_INSNS (1), /* Stored. */ + COSTS_N_INSNS (1) /* Store_unaligned. */ + }, + { + /* FP SFmode */ + { + COSTS_N_INSNS (14), /* Div. */ + COSTS_N_INSNS (4), /* Mult. */ + COSTS_N_INSNS (7), /* Mult_addsub. */ + COSTS_N_INSNS (30), /* Fma. */ + COSTS_N_INSNS (3), /* Addsub. */ + COSTS_N_INSNS (1), /* Fpconst. */ + COSTS_N_INSNS (1), /* Neg. */ + COSTS_N_INSNS (3), /* Compare. */ + COSTS_N_INSNS (3), /* Widen. */ + COSTS_N_INSNS (3), /* Narrow. */ + COSTS_N_INSNS (3), /* Toint. */ + COSTS_N_INSNS (3), /* Fromint. */ + COSTS_N_INSNS (3) /* Roundint. */ + }, + /* FP DFmode */ + { + COSTS_N_INSNS (24), /* Div. */ + COSTS_N_INSNS (5), /* Mult. */ + COSTS_N_INSNS (8), /* Mult_addsub. */ + COSTS_N_INSNS (30), /* Fma. */ + COSTS_N_INSNS (3), /* Addsub. */ + COSTS_N_INSNS (1), /* Fpconst. */ + COSTS_N_INSNS (1), /* Neg. */ + COSTS_N_INSNS (3), /* Compare. */ + COSTS_N_INSNS (3), /* Widen. */ + COSTS_N_INSNS (3), /* Narrow. */ + COSTS_N_INSNS (3), /* Toint. */ + COSTS_N_INSNS (3), /* Fromint. */ + COSTS_N_INSNS (3) /* Roundint. */ + } + }, + /* Vector */ + { + COSTS_N_INSNS (1) /* Alu. */ + } +}; + + const struct cpu_cost_table cortexa15_extra_costs = { /* ALU */ @@ -1304,7 +1406,7 @@ const struct tune_params arm_cortex_a5_tune = const struct tune_params arm_cortex_a9_tune = { arm_9e_rtx_costs, - NULL, + &cortexa9_extra_costs, cortex_a9_sched_adjust_cost, 1, /* Constant limit. */ 5, /* Max cond insns. */ |