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| author | rth <rth@138bc75d-0d04-0410-961f-82ee72b054a4> | 1997-10-28 23:29:44 +0000 |
|---|---|---|
| committer | rth <rth@138bc75d-0d04-0410-961f-82ee72b054a4> | 1997-10-28 23:29:44 +0000 |
| commit | 7aaa8f0fc1291f1ba0bcf794ec1fb1c154a18b6f (patch) | |
| tree | 73c9c463b8512da99cd76360abc5002a3aca5a2e | |
| parent | a0bebd859d32d30fc5e6686e90aea2cf215cc090 (diff) | |
| download | gcc-7aaa8f0fc1291f1ba0bcf794ec1fb1c154a18b6f.tar.gz | |
* reload1.c (eliminate_regs [SET]): If [SUBREG] widened the mode of
DEST for the spill, adjust mode of SRC to compensate.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@16222 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/reload1.c | 6 |
2 files changed, 11 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f6a96bdac10..39a753d0f16 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +Tue Oct 28 15:29:15 1997 Richard Henderson <rth@cygnus.com> + + * reload1.c (eliminate_regs [SET]): If [SUBREG] widened the mode of + DEST for the spill, adjust mode of SRC to compensate. + Tue Oct 28 14:36:45 1997 Richard Henderson <rth@cygnus.com> * alpha.md (reload_inqi): Check for MEM before strict_memory_address_p, diff --git a/gcc/reload1.c b/gcc/reload1.c index a3361abbfad..cbb41308ddb 100644 --- a/gcc/reload1.c +++ b/gcc/reload1.c @@ -3271,6 +3271,12 @@ eliminate_regs (x, mem_mode, insn, storing) && GET_CODE (insn) != INSN_LIST) emit_insn_after (gen_rtx (CLOBBER, VOIDmode, SET_DEST (x)), insn); + /* If SET_DEST was a partial-word subreg, NEW0 may have been widened + to spill the entire register (see SUBREG case above). If the + widths of SET_DEST and NEW0 no longer match, adjust NEW1. */ + if (GET_MODE (SET_DEST (x)) != GET_MODE (new0)) + new1 = gen_rtx (SUBREG, GET_MODE (new0), new1, 0); + if (new0 != SET_DEST (x) || new1 != SET_SRC (x)) return gen_rtx (SET, VOIDmode, new0, new1); } |