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authorhjl <hjl@138bc75d-0d04-0410-961f-82ee72b054a4>2008-02-18 23:44:32 +0000
committerhjl <hjl@138bc75d-0d04-0410-961f-82ee72b054a4>2008-02-18 23:44:32 +0000
commitdbbcdcd5bfbe0caeb29cbd98af1d0db78f129541 (patch)
tree5cb219bb7772e80032acadfde74f63a9148f848d
parentbeebc64a4e93e7006a311696b6373873598f080b (diff)
downloadgcc-dbbcdcd5bfbe0caeb29cbd98af1d0db78f129541.tar.gz
2008-02-18 H.J. Lu <hongjiu.lu@intel.com>
* config/i386/i386-modes.def: Use 4 byte alignment on DI for 32bit host. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@132397 138bc75d-0d04-0410-961f-82ee72b054a4
-rw-r--r--gcc/ChangeLog5
-rw-r--r--gcc/config/i386/i386-modes.def4
2 files changed, 9 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3ecc40c8132..733d076d7e8 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2008-02-18 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/i386/i386-modes.def: Use 4 byte alignment on DI for
+ 32bit host.
+
2008-02-18 Joey Ye <joey.ye@intel.com>
PR middle-end/34921
diff --git a/gcc/config/i386/i386-modes.def b/gcc/config/i386/i386-modes.def
index 105d3872b79..f2f2b4f2acb 100644
--- a/gcc/config/i386/i386-modes.def
+++ b/gcc/config/i386/i386-modes.def
@@ -17,6 +17,10 @@ You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
+/* In 32bit, DI mode uses 32bit registers. Only 4 byte alignment
+ is needed. */
+ADJUST_ALIGNMENT (DI, (TARGET_64BIT || TARGET_ALIGN_DOUBLE) ? 8 : 4);
+
/* The x86_64 ABI specifies both XF and TF modes.
XFmode is __float80 is IEEE extended; TFmode is __float128
is IEEE quad. */