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authorabennett <abennett@138bc75d-0d04-0410-961f-82ee72b054a4>2016-01-29 13:54:53 +0000
committerabennett <abennett@138bc75d-0d04-0410-961f-82ee72b054a4>2016-01-29 13:54:53 +0000
commite3078da666c94026d17cc608f062a220b8eb9ccd (patch)
tree1e764f4d0f16e221cd5c795f4ce6e2de9c57d398
parent38920dbb87fe807ad449112cee84484aada3c394 (diff)
downloadgcc-e3078da666c94026d17cc608f062a220b8eb9ccd.tar.gz
testsuite/
2016-01-29 Andrew Bennett <andrew.bennett@imgtec.com> * gcc.target/mips/p5600-bonding.c (dg-options): Force the test to be always built for p5600. * gcc.target/mips/mips.exp (mips-dg-options): Add support for the isa=p5600 dg-option. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@232980 138bc75d-0d04-0410-961f-82ee72b054a4
-rw-r--r--gcc/testsuite/ChangeLog7
-rw-r--r--gcc/testsuite/gcc.target/mips/mips.exp7
-rw-r--r--gcc/testsuite/gcc.target/mips/p5600-bonding.c2
3 files changed, 15 insertions, 1 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 6b2ddbd961b..6a279eba98f 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2016-01-29 Andrew Bennett <andrew.bennett@imgtec.com>
+
+ * gcc.target/mips/p5600-bonding.c (dg-options): Force the test to be
+ always built for p5600.
+ * gcc.target/mips/mips.exp (mips-dg-options): Add support for the
+ isa=p5600 dg-option.
+
2016-01-29 Richard Biener <rguenther@suse.de>
PR tree-optimization/69547
diff --git a/gcc/testsuite/gcc.target/mips/mips.exp b/gcc/testsuite/gcc.target/mips/mips.exp
index ff9c99a8409..32581058ff1 100644
--- a/gcc/testsuite/gcc.target/mips/mips.exp
+++ b/gcc/testsuite/gcc.target/mips/mips.exp
@@ -142,6 +142,9 @@
# isa=loongson
# select a Loongson processor
#
+# isa=p5600
+# select a P5600 processor
+#
# addressing=absolute
# force absolute addresses to be used
#
@@ -1011,6 +1014,10 @@ proc mips-dg-options { args } {
if { ![regexp {^-march=loongson} $arch] } {
set arch "-march=loongson2f"
}
+ } elseif { [string equal $spec "isa=p5600"] } {
+ if { ![regexp {^-march=p5600} $arch] } {
+ set arch "-march=p5600"
+ }
} else {
if { ![regexp {^(isa(?:|_rev))(=|<=|>=)([0-9]*)$} \
$spec dummy prop relation value nocpus] } {
diff --git a/gcc/testsuite/gcc.target/mips/p5600-bonding.c b/gcc/testsuite/gcc.target/mips/p5600-bonding.c
index 0890ffa9215..0bc6d91ef1e 100644
--- a/gcc/testsuite/gcc.target/mips/p5600-bonding.c
+++ b/gcc/testsuite/gcc.target/mips/p5600-bonding.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-dp -mtune=p5600 -mno-micromips -mno-mips16" } */
+/* { dg-options "-dp isa=p5600 -mtune=p5600 -mno-micromips -mno-mips16" } */
/* { dg-skip-if "Bonding needs peephole optimization." { *-*-* } { "-O0" "-O1" } { "" } } */
typedef int VINT32 __attribute__ ((vector_size((16))));