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| author | dje <dje@138bc75d-0d04-0410-961f-82ee72b054a4> | 2004-01-30 20:47:32 +0000 |
|---|---|---|
| committer | dje <dje@138bc75d-0d04-0410-961f-82ee72b054a4> | 2004-01-30 20:47:32 +0000 |
| commit | 341c819295ed3709f62d7ca83b7bca6594579f93 (patch) | |
| tree | 71c58ea0d7c1399c37742df59600ad953f8e6889 | |
| parent | 88b8887c834287197a41674003609578de4999be (diff) | |
| download | gcc-341c819295ed3709f62d7ca83b7bca6594579f93.tar.gz | |
Fix whitespace.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@76990 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/config/rs6000/rs6000.c | 72 |
1 files changed, 36 insertions, 36 deletions
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index c2daec61e32..127f4b140c1 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -3426,47 +3426,47 @@ rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode) adjust_address (operands[1], SImode, 4)); return; } - else if (mode == DImode && TARGET_POWERPC64 - && GET_CODE (operands[0]) == REG - && GET_CODE (operands[1]) == MEM && optimize > 0 - && SLOW_UNALIGNED_ACCESS (DImode, - MEM_ALIGN (operands[1]) > 32 - ? 32 - : MEM_ALIGN (operands[1])) - && !no_new_pseudos) - { - rtx reg = gen_reg_rtx (SImode); - emit_insn (gen_rtx_SET (SImode, reg, - adjust_address (operands[1], SImode, 0))); - reg = simplify_gen_subreg (DImode, reg, SImode, 0); - emit_insn (gen_insvdi (operands[0], GEN_INT (32), const0_rtx, reg)); - reg = gen_reg_rtx (SImode); - emit_insn (gen_rtx_SET (SImode, reg, - adjust_address (operands[1], SImode, 4))); - reg = simplify_gen_subreg (DImode, reg, SImode, 0); - emit_insn (gen_insvdi (operands[0], GEN_INT (32), GEN_INT (32), reg)); - return; - } - else if (mode == DImode && TARGET_POWERPC64 - && GET_CODE (operands[1]) == REG - && GET_CODE (operands[0]) == MEM && optimize > 0 - && SLOW_UNALIGNED_ACCESS (DImode, - MEM_ALIGN (operands[0]) > 32 - ? 32 - : MEM_ALIGN (operands[0])) - && !no_new_pseudos) + else if (mode == DImode && TARGET_POWERPC64 + && GET_CODE (operands[0]) == REG + && GET_CODE (operands[1]) == MEM && optimize > 0 + && SLOW_UNALIGNED_ACCESS (DImode, + MEM_ALIGN (operands[1]) > 32 + ? 32 + : MEM_ALIGN (operands[1])) + && !no_new_pseudos) + { + rtx reg = gen_reg_rtx (SImode); + emit_insn (gen_rtx_SET (SImode, reg, + adjust_address (operands[1], SImode, 0))); + reg = simplify_gen_subreg (DImode, reg, SImode, 0); + emit_insn (gen_insvdi (operands[0], GEN_INT (32), const0_rtx, reg)); + reg = gen_reg_rtx (SImode); + emit_insn (gen_rtx_SET (SImode, reg, + adjust_address (operands[1], SImode, 4))); + reg = simplify_gen_subreg (DImode, reg, SImode, 0); + emit_insn (gen_insvdi (operands[0], GEN_INT (32), GEN_INT (32), reg)); + return; + } + else if (mode == DImode && TARGET_POWERPC64 + && GET_CODE (operands[1]) == REG + && GET_CODE (operands[0]) == MEM && optimize > 0 + && SLOW_UNALIGNED_ACCESS (DImode, + MEM_ALIGN (operands[0]) > 32 + ? 32 + : MEM_ALIGN (operands[0])) + && !no_new_pseudos) { - rtx reg = gen_reg_rtx (DImode); - emit_move_insn (reg, + rtx reg = gen_reg_rtx (DImode); + emit_move_insn (reg, gen_rtx_LSHIFTRT (DImode, operands[1], GEN_INT (32))); - emit_move_insn (adjust_address (operands[0], SImode, 0), + emit_move_insn (adjust_address (operands[0], SImode, 0), simplify_gen_subreg (SImode, reg, DImode, 0)); - emit_move_insn (reg, operands[1]); - emit_move_insn (adjust_address (operands[0], SImode, 4), + emit_move_insn (reg, operands[1]); + emit_move_insn (adjust_address (operands[0], SImode, 4), simplify_gen_subreg (SImode, reg, DImode, 0)); - return; + return; } - + if (!no_new_pseudos) { if (GET_CODE (operands[1]) == MEM && optimize > 0 |