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| author | jakub <jakub@138bc75d-0d04-0410-961f-82ee72b054a4> | 2008-02-19 13:34:29 +0000 |
|---|---|---|
| committer | jakub <jakub@138bc75d-0d04-0410-961f-82ee72b054a4> | 2008-02-19 13:34:29 +0000 |
| commit | beb96ec845a6f487f452e149f15845e7a40d6743 (patch) | |
| tree | 90a7a6dd0d6601e827a549ffa825f2179e64e5d0 | |
| parent | 971c637a0881b594c1c35f25cde99191c3c9d4ad (diff) | |
| download | gcc-beb96ec845a6f487f452e149f15845e7a40d6743.tar.gz | |
PR target/35239
* config/i386/cpuid.h (__cpuid, __get_cpuid_max): Use special
32-bit inline asm without asm alternatives for host GCC < 3.0.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@132430 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/i386/cpuid.h | 30 |
2 files changed, 35 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9c8586ead3c..97587c7321a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2008-02-19 Jakub Jelinek <jakub@redhat.com> + + PR target/35239 + * config/i386/cpuid.h (__cpuid, __get_cpuid_max): Use special + 32-bit inline asm without asm alternatives for host GCC < 3.0. + 2008-02-19 Richard Guenther <rguenther@suse.de> PR tree-optimization/34989 diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h index 7fa4f681547..29abac734db 100644 --- a/gcc/config/i386/cpuid.h +++ b/gcc/config/i386/cpuid.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2007 Free Software Foundation, Inc. + * Copyright (C) 2007, 2008 Free Software Foundation, Inc. * * This file is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -61,6 +61,7 @@ #if defined(__i386__) && defined(__PIC__) /* %ebx may be the PIC register. */ +#if __GNUC__ >= 3 #define __cpuid(level, a, b, c, d) \ __asm__ ("xchg{l}\t{%%}ebx, %1\n\t" \ "cpuid\n\t" \ @@ -68,6 +69,16 @@ : "=a" (a), "=r" (b), "=c" (c), "=d" (d) \ : "0" (level)) #else +/* Host GCCs older than 3.0 weren't supporting Intel asm syntax + nor alternatives in i386 code. */ +#define __cpuid(level, a, b, c, d) \ + __asm__ ("xchgl\t%%ebx, %1\n\t" \ + "cpuid\n\t" \ + "xchgl\t%%ebx, %1\n\t" \ + : "=a" (a), "=r" (b), "=c" (c), "=d" (d) \ + : "0" (level)) +#endif +#else #define __cpuid(level, a, b, c, d) \ __asm__ ("cpuid\n\t" \ : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \ @@ -87,6 +98,7 @@ __get_cpuid_max (unsigned int __ext, unsigned int *__sig) unsigned int __eax, __ebx, __ecx, __edx; #ifndef __x86_64__ +#if __GNUC__ >= 3 /* See if we can use cpuid. On AMD64 we always can. */ __asm__ ("pushf{l|d}\n\t" "pushf{l|d}\n\t" @@ -100,6 +112,22 @@ __get_cpuid_max (unsigned int __ext, unsigned int *__sig) "popf{l|d}\n\t" : "=&r" (__eax), "=&r" (__ebx) : "i" (0x00200000)); +#else +/* Host GCCs older than 3.0 weren't supporting Intel asm syntax + nor alternatives in i386 code. */ + __asm__ ("pushfl\n\t" + "pushfl\n\t" + "popl\t%0\n\t" + "movl\t%0, %1\n\t" + "xorl\t%2, %0\n\t" + "pushl\t%0\n\t" + "popfl\n\t" + "pushfl\n\t" + "popl\t%0\n\t" + "popfl\n\t" + : "=&r" (__eax), "=&r" (__ebx) + : "i" (0x00200000)); +#endif if (!((__eax ^ __ebx) & 0x00200000)) return 0; |