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author | willschm <willschm@138bc75d-0d04-0410-961f-82ee72b054a4> | 2017-08-09 19:02:41 +0000 |
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committer | willschm <willschm@138bc75d-0d04-0410-961f-82ee72b054a4> | 2017-08-09 19:02:41 +0000 |
commit | eaaf318f19f659caf385e1d458dfc77ca180f3ea (patch) | |
tree | 13e7f33f4adda0e446edc2e89e4435e7d6b87ddd | |
parent | bff6c70873a2172b3bbe970540d6e6f313950395 (diff) | |
download | gcc-eaaf318f19f659caf385e1d458dfc77ca180f3ea.tar.gz |
[gcc/testsuite]
2017-08-09 Will Schmidt <will_schmidt@vnet.ibm.com>
* gcc.target/powerpc/fold-vec-madd-double.c: New.
* gcc.target/powerpc/fold-vec-madd-float.c: New.
* gcc.target/powerpc/fold-vec-madd-short.c: New.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@250996 138bc75d-0d04-0410-961f-82ee72b054a4
-rw-r--r-- | gcc/testsuite/ChangeLog | 6 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/powerpc/fold-vec-madd-double.c | 17 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/powerpc/fold-vec-madd-float.c | 17 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/powerpc/fold-vec-madd-short.c | 38 |
4 files changed, 78 insertions, 0 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 97a17e33f16..6e02fad4f4a 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,11 @@ 2017-08-09 Will Schmidt <will_schmidt@vnet.ibm.com> + * gcc.target/powerpc/fold-vec-madd-double.c: New. + * gcc.target/powerpc/fold-vec-madd-float.c: New. + * gcc.target/powerpc/fold-vec-madd-short.c: New. + +2017-08-09 Will Schmidt <will_schmidt@vnet.ibm.com> + * gcc.target/powerpc/fold-vec-cntlz-int.c: New. * gcc.target/powerpc/fold-vec-cntlz-char.c: New. * gcc.target/powerpc/fold-vec-cntlz-short.c: New. diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-madd-double.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-madd-double.c new file mode 100644 index 00000000000..0fe78241294 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-madd-double.c @@ -0,0 +1,17 @@ +/* Verify that overloaded built-ins for vec_madd with + double inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ + +#include <altivec.h> + +vector double +testd_l (vector double vd2, vector double vd3, vector double vd4) +{ + return vec_madd (vd2, vd3, vd4); +} + +/* { dg-final { scan-assembler-times "xvmaddmdp|xvmaddadp" 1 } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-madd-float.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-madd-float.c new file mode 100644 index 00000000000..fcfe0c38656 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-madd-float.c @@ -0,0 +1,17 @@ +/* Verify that overloaded built-ins for vec_madd with float + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2" } */ + +#include <altivec.h> + +vector float +testf_l (vector float vf2, vector float vf3, vector float vf4) +{ + return vec_madd (vf2, vf3, vf4); +} + +/* { dg-final { scan-assembler-times "xvmaddmsp|xvmaddasp" 1 } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-madd-short.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-madd-short.c new file mode 100644 index 00000000000..0e78f3585f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-madd-short.c @@ -0,0 +1,38 @@ +/* Verify that overloaded built-ins for vec_madd with short + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O2" } */ + +#include <altivec.h> + +vector signed short +test_mad_sss (vector signed short vss2, vector signed short vss3, + vector signed short vss4) +{ + return vec_madd (vss2, vss3, vss4); +} + +vector signed short +test_mad_suu (vector signed short vss2, vector unsigned short vus3, + vector unsigned short vus4) +{ + return vec_madd (vss2, vus3, vus4); +} + +vector signed short +test_mad_uss (vector unsigned short vus2, vector signed short vss3, + vector signed short vss4) +{ + return vec_madd (vus2, vss3, vss4); +} + +vector unsigned short +test_mad_uuu (vector unsigned short vus2, vector unsigned short vus3, + vector unsigned short vus4) +{ + return vec_madd (vus2, vus3, vus4); +} + +/* { dg-final { scan-assembler-times "vmladduhm" 4 } } */ |