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authorktkachov <ktkachov@138bc75d-0d04-0410-961f-82ee72b054a4>2017-12-14 09:50:33 +0000
committerktkachov <ktkachov@138bc75d-0d04-0410-961f-82ee72b054a4>2017-12-14 09:50:33 +0000
commit44bd1138645238bb21ca7bfc0b57db7e50f762ac (patch)
tree81afa03b1e467c1ecd9e7768e55e8326431b079a
parent62634750ad2228b91bf2c623331c657267bcffca (diff)
downloadgcc-44bd1138645238bb21ca7bfc0b57db7e50f762ac.tar.gz
[AArch64] Specify fp16 support for Cortex-A55 and Cortex-A75
The Cortex-A55 and Cortex-A75 processors support the fp16 extension. We already specify them as such in the arm port. This patch makes aarch64 consistent on this front. Bootstrapped and tested on aarch64-none-linux-gnu. Manually checked that compiling with aarch64-none-linux-gnu-gcc -mcpu=cortex-a55 -dM -E - < /dev/null shows __ARM_FEATURE_FP16_VECTOR_ARITHMETIC and __ARM_FEATURE_FP16_SCALAR_ARITHMETIC being specified as expected whereas they were not before this patch. * config/aarch64/aarch64-cores.def (cortex-a55, cortex-a75, cortex-a75.cortex-a55): Specify AARCH64_FL_F16 in the arch features. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@255624 138bc75d-0d04-0410-961f-82ee72b054a4
-rw-r--r--gcc/ChangeLog5
-rw-r--r--gcc/config/aarch64/aarch64-cores.def6
2 files changed, 8 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9d4869eadba..5e18fb9aa89 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2017-12-14 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * config/aarch64/aarch64-cores.def (cortex-a55, cortex-a75,
+ cortex-a75.cortex-a55): Specify AARCH64_FL_F16 in the arch features.
+
2017-12-14 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def
index cdf047c0fa2..fa08cdf48cd 100644
--- a/gcc/config/aarch64/aarch64-cores.def
+++ b/gcc/config/aarch64/aarch64-cores.def
@@ -83,8 +83,8 @@ AARCH64_CORE("thunderx2t99", thunderx2t99, thunderx2t99, 8_1A, AARCH64_FL_FOR
/* ARMv8.2-A Architecture Processors. */
/* ARM ('A') cores. */
-AARCH64_CORE("cortex-a55", cortexa55, cortexa53, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa53, 0x41, 0xd05, -1)
-AARCH64_CORE("cortex-a75", cortexa75, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa73, 0x41, 0xd0a, -1)
+AARCH64_CORE("cortex-a55", cortexa55, cortexa53, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa53, 0x41, 0xd05, -1)
+AARCH64_CORE("cortex-a75", cortexa75, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa73, 0x41, 0xd0a, -1)
/* ARMv8.3-A Architecture Processors. */
@@ -100,6 +100,6 @@ AARCH64_CORE("cortex-a73.cortex-a53", cortexa73cortexa53, cortexa53, 8A, AARCH
/* ARM DynamIQ big.LITTLE configurations. */
-AARCH64_CORE("cortex-a75.cortex-a55", cortexa75cortexa55, cortexa53, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa73, 0x41, AARCH64_BIG_LITTLE (0xd0a, 0xd05), -1)
+AARCH64_CORE("cortex-a75.cortex-a55", cortexa75cortexa55, cortexa53, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa73, 0x41, AARCH64_BIG_LITTLE (0xd0a, 0xd05), -1)
#undef AARCH64_CORE