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| author | uros <uros@138bc75d-0d04-0410-961f-82ee72b054a4> | 2017-09-28 18:11:41 +0000 |
|---|---|---|
| committer | uros <uros@138bc75d-0d04-0410-961f-82ee72b054a4> | 2017-09-28 18:11:41 +0000 |
| commit | 6b09daa1e565dff7d943075de5f8329652d1192d (patch) | |
| tree | 1f892b1b3d3a6a20f5c3b44a0e9134c94bab1653 | |
| parent | 67b313c93db43cc73d3731a8e50c2ef01c837fed (diff) | |
| download | gcc-6b09daa1e565dff7d943075de5f8329652d1192d.tar.gz | |
gcc/
* config/i386/i386.md (*movsf_internal, *movdf_internal):
Return 256-bit AVX modes for TARGET_PREFER_AVX256.
gcc/testsuite/
* gcc.target/i386/avx512f-constant-float-return.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@253259 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/i386/i386.md | 6 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/avx512f-constant-float-return.c | 15 |
4 files changed, 29 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a6c8b93c439..c8b67cdf2f9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2017-09-28 Sergey Shalnov <Sergey.Shalnov@intel.com> + + * config/i386/i386.md (*movsf_internal, *movdf_internal): + Return 256-bit AVX modes for TARGET_PREFER_AVX256. + 2017-09-28 Thomas Preud'homme <thomas.preudhomme@arm.com> * config/arm/arm.c (arm_option_override): Forbid ARMv8-M Security @@ -785,7 +790,7 @@ 2017-09-21 Martin Sebor <msebor@redhat.com> - * PR c/81882 + PR c/81882 * doc/extend.texi (attribute ifunc): Avoid relying on ill-formed code (in C++) or code that triggers warnings. diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index f51e02c7732..b9a392852d4 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -3524,7 +3524,8 @@ (eq_attr "alternative" "12,16") (cond [(not (match_test "TARGET_SSE2")) (const_string "V4SF") - (match_test "TARGET_AVX512F") + (and (match_test "TARGET_AVX512F") + (not (match_test "TARGET_PREFER_AVX256"))) (const_string "XI") (match_test "TARGET_AVX") (const_string "V2DF") @@ -3693,7 +3694,8 @@ (eq_attr "alternative" "5") (cond [(not (match_test "TARGET_SSE2")) (const_string "V4SF") - (match_test "TARGET_AVX512F") + (and (match_test "TARGET_AVX512F") + (not (match_test "TARGET_PREFER_AVX256"))) (const_string "V16SF") (match_test "TARGET_AVX") (const_string "V4SF") diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index d016f99f904..c86a664de4d 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2017-09-28 Sergey Shalnov <Sergey.Shalnov@intel.com> + + * gcc.target/i386/avx512f-constant-float-return.c: New test. + 2017-09-28 Christophe Lyon <christophe.lyon@linaro.org> * gcc.target/arm/aapcs/align4.c: Require arm_neon_hw effective target. diff --git a/gcc/testsuite/gcc.target/i386/avx512f-constant-float-return.c b/gcc/testsuite/gcc.target/i386/avx512f-constant-float-return.c new file mode 100644 index 00000000000..153cf698127 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-constant-float-return.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=skylake-avx512 -mprefer-avx256" } */ +/* { dg-final { scan-assembler-not "%zmm\[0-9\]+" } } */ + +float +my_test_f() +{ + return 0.0f; +} + +double +my_test_d() +{ + return 0.0; +} |