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| author | rearnsha <rearnsha@138bc75d-0d04-0410-961f-82ee72b054a4> | 2009-07-15 10:12:22 +0000 |
|---|---|---|
| committer | rearnsha <rearnsha@138bc75d-0d04-0410-961f-82ee72b054a4> | 2009-07-15 10:12:22 +0000 |
| commit | 1c274529fc9415135a0e7895cea8389ecc9bb30b (patch) | |
| tree | d553384857d12a6b186d25060e36c9afc8893241 | |
| parent | 1a8bc727477c2bf5567d972c14ecbc17eec53d6c (diff) | |
| download | gcc-1c274529fc9415135a0e7895cea8389ecc9bb30b.tar.gz | |
* arm.md (ior_xor): New code iterator.
(split for ior/xor with shift and zero-extend): New split pattern.
* arm/predicates.md (subreg_lowpart_operator): New special predicate.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@149673 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 22 | ||||
| -rw-r--r-- | gcc/config/arm/predicates.md | 4 |
3 files changed, 32 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e3f5d0c1e44..8ae44d8bdb6 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2009-07-15 Richard Earnshaw <rearnsha@arm.com> + + * arm.md (ior_xor): New code iterator. + (split for ior/xor with shift and zero-extend): New split pattern. + * arm/predicates.md (subreg_lowpart_operator): New special predicate. + 2009-07-15 Richard Guenther <rguenther@suse.de> * tree-ssa-structalias.c (make_constraint_from_heapvar): Initialize diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 0fd0a1982ea..809f2c49b97 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -4207,6 +4207,28 @@ "" ) +(define_code_iterator ior_xor [ior xor]) + +(define_split + [(set (match_operand:SI 0 "s_register_operand" "") + (ior_xor:SI (and:SI (ashift:SI + (match_operand:SI 1 "s_register_operand" "") + (match_operand:SI 2 "const_int_operand" "")) + (match_operand:SI 3 "const_int_operand" "")) + (zero_extend:SI + (match_operator 5 "subreg_lowpart_operator" + [(match_operand:SI 4 "s_register_operand" "")]))))] + "TARGET_32BIT + && (INTVAL (operands[3]) + == (GET_MODE_MASK (GET_MODE (operands[5])) + & (GET_MODE_MASK (GET_MODE (operands[5])) + << (INTVAL (operands[2])))))" + [(set (match_dup 0) (ior_xor:SI (ashift:SI (match_dup 1) (match_dup 2)) + (match_dup 4))) + (set (match_dup 0) (zero_extend:SI (match_dup 5)))] + "operands[5] = gen_lowpart (GET_MODE (operands[5]), operands[0]);" +) + (define_insn "*compareqi_eq0" [(set (reg:CC_Z CC_REGNUM) (compare:CC_Z (match_operand:QI 0 "s_register_operand" "r") diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index 7997cc94cf5..d351f443851 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -73,6 +73,10 @@ || REGNO_REG_CLASS (REGNO (op)) == FPA_REGS)); }) +(define_special_predicate "subreg_lowpart_operator" + (and (match_code "subreg") + (match_test "subreg_lowpart_p (op)"))) + ;; Reg, subreg(reg) or const_int. (define_predicate "reg_or_int_operand" (ior (match_code "const_int") |