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| author | Yvan Roux <yvan.roux@linaro.org> | 2017-08-10 15:15:07 +0200 |
|---|---|---|
| committer | Yvan Roux <yvan.roux@linaro.org> | 2017-08-16 08:02:07 +0000 |
| commit | 3e651fe5bff3d64fa8e79da839d10048e6d06275 (patch) | |
| tree | 35de5e6c2dbac940ec9d82e29dd0dd1c77e20559 | |
| parent | 60317f7d28c701732c7f2109eb61978adf4981f8 (diff) | |
| download | gcc-3e651fe5bff3d64fa8e79da839d10048e6d06275.tar.gz | |
gcc/
Backport from trunk r249200.
2017-06-14 Wilco Dijkstra <wdijkstr@arm.com>
* config/arm/cortex-a53.md (cortex_a53_fpalu) Adjust latency.
(cortex_a53_fconst): Likewise.
(cortex_a53_fpmul): Likewise.
(cortex_a53_f_load_64): Likewise.
(cortex_a53_f_load_many): Likewise.
(cortex_a53_advsimd_alu): Likewise.
(cortex_a53_advsimd_alu_q): Likewise.
(cortex_a53_advsimd_mul): Likewise.
(cortex_a53_advsimd_mul_q): Likewise.
(fpmac bypass): Add new bypass for fpmac-fpmac case.
Add missing fmul, r2f_cvt and fconst cases.
Change-Id: I258a4aa9e9f490f9cd0583624aee54d8143d8802
| -rw-r--r-- | gcc/config/arm/cortex-a53.md | 34 |
1 files changed, 16 insertions, 18 deletions
diff --git a/gcc/config/arm/cortex-a53.md b/gcc/config/arm/cortex-a53.md index b7e0c9257f7..ff16e360a66 100644 --- a/gcc/config/arm/cortex-a53.md +++ b/gcc/config/arm/cortex-a53.md @@ -511,19 +511,19 @@ ;; Floating-point arithmetic. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -(define_insn_reservation "cortex_a53_fpalu" 5 +(define_insn_reservation "cortex_a53_fpalu" 4 (and (eq_attr "tune" "cortexa53") (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fmov, f_cvt, fcmps, fcmpd, fccmps, fccmpd, fcsel, f_rints, f_rintd, f_minmaxs, f_minmaxd")) "cortex_a53_slot_any,cortex_a53_fp_alu") -(define_insn_reservation "cortex_a53_fconst" 3 +(define_insn_reservation "cortex_a53_fconst" 2 (and (eq_attr "tune" "cortexa53") (eq_attr "type" "fconsts,fconstd")) "cortex_a53_slot_any,cortex_a53_fp_alu") -(define_insn_reservation "cortex_a53_fpmul" 5 +(define_insn_reservation "cortex_a53_fpmul" 4 (and (eq_attr "tune" "cortexa53") (eq_attr "type" "fmuls,fmuld")) "cortex_a53_slot_any,cortex_a53_fp_mul") @@ -574,7 +574,7 @@ ;; Floating-point load/store. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -(define_insn_reservation "cortex_a53_f_load_64" 4 +(define_insn_reservation "cortex_a53_f_load_64" 3 (and (eq_attr "tune" "cortexa53") (ior (eq_attr "type" "f_loads,f_loadd") (eq_attr "cortex_a53_advsimd_type" @@ -582,7 +582,7 @@ "cortex_a53_slot_any+cortex_a53_ls_agen, cortex_a53_load") -(define_insn_reservation "cortex_a53_f_load_many" 5 +(define_insn_reservation "cortex_a53_f_load_many" 4 (and (eq_attr "tune" "cortexa53") (eq_attr "cortex_a53_advsimd_type" "advsimd_load_128,advsimd_load_lots")) @@ -616,22 +616,22 @@ ;; or a 128-bit operation in which case we require in our model that we ;; issue from slot 0. -(define_insn_reservation "cortex_a53_advsimd_alu" 5 +(define_insn_reservation "cortex_a53_advsimd_alu" 4 (and (eq_attr "tune" "cortexa53") (eq_attr "cortex_a53_advsimd_type" "advsimd_alu")) "cortex_a53_slot_any,cortex_a53_fp_alu") -(define_insn_reservation "cortex_a53_advsimd_alu_q" 5 +(define_insn_reservation "cortex_a53_advsimd_alu_q" 4 (and (eq_attr "tune" "cortexa53") (eq_attr "cortex_a53_advsimd_type" "advsimd_alu_q")) "cortex_a53_slot0,cortex_a53_fp_alu_q") -(define_insn_reservation "cortex_a53_advsimd_mul" 5 +(define_insn_reservation "cortex_a53_advsimd_mul" 4 (and (eq_attr "tune" "cortexa53") (eq_attr "cortex_a53_advsimd_type" "advsimd_mul")) "cortex_a53_slot_any,cortex_a53_fp_mul") -(define_insn_reservation "cortex_a53_advsimd_mul_q" 5 +(define_insn_reservation "cortex_a53_advsimd_mul_q" 4 (and (eq_attr "tune" "cortexa53") (eq_attr "cortex_a53_advsimd_type" "advsimd_mul_q")) "cortex_a53_slot0,cortex_a53_fp_mul_q") @@ -710,20 +710,18 @@ ;; multiply-accumulate operations as a bypass reducing the latency ;; of producing instructions to near zero. -(define_bypass 1 "cortex_a53_fp*, +(define_bypass 1 "cortex_a53_fpalu, + cortex_a53_fpmul, cortex_a53_r2f, + cortex_a53_r2f_cvt, + cortex_a53_fconst, cortex_a53_f_load*" "cortex_a53_fpmac" "aarch_accumulator_forwarding") -;; Model a bypass from the result of an FP operation to a use. - -(define_bypass 4 "cortex_a53_fpalu, - cortex_a53_fpmul" - "cortex_a53_fpalu, - cortex_a53_fpmul, - cortex_a53_fpmac, - cortex_a53_advsimd_div*") +(define_bypass 4 "cortex_a53_fpmac" + "cortex_a53_fpmac" + "aarch_accumulator_forwarding") ;; We want AESE and AESMC to end up consecutive to one another. |