* Makefile.in (HOST_CFLAGS): Take out -DGENERATOR_FILE.

(CONFIG_H, TCONFIG_H, TM_P_H): Update. (GEN, STAGESTUFF): Add new files. (insn-constants.h, s-constants, tm-preds.h, s-preds, genconstants, genpreds, genconstants.o, genpreds.o): New rules. (hashtab.o, safe-ctype.o): Add -DGENERATOR_FILE. * mkconfig.sh: Include tm-preds.h in tm_p.h; insn-constants.h as well as insn-codes.h and insn-flags.h in config.h; and no extra headers in tconfig.h and hconfig.h. * gencodes.c: Eliminate code to generate predicate declarations or #defines for md-file constants. * genconstants.c, genpreds.c: New files. * i386.md: Re-order guard expressions such that TARGET_64BIT comes first, when this permits better optimization. Add TARGET_64BIT to more x86-64 patterns. Add comment explaining why this is desirable. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@44743 138bc75d-0d04-0410-961f-82ee72b054a4
author: zack <zack@138bc75d-0d04-0410-961f-82ee72b054a4> 2001-08-09 17:11:00 +0000
committer: zack <zack@138bc75d-0d04-0410-961f-82ee72b054a4> 2001-08-09 17:11:00 +0000
commit: e23a6527d76e7d7d1e4b1a2d2787681b0202bc9a (patch)
tree: c707f6fbe6eee894928f18532faad363c22b3b19
parent: 45c2202bc22116481baf8d8fd6cb3af45627a784 (diff)
download: gcc-e23a6527d76e7d7d1e4b1a2d2787681b0202bc9a.tar.gz
7 files changed, 381 insertions, 201 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e27d76c5bcb..ec34ae2e195 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,24 @@
+2001-08-09  Zack Weinberg  <zackw@stanford.edu>
+
+	 * Makefile.in (HOST_CFLAGS): Take out -DGENERATOR_FILE.
+	 (CONFIG_H, TCONFIG_H, TM_P_H): Update.
+	 (GEN, STAGESTUFF): Add new files.
+	 (insn-constants.h, s-constants, tm-preds.h, s-preds,
+	 genconstants, genpreds, genconstants.o, genpreds.o): New rules.
+	 (hashtab.o, safe-ctype.o): Add -DGENERATOR_FILE.
+	 * mkconfig.sh: Include tm-preds.h in tm_p.h; insn-constants.h
+	 as well as insn-codes.h and insn-flags.h in config.h; and no
+	 extra headers in tconfig.h and hconfig.h.
+
+	 * gencodes.c: Eliminate code to generate predicate declarations
+	 or #defines for md-file constants.
+	 * genconstants.c, genpreds.c: New files.
+
+	 * i386.md: Re-order guard expressions such that TARGET_64BIT
+	 comes first, when this permits better optimization.  Add
+	 TARGET_64BIT to more x86-64 patterns.  Add comment explaining
+	 why this is desirable.
+
 2001-08-09  Jakub Jelinek  <jakub@redhat.com>
 
 	* config/ia64/fde-glibc.c: Require glibc 2.2.4+ headers.
@@ -19,8 +40,8 @@ Thu Aug  9 11:30:20 2001  Richard Kenner  <kenner@vlsi1.ultra.nyu.edu>
 
 2001-08-09  Graham Stott  <grahams@redhat.com>
 
-	* predict.c (estimate_probability): Replace magic numbers with 
-	appropriate enumeration. 	
+	* predict.c (estimate_probability): Replace magic numbers with
+	appropriate enumeration.
 
 2001-08-09  Graham Stott  <grahams@redhat.com>
 
@@ -30,8 +51,8 @@ Thu Aug  9 11:30:20 2001  Richard Kenner  <kenner@vlsi1.ultra.nyu.edu>
 
 2001-08-09  Aldy Hernandez  <aldyh@redhat.com>
 
-        * config/mips/mips.c	(mips_legitimate_address_p): Check for
-        CONST_INT in last patch.	
+	* config/mips/mips.c	(mips_legitimate_address_p): Check for
+	CONST_INT in last patch.
 
 2001-08-08  Anthony Green  <green@redhat.com>
 
@@ -74,10 +95,10 @@ Thu Aug  9 11:30:20 2001  Richard Kenner  <kenner@vlsi1.ultra.nyu.edu>
 
 2001-08-08  Jan van Male <jan.vanmale@fenk.wau.nl>
 
-        * emit-rtl.c (adjust_address, adjust_address_nv): Cast offset to
+	* emit-rtl.c (adjust_address, adjust_address_nv): Cast offset to
 	unsigned HOST_WIDE_INT to avoid warning.
-        * final.c (final): Cast INSN_UID to unsigned to avoid warning.
-        * flow.c (set_block_for_new_insns): Likewise.
+	* final.c (final): Cast INSN_UID to unsigned to avoid warning.
+	* flow.c (set_block_for_new_insns): Likewise.
 
 Wed Aug  8 21:08:14 CEST 2001  Jan Hubicka  <jh@suse.cz>
 
@@ -270,8 +291,8 @@ Tue Aug  7 22:18:06 CEST 2001  Jan Hubicka  <jh@suse.cz>
 
 2001-08-07  Daniel Jacobowitz  <drow@mvista.com>
 
-        * config.gcc: Quote target_cpu_default2 correctly for
-        powerpc*-*-* targets.
+	* config.gcc: Quote target_cpu_default2 correctly for
+	powerpc*-*-* targets.
 
 2001-08-07  Neil Booth  <neil@daikokuya.demon.co.uk>
 
diff --git a/gcc/Makefile.in b/gcc/Makefile.in
index 266201b73a9..bfa3a84dd27 100644
--- a/gcc/Makefile.in
+++ b/gcc/Makefile.in
@@ -482,7 +482,7 @@ HOST_PREFIX_1=loser-
 HOST_CC=$(CC)
 # If you change any of the following variables, check whether a
 # similar change is needed in build-make.
-HOST_CFLAGS=$(ALL_CFLAGS) -DGENERATOR_FILE
+HOST_CFLAGS=$(ALL_CFLAGS)
 HOST_LDFLAGS=$(LDFLAGS)
 HOST_CPPFLAGS=$(ALL_CPPFLAGS)
 HOST_OBSTACK=$(OBSTACK)
@@ -550,14 +550,14 @@ all: all.indirect
 
 # GCONFIG_H lists the config files that the generator files depend on, while
 # CONFIG_H lists the the ones ordinary gcc files depend on, which includes
-# a file generated by gencodes.
+# several files generated by those generators.
 GCONFIG_H = config.h $(host_xm_file_list)
 HCONFIG_H = hconfig.h $(build_xm_file_list)
-CONFIG_H = $(GCONFIG_H) insn-codes.h insn-flags.h
-TCONFIG_H = tconfig.h $(xm_file_list) insn-codes.h
+CONFIG_H = $(GCONFIG_H) insn-constants.h insn-codes.h insn-flags.h
+TCONFIG_H = tconfig.h $(xm_file_list)
 TARGET_H = target.h
 TARGET_DEF_H = target-def.h
-TM_P_H = tm_p.h $(tm_p_file_list) insn-codes.h
+TM_P_H = tm_p.h $(tm_p_file_list) tm-preds.h
 
 MACHMODE_H = machmode.h machmode.def
 RTL_BASE_H = rtl.h rtl.def $(MACHMODE_H)
@@ -762,20 +762,22 @@ BACKEND = main.o libbackend.a
 GEN= genemit$(build_exeext) genoutput$(build_exeext) genrecog$(build_exeext) \
  genextract$(build_exeext) genflags$(build_exeext) gencodes$(build_exeext)   \
  genconfig$(build_exeext) genpeep$(build_exeext) gengenrtl$(build_exeext)    \
- gencheck$(build_exeext)
+ gencheck$(build_exeext) genpreds$(build_exeext) genconstants$(build_exeext)
 
 # Files to be copied away after each stage in building.
 STAGESTUFF = *$(objext) insn-flags.h insn-config.h insn-codes.h \
  insn-output.c insn-recog.c insn-emit.c insn-extract.c insn-peep.c \
- insn-attr.h insn-attrtab.c insn-opinit.c tree-check.h \
+ insn-attr.h insn-attrtab.c insn-opinit.c insn-constants.h tm-preds.h \
+ tree-check.h \
  s-flags s-config s-codes s-mlib s-under s-genrtl \
  s-output s-recog s-emit s-extract s-peep s-check \
- s-attr s-attrtab s-opinit s-crt0 \
+ s-attr s-attrtab s-opinit s-preds s-constants s-crt0 \
  genemit$(build_exeext) genoutput$(build_exeext) genrecog$(build_exeext) \
  genextract$(build_exeext) genflags$(build_exeext) gencodes$(build_exeext) \
  genconfig$(build_exeext) genpeep$(build_exeext) genattrtab$(build_exeext) \
  genattr$(build_exeext) genopinit$(build_exeext) gengenrtl$(build_exeext) \
- gencheck$(build_exeext) genrtl.c genrtl.h \
+ gencheck$(build_exeext) genpreds$(build_exeext) genconstants$(build_exeext) \
+ genrtl.c genrtl.h \
  xgcc$(exeext) cpp$(exeext) cc1$(exeext) cpp0$(exeext) $(EXTRA_PASSES) \
  $(EXTRA_PARTS) $(EXTRA_PROGRAMS) gcc-cross$(exeext) cc1obj$(exeext) \
  enquire$(exeext) protoize$(exeext) unprotoize$(exeext) \
@@ -1591,7 +1593,7 @@ halfpic.o: halfpic.c $(CONFIG_H) $(RTL_H) $(TREE_H) $(SYSTEM_H)
 # Generate header and source files from the machine description,
 # and compile them.
 
-.PRECIOUS: insn-config.h insn-flags.h insn-codes.h \
+.PRECIOUS: insn-config.h insn-flags.h insn-codes.h insn-constants.h \
   insn-emit.c insn-recog.c insn-extract.c insn-output.c insn-peep.c \
   insn-attr.h insn-attrtab.c
 
@@ -1632,6 +1634,12 @@ s-codes : $(md_file) gencodes$(build_exeext) $(srcdir)/move-if-change
 	$(SHELL) $(srcdir)/move-if-change tmp-codes.h insn-codes.h
 	$(STAMP) s-codes
 
+insn-constants.h: s-constants ; @true
+s-constants : $(md_file) genconstants$(build_exeext) $(srcdir)/move-if-change
+	./genconstants$(build_exeext) $(md_file) > tmp-constants.h
+	$(SHELL) $(srcdir)/move-if-change tmp-constants.h insn-constants.h
+	$(STAMP) s-constants
+
 insn-emit.o : insn-emit.c $(CONFIG_H) $(RTL_H) $(EXPR_H) real.h output.h \
   insn-config.h $(SYSTEM_H) reload.h $(RECOG_H) toplev.h \
   function.h flags.h hard-reg-set.h resource.h $(TM_P_H)
@@ -1718,11 +1726,19 @@ genrtl.c genrtl.h : s-genrtl
 	@true	# force gnu make to recheck modification times.
 
 s-genrtl: gengenrtl$(build_exeext) $(srcdir)/move-if-change $(RTL_BASE_H)
-	./gengenrtl$(build_exeext) -h >tmp-genrtl.h
+	./gengenrtl$(build_exeext) -h > tmp-genrtl.h
 	$(SHELL) $(srcdir)/move-if-change tmp-genrtl.h genrtl.h
-	./gengenrtl$(build_exeext) >tmp-genrtl.c
+	./gengenrtl$(build_exeext) > tmp-genrtl.c
 	$(SHELL) $(srcdir)/move-if-change tmp-genrtl.c genrtl.c
 	$(STAMP) s-genrtl
+
+tm-preds.h: s-preds; @true
+
+s-preds: genpreds$(build_exeext) $(srcdir)/move-if-change
+	./genpreds$(build_exeext) > tmp-preds.h
+	$(SHELL) $(srcdir)/move-if-change tmp-preds.h tm-preds.h
+	$(STAMP) s-preds
+
 #
 # Compile the programs that generate insn-* from the machine description.
 # They are compiled with $(HOST_CC), and associated libraries,
@@ -1744,12 +1760,12 @@ gensupport.o: gensupport.c $(RTL_H) $(OBSTACK_H) $(SYSTEM_H) errors.h gensupport
 hashtab.o: $(srcdir)/../libiberty/hashtab.c $(GCONFIG_H)
 	rm -f hashtab.c
 	$(LN_S) $(srcdir)/../libiberty/hashtab.c hashtab.c
-	$(HOST_CC) -c $(HOST_CFLAGS) $(HOST_CPPFLAGS) $(INCLUDES) hashtab.c
+	$(HOST_CC) -c $(HOST_CFLAGS) -DGENERATOR_FILE $(HOST_CPPFLAGS) $(INCLUDES) hashtab.c
 
 safe-ctype.o: $(srcdir)/../libiberty/safe-ctype.c $(GCONFIG_H)
 	rm -f safe-ctype.c
 	$(LN_S) $(srcdir)/../libiberty/safe-ctype.c safe-ctype.c
-	$(HOST_CC) -c $(HOST_CFLAGS) $(HOST_CPPFLAGS) $(INCLUDES) safe-ctype.c
+	$(HOST_CC) -c $(HOST_CFLAGS) -DGENERATOR_FILE $(HOST_CPPFLAGS) $(INCLUDES) safe-ctype.c
 
 genconfig$(build_exeext) : genconfig.o $(HOST_RTL) $(HOST_PRINT) $(HOST_ERRORS) $(HOST_LIBDEPS)
 	$(HOST_CC) $(HOST_CFLAGS) $(HOST_LDFLAGS) -o $@ \
@@ -1775,6 +1791,13 @@ gencodes.o : gencodes.c $(RTL_H) $(HCONFIG_H) \
   $(SYSTEM_H) errors.h gensupport.h
 	$(HOST_CC) -c $(HOST_CFLAGS) $(HOST_CPPFLAGS) $(INCLUDES) $(srcdir)/gencodes.c
 
+genconstants$(build_exeext) : genconstants.o $(HOST_RTL) $(HOST_ERRORS) $(HOST_LIBDEPS)
+	$(HOST_CC) $(HOST_CFLAGS) $(HOST_LDFLAGS) -o $@ \
+	 genconstants.o $(HOST_RTL) $(HOST_ERRORS) $(HOST_LIBS)
+
+genconstants.o : genconstants.c $(RTL_H) $(HCONFIG_H) $(SYSTEM_H) errors.h
+	$(HOST_CC) -c $(HOST_CFLAGS) $(HOST_CPPFLAGS) $(INCLUDES) $(srcdir)/genconstants.c
+
 genemit$(build_exeext) : genemit.o $(HOST_RTL) $(HOST_PRINT) $(HOST_ERRORS) $(HOST_LIBDEPS)
 	$(HOST_CC) $(HOST_CFLAGS) $(HOST_LDFLAGS) -o $@ \
 	 genemit.o $(HOST_RTL) $(HOST_PRINT) $(HOST_ERRORS) $(HOST_LIBS)
@@ -1842,6 +1865,14 @@ gengenrtl$(build_exeext) : gengenrtl.o $(HOST_LIBDEPS)
 
 gengenrtl.o : gengenrtl.c $(RTL_BASE_H) $(HCONFIG_H) $(SYSTEM_H) real.h
 	$(HOST_CC) -c $(HOST_CFLAGS) $(HOST_CPPFLAGS) $(INCLUDES) $(srcdir)/gengenrtl.c
+
+genpreds$(build_exeext) : genpreds.o $(HOST_LIBDEPS)
+	$(HOST_CC) $(HOST_CFLAGS) $(HOST_LDFLAGS) -o $@ \
+	 genpreds.o $(HOST_LIBS)
+
+genpreds.o : genpreds.c $(RTL_BASE_H) $(HCONFIG_H) $(SYSTEM_H)
+	$(HOST_CC) -c $(HOST_CFLAGS) $(HOST_CPPFLAGS) $(INCLUDES) $(srcdir)/genpreds.c
+
 #
 # Compile the libraries to be used by gen*.
 # If we are not cross-building, gen* use the same .o's that cc1 will use,
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 7f84549ab9c..75fb5027b28 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -96,6 +96,11 @@
 ;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
 ;; from i386.c.
 
+;; In C guard expressions, put expressions which may be compile-time
+;; constants first.  This allows for better optimization.  For
+;; example, write "TARGET_64BIT && reload_completed", not
+;; "reload_completed && TARGET_64BIT".
+
 
 ;; Processor type.  This attribute must exactly match the processor_type
 ;; enumeration in i386.h.
@@ -1074,7 +1079,7 @@
 	(compare (minus:DI (match_operand:DI 0 "nonimmediate_operand" "rm,r")
 			   (match_operand:DI 1 "x86_64_general_operand" "re,mr"))
 		 (const_int 0)))]
-  "ix86_match_ccmode (insn, CCGOCmode)"
+  "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)"
   "cmp{q}\t{%1, %0|%0, %1}"
   [(set_attr "type" "icmp")
    (set_attr "mode" "DI")])
@@ -1083,7 +1088,7 @@
   [(set (reg:CC 17)
 	(compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
 		    (match_operand:DI 1 "general_operand" "")))]
-  ""
+  "TARGET_64BIT"
   "")
 
 (define_insn "cmpdi_1_insn_rex64"
@@ -1309,7 +1314,7 @@
   [(set (reg:CC 17)
 	(compare:CC (match_operand:XF 0 "cmp_fp_expander_operand" "")
 		    (match_operand:XF 1 "cmp_fp_expander_operand" "")))]
-  "TARGET_80387 && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_80387"
 {
   ix86_compare_op0 = operands[0];
   ix86_compare_op1 = operands[1];
@@ -1434,7 +1439,7 @@
 	(compare:CCFP
 	  (match_operand:XF 0 "register_operand" "f")
 	  (match_operand:XF 1 "register_operand" "f")))]
-  "TARGET_80387 && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_80387"
   "* return output_fp_compare (insn, operands, 0, 0);"
   [(set_attr "type" "fcmp")
    (set_attr "mode" "XF")])
@@ -1455,7 +1460,7 @@
 	  [(compare:CCFP
 	     (match_operand:XF 1 "register_operand" "f")
 	     (match_operand:XF 2 "register_operand" "f"))] 9))]
-  "TARGET_80387 && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_80387"
   "* return output_fp_compare (insn, operands, 2, 0);"
   [(set_attr "type" "multi")
    (set_attr "mode" "XF")])
@@ -2425,8 +2430,8 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(match_operand:DI 1 "const0_operand" "i"))
    (clobber (reg:CC 17))]
-  "reload_completed && (!TARGET_USE_MOV0 || optimize_size)
-   && TARGET_64BIT"
+  "TARGET_64BIT && (!TARGET_USE_MOV0 || optimize_size)
+   && reload_completed"
   "xor{l}\t{%k0, %k0|%k0, %k0}"
   [(set_attr "type" "alu1")
    (set_attr "mode" "SI")
@@ -2436,10 +2441,10 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(match_operand:DI 1 "const_int_operand" "i"))
    (clobber (reg:CC 17))]
-  "reload_completed && GET_CODE (operands[1]) == CONST_INT
-   && TARGET_64BIT
-   && INTVAL (operands[1]) == -1
-   && (TARGET_PENTIUM || optimize_size)"
+  "TARGET_64BIT && (TARGET_PENTIUM || optimize_size)
+   && reload_completed
+   && GET_CODE (operands[1]) == CONST_INT
+   && INTVAL (operands[1]) == -1"
 {
   operands[1] = constm1_rtx;
   return "or{q}\t{%1, %0|%0, %1}";
@@ -2485,8 +2490,8 @@
 (define_insn "*movdi_1_rex64"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!m*y,!*y,!*Y,!m,!*Y")
 	(match_operand:DI 1 "general_operand" "Z,rem,i,re,n,*y,m,*Y,*Y,*m"))]
-  "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
-   && TARGET_64BIT"
+  "TARGET_64BIT
+   && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
 {
   switch (get_attr_type (insn))
     {
@@ -3041,7 +3046,7 @@
 (define_insn "*pushxf_nointeger"
   [(set (match_operand:XF 0 "push_operand" "=X,X,X")
 	(match_operand:XF 1 "general_no_elim_operand" "f,Fo,*r"))]
-  "optimize_size && !TARGET_64BIT"
+  "!TARGET_64BIT && optimize_size"
 {
   switch (which_alternative)
     {
@@ -3097,7 +3102,7 @@
 (define_insn "*pushxf_integer"
   [(set (match_operand:XF 0 "push_operand" "=<,<")
 	(match_operand:XF 1 "general_no_elim_operand" "f#r,ro#f"))]
-  "!optimize_size && !TARGET_64BIT"
+  "!TARGET_64BIT && !optimize_size"
 {
   switch (which_alternative)
     {
@@ -3190,9 +3195,9 @@
 (define_insn "*movxf_nointeger"
   [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o")
 	(match_operand:XF 1 "general_operand" "fm,f,G,*roF,F*r"))]
-  "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
-   && !TARGET_64BIT
+  "!TARGET_64BIT
    && optimize_size
+   && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
    && (reload_in_progress || reload_completed
        || GET_CODE (operands[1]) != CONST_DOUBLE
        || memory_operand (operands[0], XFmode))" 
@@ -3283,9 +3288,9 @@
 (define_insn "*movxf_integer"
   [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
 	(match_operand:XF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
-  "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
-   && !TARGET_64BIT
+  "!TARGET_64BIT
    && !optimize_size
+   && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
    && (reload_in_progress || reload_completed
        || GET_CODE (operands[1]) != CONST_DOUBLE
        || memory_operand (operands[0], XFmode))" 
@@ -3654,7 +3659,7 @@
 (define_split
   [(set (match_operand:DI 0 "memory_operand" "")
      (zero_extend:DI (match_dup 0)))]
-  ""
+  "TARGET_64BIT"
   [(set (match_dup 4) (const_int 0))]
   "split_di (&operands[0], 1, &operands[3], &operands[4]);")
 
@@ -3662,8 +3667,8 @@
   [(set (match_operand:DI 0 "register_operand" "")
 	(zero_extend:DI (match_operand:SI 1 "register_operand" "")))
    (clobber (reg:CC 17))]
-  "reload_completed && true_regnum (operands[0]) == true_regnum (operands[1])
-   && !TARGET_64BIT"
+  "!TARGET_64BIT && reload_completed
+   && true_regnum (operands[0]) == true_regnum (operands[1])"
   [(set (match_dup 4) (const_int 0))]
   "split_di (&operands[0], 1, &operands[3], &operands[4]);")
 
@@ -3671,7 +3676,7 @@
   [(set (match_operand:DI 0 "nonimmediate_operand" "")
 	(zero_extend:DI (match_operand:SI 1 "general_operand" "")))
    (clobber (reg:CC 17))]
-  "reload_completed && !TARGET_64BIT"
+  "!TARGET_64BIT && reload_completed"
   [(set (match_dup 3) (match_dup 1))
    (set (match_dup 4) (const_int 0))]
   "split_di (&operands[0], 1, &operands[3], &operands[4]);")
@@ -3933,14 +3938,14 @@
 (define_split
   [(set (match_operand:DF 0 "push_operand" "")
 	(float_extend:DF (match_operand:SF 1 "register_operand" "")))]
-  "FP_REGNO_P (REGNO (operands[1])) && !TARGET_64BIT"
+  "!TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))"
   [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
    (set (mem:DF (reg:SI 7)) (float_extend:DF (match_dup 1)))])
 
 (define_split
   [(set (match_operand:DF 0 "push_operand" "")
 	(float_extend:DF (match_operand:SF 1 "register_operand" "")))]
-  "FP_REGNO_P (REGNO (operands[1])) && TARGET_64BIT"
+  "TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))"
   [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
    (set (mem:DF (reg:DI 7)) (float_extend:DF (match_dup 1)))])
 
@@ -3953,7 +3958,7 @@
 (define_split
   [(set (match_operand:XF 0 "push_operand" "")
 	(float_extend:XF (match_operand:SF 1 "register_operand" "")))]
-  "FP_REGNO_P (REGNO (operands[1])) && !TARGET_64BIT"
+  "!TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))"
   [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
    (set (mem:XF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
 
@@ -3966,14 +3971,14 @@
 (define_split
   [(set (match_operand:TF 0 "push_operand" "")
 	(float_extend:TF (match_operand:SF 1 "register_operand" "")))]
-  "FP_REGNO_P (REGNO (operands[1])) && !TARGET_64BIT"
+  "!TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))"
   [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
    (set (mem:TF (reg:SI 7)) (float_extend:TF (match_dup 1)))])
 
 (define_split
   [(set (match_operand:TF 0 "push_operand" "")
 	(float_extend:TF (match_operand:SF 1 "register_operand" "")))]
-  "FP_REGNO_P (REGNO (operands[1])) && TARGET_64BIT"
+  "TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))"
   [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
    (set (mem:DF (reg:DI 7)) (float_extend:TF (match_dup 1)))])
 
@@ -3986,7 +3991,7 @@
 (define_split
   [(set (match_operand:XF 0 "push_operand" "")
 	(float_extend:XF (match_operand:DF 1 "register_operand" "")))]
-  "FP_REGNO_P (REGNO (operands[1])) && !TARGET_64BIT"
+  "!TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))"
   [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
    (set (mem:DF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
 
@@ -3999,14 +4004,14 @@
 (define_split
   [(set (match_operand:TF 0 "push_operand" "")
 	(float_extend:TF (match_operand:DF 1 "register_operand" "")))]
-  "FP_REGNO_P (REGNO (operands[1])) && !TARGET_64BIT"
+  "!TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))"
   [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
    (set (mem:TF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
 
 (define_split
   [(set (match_operand:TF 0 "push_operand" "")
 	(float_extend:TF (match_operand:DF 1 "register_operand" "")))]
-  "FP_REGNO_P (REGNO (operands[1])) && TARGET_64BIT"
+  "TARGET_64BIT && FP_REGNO_P (REGNO (operands[1]))"
   [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
    (set (mem:TF (reg:DI 7)) (float_extend:TF (match_dup 1)))])
 
@@ -4064,7 +4069,7 @@
 (define_expand "extendsfxf2"
   [(set (match_operand:XF 0 "nonimmediate_operand" "")
         (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "")))]
-  "TARGET_80387 && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_80387"
 {
   if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
     operands[1] = force_reg (SFmode, operands[1]);
@@ -4073,7 +4078,7 @@
 (define_insn "*extendsfxf2_1"
   [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
         (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
-  "TARGET_80387 && !TARGET_64BIT
+  "!TARGET_64BIT && TARGET_80387
    && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
 {
   switch (which_alternative)
@@ -4146,7 +4151,7 @@
 (define_expand "extenddfxf2"
   [(set (match_operand:XF 0 "nonimmediate_operand" "")
         (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "")))]
-  "TARGET_80387 && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_80387"
 {
   if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
     operands[1] = force_reg (DFmode, operands[1]);
@@ -4155,7 +4160,7 @@
 (define_insn "*extenddfxf2_1"
   [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
         (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
-  "TARGET_80387 && !TARGET_64BIT
+  "!TARGET_64BIT && TARGET_80387
    && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
 {
   switch (which_alternative)
@@ -4372,7 +4377,7 @@
 		   (float_truncate:SF
 		    (match_operand:XF 1 "register_operand" "")))
 	      (clobber (match_dup 2))])]
-  "TARGET_80387 && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_80387"
   "operands[2] = assign_386_stack_local (SFmode, 0);")
 
 (define_insn "*truncxfsf2_1"
@@ -4380,7 +4385,7 @@
 	(float_truncate:SF
 	 (match_operand:XF 1 "register_operand" "f,f,f,f")))
    (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
-  "TARGET_80387 && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_80387"
 {
   switch (which_alternative)
     {
@@ -4400,7 +4405,7 @@
   [(set (match_operand:SF 0 "memory_operand" "=m")
 	(float_truncate:SF
 	 (match_operand:XF 1 "register_operand" "f")))]
-  "TARGET_80387 && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_80387"
 {
   if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
     return "fstp%z0\t%y0";
@@ -4497,7 +4502,7 @@
 		   (float_truncate:DF
 		    (match_operand:XF 1 "register_operand" "")))
 	      (clobber (match_dup 2))])]
-  "TARGET_80387 && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_80387"
   "operands[2] = assign_386_stack_local (DFmode, 0);")
 
 (define_insn "*truncxfdf2_1"
@@ -4505,7 +4510,7 @@
 	(float_truncate:DF
 	 (match_operand:XF 1 "register_operand" "f,f,f,f")))
    (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
-  "TARGET_80387 && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_80387"
 {
   switch (which_alternative)
     {
@@ -4526,7 +4531,7 @@
   [(set (match_operand:DF 0 "memory_operand" "=m")
 	(float_truncate:DF
 	  (match_operand:XF 1 "register_operand" "f")))]
-  "TARGET_80387 && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_80387"
 {
   if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
     return "fstp%z0\t%y0";
@@ -4626,7 +4631,7 @@
 (define_expand "fix_truncxfdi2"
   [(set (match_operand:DI 0 "nonimmediate_operand" "")
         (fix:DI (match_operand:XF 1 "register_operand" "")))]
-  "TARGET_80387 && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_80387"
   "")
 
 (define_expand "fix_trunctfdi2"
@@ -4640,7 +4645,7 @@
         (fix:DI (match_operand:DF 1 "register_operand" "")))]
   "TARGET_80387 || (TARGET_SSE2 && TARGET_64BIT)"
 {
-  if (TARGET_SSE2 && TARGET_64BIT)
+  if (TARGET_64BIT && TARGET_SSE2)
    {
      rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
      emit_insn (gen_fix_truncdfdi_sse (out, operands[1]));
@@ -4749,14 +4754,14 @@
 (define_insn "fix_truncsfdi_sse"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(fix:DI (match_operand:SF 1 "nonimmediate_operand" "xm")))]
-  "TARGET_SSE && TARGET_64BIT"
+  "TARGET_64BIT && TARGET_SSE"
   "cvttss2si{q}\t{%1, %0|%0, %1}"
   [(set_attr "type" "sse")])
 
 (define_insn "fix_truncdfdi_sse"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(fix:DI (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
-  "TARGET_SSE2 && TARGET_64BIT"
+  "TARGET_64BIT && TARGET_SSE2"
   "cvttsd2si{q}\t{%1, %0|%0, %1}"
   [(set_attr "type" "sse")])
 
@@ -4765,7 +4770,7 @@
 (define_expand "fix_truncxfsi2"
   [(set (match_operand:SI 0 "nonimmediate_operand" "")
 	(fix:SI (match_operand:XF 1 "register_operand" "")))]
-  "TARGET_80387 && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_80387"
   "")
 
 (define_expand "fix_trunctfsi2"
@@ -4898,7 +4903,7 @@
 (define_expand "fix_truncxfhi2"
   [(set (match_operand:HI 0 "nonimmediate_operand" "")
         (fix:HI (match_operand:XF 1 "register_operand" "")))]
-  "TARGET_80387 && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_80387"
   "")
 
 (define_expand "fix_trunctfhi2"
@@ -5062,7 +5067,7 @@
 (define_expand "floatdisf2"
   [(set (match_operand:SF 0 "register_operand" "")
 	(float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
-  "(TARGET_SSE && TARGET_64BIT) || TARGET_80387"
+  "(TARGET_64BIT && TARGET_SSE) || TARGET_80387"
   "")
 
 (define_insn "*floatdisf2_i387_only"
@@ -5079,7 +5084,7 @@
 (define_insn "*floatdisf2_i387"
   [(set (match_operand:SF 0 "register_operand" "=f,?f,x")
 	(float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,mr")))]
-  "TARGET_80387 && TARGET_64BIT && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
+  "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
   "@
    fild%z1\t%1
    #
@@ -5091,7 +5096,7 @@
 (define_insn "*floatdisf2_sse"
   [(set (match_operand:SF 0 "register_operand" "=x")
 	(float:SF (match_operand:DI 1 "nonimmediate_operand" "mr")))]
-  "TARGET_SSE && TARGET_64BIT"
+  "TARGET_64BIT && TARGET_SSE"
   "cvtsi2ss{q}\t{%1, %0|%0, %1}"
   [(set_attr "type" "sse")
    (set_attr "mode" "SF")
@@ -5138,7 +5143,7 @@
 (define_expand "floatdidf2"
   [(set (match_operand:DF 0 "register_operand" "")
 	(float:DF (match_operand:DI 1 "nonimmediate_operand" "")))]
-  "TARGET_80387 || (TARGET_SSE2 && TARGET_64BIT)"
+  "(TARGET_64BIT && TARGET_SSE2) || TARGET_80387"
   "")
 
 (define_insn "*floatdidf2_i387_only"
@@ -5155,7 +5160,7 @@
 (define_insn "*floatdidf2_i387"
   [(set (match_operand:DF 0 "register_operand" "=f,?f,Y")
 	(float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,mr")))]
-  "TARGET_80387 && TARGET_64BIT && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
+  "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
   "@
    fild%z1\t%1
    #
@@ -5176,7 +5181,7 @@
 (define_insn "floathixf2"
   [(set (match_operand:XF 0 "register_operand" "=f,f")
 	(float:XF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
-  "TARGET_80387 && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_80387"
   "@
    fild%z1\t%1
    #"
@@ -5198,7 +5203,7 @@
 (define_insn "floatsixf2"
   [(set (match_operand:XF 0 "register_operand" "=f,f")
 	(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
-  "TARGET_80387 && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_80387"
   "@
    fild%z1\t%1
    #"
@@ -5220,7 +5225,7 @@
 (define_insn "floatdixf2"
   [(set (match_operand:XF 0 "register_operand" "=f,f")
 	(float:XF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
-  "TARGET_80387 && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_80387"
   "@
    fild%z1\t%1
    #"
@@ -5282,7 +5287,7 @@
 	(plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
 		 (match_operand:DI 2 "general_operand" "")))
    (clobber (reg:CC 17))]
-  "reload_completed && !TARGET_64BIT"
+  "!TARGET_64BIT && reload_completed"
   [(parallel [(set (reg:CC 17) (unspec:CC [(match_dup 1) (match_dup 2)] 12))
 	      (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
    (parallel [(set (match_dup 3)
@@ -5300,7 +5305,7 @@
 			    (match_operand:DI 1 "nonimmediate_operand" "%0,0"))
 		   (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
    (clobber (reg:CC 17))]
-  "ix86_binary_operator_ok (PLUS, DImode, operands)"
+  "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
   "adc{q}\t{%2, %0|%0, %2}"
   [(set_attr "type" "alu")
    (set_attr "pent_pair" "pu")
@@ -5625,7 +5630,7 @@
 	(plus:DI (match_operand:DI 1 "register_operand" "")
 		 (match_operand:DI 2 "x86_64_nonmemory_operand" "")))
    (clobber (reg:CC 17))]
-  "reload_completed && TARGET_64BIT
+  "TARGET_64BIT && reload_completed
    && true_regnum (operands[0]) != true_regnum (operands[1])"
   [(set (match_dup 0)
 	(plus:DI (match_dup 1)
@@ -6862,7 +6867,7 @@
   [(set (match_operand:XF 0 "register_operand" "")
 	(plus:XF (match_operand:XF 1 "register_operand" "")
 		 (match_operand:XF 2 "register_operand" "")))]
-  "TARGET_80387 && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_80387"
   "")
 
 (define_expand "addtf3"
@@ -6911,7 +6916,7 @@
 	(minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
 		  (match_operand:DI 2 "general_operand" "")))
    (clobber (reg:CC 17))]
-  "reload_completed && !TARGET_64BIT"
+  "!TARGET_64BIT && reload_completed"
   [(parallel [(set (reg:CC 17) (compare:CC (match_dup 1) (match_dup 2)))
 	      (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
    (parallel [(set (match_dup 3)
@@ -6929,7 +6934,7 @@
 	    (plus:DI (ltu:DI (reg:CC 17) (const_int 0))
 	       (match_operand:DI 2 "x86_64_general_operand" "re,rm"))))
    (clobber (reg:CC 17))]
-  "ix86_binary_operator_ok (MINUS, DImode, operands)"
+  "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
   "sbb{q}\t{%2, %0|%0, %2}"
   [(set_attr "type" "alu")
    (set_attr "pent_pair" "pu")
@@ -7179,7 +7184,7 @@
   [(set (match_operand:XF 0 "register_operand" "")
 	(minus:XF (match_operand:XF 1 "register_operand" "")
 		  (match_operand:XF 2 "register_operand" "")))]
-  "TARGET_80387 && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_80387"
   "")
 
 (define_expand "subtf3"
@@ -7218,8 +7223,8 @@
 	(mult:DI (match_operand:DI 1 "nonimmediate_operand" "%rm,0,0")
 		 (match_operand:DI 2 "x86_64_general_operand" "K,e,mr")))
    (clobber (reg:CC 17))]
-  "(GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
-   && TARGET_64BIT"
+  "TARGET_64BIT
+   && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
   "@
    imul{q}\t{%2, %1, %0|%0, %1, %2}
    imul{q}\t{%2, %1, %0|%0, %1, %2}
@@ -7505,7 +7510,7 @@
   [(set (match_operand:XF 0 "register_operand" "")
 	(mult:XF (match_operand:XF 1 "register_operand" "")
 		 (match_operand:XF 2 "register_operand" "")))]
-  "TARGET_80387 && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_80387"
   "")
 
 (define_expand "multf3"
@@ -7559,7 +7564,7 @@
   [(set (match_operand:XF 0 "register_operand" "")
 	(div:XF (match_operand:XF 1 "register_operand" "")
 		(match_operand:XF 2 "register_operand" "")))]
-  "TARGET_80387 && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_80387"
   "")
 
 (define_expand "divtf3"
@@ -7801,7 +7806,7 @@
    (set (match_operand:DI 3 "register_operand" "")
 	(umod:DI (match_dup 1) (match_dup 2)))
    (clobber (reg:CC 17))]
-  "reload_completed && TARGET_64BIT"
+  "TARGET_64BIT && reload_completed"
   [(set (match_dup 3) (const_int 0))
    (parallel [(set (match_dup 0)
 		   (udiv:DI (match_dup 1) (match_dup 2)))
@@ -8090,8 +8095,8 @@
 		   (match_operand:DI 1 "const_int_operand" "")
 		   (match_operand:DI 2 "const_int_operand" ""))
 		 (const_int 0)))]
-  "ix86_match_ccmode (insn, CCNOmode)
-   && TARGET_64BIT
+  "TARGET_64BIT
+   && ix86_match_ccmode (insn, CCNOmode)
    && (GET_MODE (operands[0]) == SImode
        || GET_MODE (operands[0]) == DImode
        || GET_MODE (operands[0]) == HImode
@@ -9153,8 +9158,7 @@
   [(set (match_operand:DI 0 "nonimmediate_operand" "")
 	(neg:DI (match_operand:DI 1 "general_operand" "")))
    (clobber (reg:CC 17))]
-  "reload_completed
-   && !TARGET_64BIT"
+  "!TARGET_64BIT && reload_completed"
   [(parallel
     [(set (reg:CCZ 17)
 	  (compare:CCZ (neg:SI (match_dup 2)) (const_int 0)))
@@ -9497,7 +9501,7 @@
 	(neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0")))
    (use (match_operand:DF 2 "nonmemory_operand" "Y,0,*g#Y,*g#Y"))
    (clobber (reg:CC 17))]
-  "TARGET_SSE2 && !TARGET_64BIT
+  "!TARGET_64BIT && TARGET_SSE2
    && (reload_in_progress || reload_completed
        || (register_operand (operands[0], VOIDmode)
 	   && register_operand (operands[1], VOIDmode)))"
@@ -9508,7 +9512,7 @@
 	(neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0")))
    (use (match_operand:DF 2 "general_operand" "Y,0,*g#Yr,*rm"))
    (clobber (reg:CC 17))]
-  "TARGET_SSE2 && TARGET_64BIT
+  "TARGET_64BIT && TARGET_SSE2
    && (reload_in_progress || reload_completed
        || (register_operand (operands[0], VOIDmode)
 	   && register_operand (operands[1], VOIDmode)))"
@@ -9540,7 +9544,7 @@
 	(neg:DF (match_operand:DF 1 "register_operand" "")))
    (use (match_operand:DF 2 "" ""))
    (clobber (reg:CC 17))]
-  "reload_completed && GENERAL_REG_P (operands[0]) && TARGET_64BIT"
+  "TARGET_64BIT && reload_completed && GENERAL_REG_P (operands[0])"
   [(parallel [(set (match_dup 0)
 		   (xor:DI (match_dup 1) (match_dup 2)))
 	      (clobber (reg:CC 17))])]
@@ -9574,7 +9578,7 @@
   [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
 	(neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
    (clobber (reg:CC 17))]
-  "TARGET_80387 && !TARGET_64BIT
+  "!TARGET_64BIT && TARGET_80387
    && ix86_unary_operator_ok (NEG, DFmode, operands)"
   "#")
 
@@ -9586,7 +9590,7 @@
   [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
 	(neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
    (clobber (reg:CC 17))]
-  "TARGET_80387 && TARGET_64BIT
+  "TARGET_64BIT && TARGET_80387
    && ix86_unary_operator_ok (NEG, DFmode, operands)"
   "#")
 
@@ -9603,8 +9607,8 @@
   [(set (match_operand:DF 0 "register_operand" "")
 	(neg:DF (match_operand:DF 1 "register_operand" "")))
    (clobber (reg:CC 17))]
-  "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))
-   && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_80387 && reload_completed
+   && !FP_REGNO_P (REGNO (operands[0]))"
   [(parallel [(set (match_dup 3) (xor:SI (match_dup 3) (match_dup 4)))
 	      (clobber (reg:CC 17))])]
   "operands[4] = GEN_INT (trunc_int_for_mode (0x80000000, SImode));
@@ -9614,7 +9618,7 @@
   [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
 		   (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
 	      (clobber (reg:CC 17))])]
-  "TARGET_80387 && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_80387"
   "ix86_expand_unary_operator (NEG, XFmode, operands); DONE;")
 
 (define_expand "negtf2"
@@ -9631,7 +9635,7 @@
   [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
 	(neg:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
    (clobber (reg:CC 17))]
-  "TARGET_80387 && !TARGET_64BIT
+  "!TARGET_64BIT && TARGET_80387
    && ix86_unary_operator_ok (NEG, XFmode, operands)"
   "#")
 
@@ -9719,7 +9723,7 @@
 (define_insn "*negxf2_1"
   [(set (match_operand:XF 0 "register_operand" "=f")
 	(neg:XF (match_operand:XF 1 "register_operand" "0")))]
-  "TARGET_80387 && !TARGET_64BIT && reload_completed"
+  "!TARGET_64BIT && TARGET_80387 && reload_completed"
   "fchs"
   [(set_attr "type" "fsgn")
    (set_attr "mode" "XF")
@@ -9729,7 +9733,7 @@
   [(set (match_operand:XF 0 "register_operand" "=f")
 	(neg:XF (float_extend:XF
 		  (match_operand:DF 1 "register_operand" "0"))))]
-  "TARGET_80387 && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_80387"
   "fchs"
   [(set_attr "type" "fsgn")
    (set_attr "mode" "XF")
@@ -9739,7 +9743,7 @@
   [(set (match_operand:XF 0 "register_operand" "=f")
 	(neg:XF (float_extend:XF
 		  (match_operand:SF 1 "register_operand" "0"))))]
-  "TARGET_80387 && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_80387"
   "fchs"
   [(set_attr "type" "fsgn")
    (set_attr "mode" "XF")
@@ -9949,7 +9953,7 @@
 	(abs:DF (match_operand:DF 1 "nonimmediate_operand" "Y,0,0")))
    (use (match_operand:DF 2 "nonmemory_operand" "*0#Y,*g#Y,*g#Y"))
    (clobber (reg:CC 17))]
-  "TARGET_SSE2 && !TARGET_64BIT
+  "!TARGET_64BIT && TARGET_SSE2
    && (reload_in_progress || reload_completed
        || (register_operand (operands[0], VOIDmode)
 	   && register_operand (operands[1], VOIDmode)))"
@@ -9960,7 +9964,7 @@
 	(abs:DF (match_operand:DF 1 "nonimmediate_operand" "Y,0")))
    (use (match_operand:DF 2 "nonmemory_operand" "*0#Y,*g#Y"))
    (clobber (reg:CC 17))]
-  "TARGET_SSE2 && TARGET_64BIT
+  "TARGET_64BIT && TARGET_SSE2
    && (reload_in_progress || reload_completed
        || (register_operand (operands[0], VOIDmode)
 	   && register_operand (operands[1], VOIDmode)))"
@@ -10004,7 +10008,7 @@
   [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
 	(abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
    (clobber (reg:CC 17))]
-  "TARGET_80387 && !TARGET_64BIT
+  "!TARGET_64BIT && TARGET_80387
    && ix86_unary_operator_ok (ABS, DFmode, operands)"
   "#")
 
@@ -10016,7 +10020,7 @@
   [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
 	(abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
    (clobber (reg:CC 17))]
-  "TARGET_80387 && TARGET_64BIT
+  "TARGET_64BIT && TARGET_80387
    && ix86_unary_operator_ok (ABS, DFmode, operands)"
   "#")
 
@@ -10033,8 +10037,8 @@
   [(set (match_operand:DF 0 "register_operand" "")
 	(abs:DF (match_operand:DF 1 "register_operand" "")))
    (clobber (reg:CC 17))]
-  "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))
-   && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_80387 && reload_completed &&
+   !FP_REGNO_P (REGNO (operands[0]))"
   [(parallel [(set (match_dup 3) (and:SI (match_dup 3) (match_dup 4)))
 	      (clobber (reg:CC 17))])]
   "operands[4] = GEN_INT (trunc_int_for_mode (~0x80000000, SImode));
@@ -10044,7 +10048,7 @@
   [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
 		   (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
 	      (clobber (reg:CC 17))])]
-  "TARGET_80387 && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_80387"
   "ix86_expand_unary_operator (ABS, XFmode, operands); DONE;")
 
 (define_expand "abstf2"
@@ -10061,7 +10065,7 @@
   [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
 	(abs:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
    (clobber (reg:CC 17))]
-  "TARGET_80387 && !TARGET_64BIT
+  "!TARGET_64BIT && TARGET_80387
    && ix86_unary_operator_ok (ABS, XFmode, operands)"
   "#")
 
@@ -10140,7 +10144,7 @@
 (define_insn "*absxf2_1"
   [(set (match_operand:XF 0 "register_operand" "=f")
 	(abs:XF (match_operand:XF 1 "register_operand" "0")))]
-  "TARGET_80387 && !TARGET_64BIT && reload_completed"
+  "!TARGET_64BIT && TARGET_80387 && reload_completed"
   "fabs"
   [(set_attr "type" "fsgn")
    (set_attr "mode" "DF")])
@@ -10149,7 +10153,7 @@
   [(set (match_operand:XF 0 "register_operand" "=f")
 	(abs:XF (float_extend:XF
 	  (match_operand:DF 1 "register_operand" "0"))))]
-  "TARGET_80387 && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_80387"
   "fabs"
   [(set_attr "type" "fsgn")
    (set_attr "mode" "XF")])
@@ -10158,7 +10162,7 @@
   [(set (match_operand:XF 0 "register_operand" "=f")
 	(abs:XF (float_extend:XF
 	  (match_operand:SF 1 "register_operand" "0"))))]
-  "TARGET_80387 && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_80387"
   "fabs"
   [(set_attr "type" "fsgn")
    (set_attr "mode" "XF")])
@@ -10483,8 +10487,7 @@
 	(ashift:DI (match_operand:DI 1 "register_operand" "")
 		   (match_operand:QI 2 "immediate_operand" "")))
    (clobber (reg:CC 17))]
-  "reload_completed
-   && TARGET_64BIT
+  "TARGET_64BIT && reload_completed
    && true_regnum (operands[0]) != true_regnum (operands[1])"
   [(set (match_dup 0)
 	(mult:DI (match_dup 1)
@@ -10711,7 +10714,7 @@
 	(zero_extend:DI (ashift:SI (match_operand:SI 1 "register_operand" "0,r")
 			(match_operand:QI 2 "nonmemory_operand" "cI,M"))))
    (clobber (reg:CC 17))]
-  "ix86_binary_operator_ok (ASHIFT, SImode, operands) && TARGET_64BIT"
+  "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
 {
   switch (get_attr_type (insn))
     {
@@ -11333,8 +11336,9 @@
 	(zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0")
 				     (match_operand:SI 2 "const_int_operand" "i,i"))))
    (clobber (reg:CC 17))]
-  "INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_size)
-   && TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
+  "TARGET_64BIT && (TARGET_USE_CLTD || optimize_size)
+   && INTVAL (operands[2]) == 31
+   && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
   "@
    {cltd|cdq}
    sar{l}\t{%2, %k0|%k0, %2}"
@@ -13042,7 +13046,7 @@
    (use (match_operand 2 "" ""))        ; max iterations
    (use (match_operand 3 "" ""))        ; loop level 
    (use (match_operand 4 "" ""))]       ; label
-  "TARGET_USE_LOOP && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_USE_LOOP"
   "                                 
 {
   /* Only use cloop on innermost loops.  */
@@ -13066,7 +13070,7 @@
 		 (const_int -1)))
    (clobber (match_scratch:SI 3 "=X,X,r"))
    (clobber (reg:CC 17))]
-  "TARGET_USE_LOOP && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_USE_LOOP"
 {
   if (which_alternative != 0)
     return "#";
@@ -13096,7 +13100,7 @@
 		 (const_int -1)))
    (clobber (match_scratch:SI 2 ""))
    (clobber (reg:CC 17))]
-  "TARGET_USE_LOOP && !TARGET_64BIT
+  "!TARGET_64BIT && TARGET_USE_LOOP
    && reload_completed
    && REGNO (operands[1]) != 2"
   [(parallel [(set (reg:CCZ 17)
@@ -13119,7 +13123,7 @@
 		 (const_int -1)))
    (clobber (match_scratch:SI 3 ""))
    (clobber (reg:CC 17))]
-  "TARGET_USE_LOOP && !TARGET_64BIT
+  "!TARGET_64BIT && TARGET_USE_LOOP
    && reload_completed
    && (! REG_P (operands[2])
        || ! rtx_equal_p (operands[1], operands[2]))"
@@ -13550,7 +13554,7 @@
 
 (define_insn_and_split "eh_return_si"
   [(unspec_volatile [(match_operand:SI 0 "register_operand" "c")] 13)]
-  ""
+  "!TARGET_64BIT"
   "#"
   "reload_completed"
   [(const_int 1)]
@@ -13558,7 +13562,7 @@
 
 (define_insn_and_split "eh_return_di"
   [(unspec_volatile [(match_operand:DI 0 "register_operand" "c")] 13)]
-  ""
+  "TARGET_64BIT"
   "#"
   "reload_completed"
   [(const_int 1)]
@@ -13758,7 +13762,7 @@
 	(match_operator:XF 3 "binary_fp_operator"
 			[(match_operand:XF 1 "register_operand" "%0")
 			 (match_operand:XF 2 "register_operand" "f")]))]
-  "TARGET_80387 && !TARGET_64BIT
+  "!TARGET_64BIT && TARGET_80387
    && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
   "* return output_387_binary_op (insn, operands);"
   [(set (attr "type") 
@@ -13954,7 +13958,7 @@
 	(match_operator:XF 3 "binary_fp_operator"
 			[(match_operand:XF 1 "register_operand" "0,f")
 			 (match_operand:XF 2 "register_operand" "f,0")]))]
-  "TARGET_80387 && !TARGET_64BIT
+  "!TARGET_64BIT && TARGET_80387
    && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
   "* return output_387_binary_op (insn, operands);"
   [(set (attr "type") 
@@ -13988,7 +13992,7 @@
 	(match_operator:XF 3 "binary_fp_operator"
 	   [(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
 	    (match_operand:XF 2 "register_operand" "0,0")]))]
-  "TARGET_80387 && !TARGET_64BIT && TARGET_USE_FIOP"
+  "!TARGET_64BIT && TARGET_80387 && TARGET_USE_FIOP"
   "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
   [(set (attr "type") 
         (cond [(match_operand:XF 3 "mult_operator" "") 
@@ -14024,7 +14028,7 @@
 	(match_operator:XF 3 "binary_fp_operator"
 	  [(match_operand:XF 1 "register_operand" "0,0")
 	   (float:XF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
-  "TARGET_80387 && !TARGET_64BIT && TARGET_USE_FIOP"
+  "!TARGET_64BIT && TARGET_80387 && TARGET_USE_FIOP"
   "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
   [(set (attr "type") 
         (cond [(match_operand:XF 3 "mult_operator" "") 
@@ -14060,7 +14064,7 @@
 	(match_operator:XF 3 "binary_fp_operator"
 	   [(float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
 	    (match_operand:XF 2 "register_operand" "0,f")]))]
-  "TARGET_80387 && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_80387"
   "* return output_387_binary_op (insn, operands);"
   [(set (attr "type") 
         (cond [(match_operand:XF 3 "mult_operator" "") 
@@ -14093,7 +14097,7 @@
 	  [(match_operand:XF 1 "register_operand" "0,f")
 	   (float_extend:XF
 	    (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
-  "TARGET_80387 && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_80387"
   "* return output_387_binary_op (insn, operands);"
   [(set (attr "type") 
         (cond [(match_operand:XF 3 "mult_operator" "") 
@@ -14126,7 +14130,7 @@
 	(match_operator:XF 3 "binary_fp_operator"
 	   [(float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,0"))
 	    (match_operand:XF 2 "register_operand" "0,f")]))]
-  "TARGET_80387 && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_80387"
   "* return output_387_binary_op (insn, operands);"
   [(set (attr "type") 
         (cond [(match_operand:XF 3 "mult_operator" "") 
@@ -14159,7 +14163,7 @@
 	  [(match_operand:XF 1 "register_operand" "0,f")
 	   (float_extend:XF
 	    (match_operand:DF 2 "nonimmediate_operand" "fm,0"))]))]
-  "TARGET_80387 && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_80387"
   "* return output_387_binary_op (insn, operands);"
   [(set (attr "type") 
         (cond [(match_operand:XF 3 "mult_operator" "") 
@@ -14322,7 +14326,7 @@
 (define_insn "sqrtxf2"
   [(set (match_operand:XF 0 "register_operand" "=f")
 	(sqrt:XF (match_operand:XF 1 "register_operand" "0")))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_64BIT
+  "!TARGET_64BIT && TARGET_80387 && !TARGET_NO_FANCY_MATH_387 
    && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
   "fsqrt"
   [(set_attr "type" "fpspc")
@@ -14343,7 +14347,7 @@
   [(set (match_operand:XF 0 "register_operand" "=f")
 	(sqrt:XF (float_extend:XF
 		  (match_operand:DF 1 "register_operand" "0"))))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_80387 && TARGET_NO_FANCY_MATH_387"
   "fsqrt"
   [(set_attr "type" "fpspc")
    (set_attr "mode" "XF")
@@ -14363,7 +14367,7 @@
   [(set (match_operand:XF 0 "register_operand" "=f")
 	(sqrt:XF (float_extend:XF
 		  (match_operand:SF 1 "register_operand" "0"))))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_80387 && TARGET_NO_FANCY_MATH_387"
   "fsqrt"
   [(set_attr "type" "fpspc")
    (set_attr "mode" "XF")
@@ -14410,7 +14414,7 @@
 (define_insn "sinxf2"
   [(set (match_operand:XF 0 "register_operand" "=f")
 	(unspec:XF [(match_operand:XF 1 "register_operand" "0")] 1))]
-  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_64BIT
+  "!TARGET_64BIT && TARGET_80387 && TARGET_NO_FANCY_MATH_387
    && flag_unsafe_math_optimizations"
   "fsin"
   [(set_attr "type" "fpspc")
@@ -14659,7 +14663,7 @@
 	      (clobber (reg:CC 17))])
    (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 1)))
 	      (clobber (reg:CC 17))])]
-  "!TARGET_64BIT"
+  "TARGET_64BIT"
 {
   if (TARGET_SINGLE_STRINGOP || optimize_size)
     {
@@ -15637,7 +15641,7 @@
 				[(reg 17) (const_int 0)])
 		      (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0")
 		      (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))]
-  "TARGET_CMOVE && !TARGET_64BIT
+  "!TARGET_64BIT && TARGET_CMOVE
    && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
   "@
    fcmov%F1\t{%2, %0|%0, %2}
@@ -15653,7 +15657,7 @@
 				[(reg 17) (const_int 0)])
 		      (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0")
 		      (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))]
-  "TARGET_CMOVE && TARGET_64BIT
+  "TARGET_64BIT && TARGET_CMOVE
    && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
   "@
    fcmov%F1\t{%2, %0|%0, %2}
@@ -15669,7 +15673,7 @@
 				[(match_operand 4 "" "") (const_int 0)])
 		      (match_operand:DF 2 "nonimmediate_operand" "")
 		      (match_operand:DF 3 "nonimmediate_operand" "")))]
-  "!ANY_FP_REG_P (operands[0]) && reload_completed && !TARGET_64BIT"
+  "!TARGET_64BIT && !ANY_FP_REG_P (operands[0]) && reload_completed"
   [(set (match_dup 2)
 	(if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
 		      (match_dup 5)
@@ -15687,7 +15691,7 @@
 	(if_then_else:XF (match_operand 1 "comparison_operator" "")
 			 (match_operand:XF 2 "register_operand" "")
 			 (match_operand:XF 3 "register_operand" "")))]
-  "TARGET_CMOVE && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_CMOVE"
   "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
 
 (define_expand "movtfcc"
@@ -15704,7 +15708,7 @@
 				[(reg 17) (const_int 0)])
 		      (match_operand:XF 2 "register_operand" "f,0")
 		      (match_operand:XF 3 "register_operand" "0,f")))]
-  "TARGET_CMOVE && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_CMOVE"
   "@
    fcmov%F1\t{%2, %0|%0, %2}
    fcmov%f1\t{%3, %0|%0, %3}"
@@ -16405,7 +16409,7 @@
    (set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 0)))
    (clobber (match_dup 0))
    (clobber (reg:CC 17))]
-  "TARGET_STACK_PROBE && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_STACK_PROBE"
   "call\t__alloca"
   [(set_attr "type" "multi")
    (set_attr "length" "5")])
@@ -16415,7 +16419,7 @@
    (set (reg:DI 7) (minus:DI (reg:DI 7) (match_dup 0)))
    (clobber (match_dup 0))
    (clobber (reg:CC 17))]
-  "TARGET_STACK_PROBE && TARGET_64BIT"
+  "TARGET_64BIT && TARGET_STACK_PROBE"
   "call\t__alloca"
   [(set_attr "type" "multi")
    (set_attr "length" "5")])
@@ -16446,7 +16450,7 @@
 
 (define_expand "builtin_setjmp_receiver"
   [(label_ref (match_operand 0 "" ""))]
-  "flag_pic && !TARGET_64BIT"
+  "!TARGET_64BIT && flag_pic"
 {
   load_pic_register ();
   DONE;
diff --git a/gcc/gencodes.c b/gcc/gencodes.c
index 7e4f9644263..2610a12325f 100644
--- a/gcc/gencodes.c
+++ b/gcc/gencodes.c
@@ -28,12 +28,9 @@ Boston, MA 02111-1307, USA.  */
 #include "errors.h"
 #include "gensupport.h"
 
-
 static int insn_code_number;
 
 static void gen_insn PARAMS ((rtx));
-static void output_predicate_decls PARAMS ((void));
-static int print_md_constant PARAMS ((void **, void *));
 
 static void
 gen_insn (insn)
@@ -47,30 +44,6 @@ gen_insn (insn)
 	    insn_code_number);
 }
 
-/* Print out declarations for all predicates mentioned in
-   PREDICATE_CODES.  */
-
-static void
-output_predicate_decls ()
-{
-#ifdef PREDICATE_CODES
-  static struct {
-    const char *name;
-    RTX_CODE codes[NUM_RTX_CODE];
-  } predicate[] = {
-    PREDICATE_CODES
-  };
-  size_t i;
-
-  putc ('\n', stdout);
-  puts ("struct rtx_def;\n#include \"machmode.h\"\n");
-  for (i = 0; i < sizeof predicate / sizeof *predicate; i++)
-    printf ("extern int %s PARAMS ((struct rtx_def *, enum machine_mode));\n",
-	    predicate[i].name);
-  putc ('\n', stdout);
-#endif
-}
-
 extern int main PARAMS ((int, char **));
 
 int
@@ -114,10 +87,6 @@ main (argc, argv)
 
   printf ("\n#define MAX_INSN_CODE ((int) CODE_FOR_nothing)\n\n");
 
-  traverse_md_constants (print_md_constant, stdout);
-
-  output_predicate_decls ();
-
   puts("\n#endif /* GCC_INSN_CODES_H */");
 
   if (ferror (stdout) || fflush (stdout) || fclose (stdout))
@@ -134,18 +103,3 @@ get_insn_name (code)
 {
   return NULL;
 }
-
-/* Called via traverse_md_constants; emit a #define for
-   the current constant definition.  */
-
-static int
-print_md_constant (slot, info)
-     void **slot;
-     void *info;
-{
-  struct md_constant *def = *slot;
-  FILE *file = info;
-
-  fprintf (file, "#define %s %s\n", def->name, def->value);
-  return 1;
-}
diff --git a/gcc/genconstants.c b/gcc/genconstants.c
new file mode 100644
index 00000000000..69d62cba6a2
--- /dev/null
+++ b/gcc/genconstants.c
@@ -0,0 +1,89 @@
+/* Generate from machine description:
+   a series of #define statements, one for each constant named in
+   a (define_constants ...) pattern.
+
+   Copyright (C) 1987, 1991, 1995, 1998,
+   1999, 2000, 2001 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* This program does not use gensupport.c because it does not need to
+   look at insn patterns, only (define_constants), and we want to
+   minimize dependencies.  */
+
+#include "hconfig.h"
+#include "system.h"
+#include "rtl.h"
+#include "errors.h"
+#include "gensupport.h"
+
+static int print_md_constant PARAMS ((void **, void *));
+extern int main PARAMS ((int, char **));
+
+/* Called via traverse_md_constants; emit a #define for
+   the current constant definition.  */
+
+static int
+print_md_constant (slot, info)
+     void **slot;
+     void *info;
+{
+  struct md_constant *def = *slot;
+  FILE *file = info;
+
+  fprintf (file, "#define %s %s\n", def->name, def->value);
+  return 1;
+}
+
+int
+main (argc, argv)
+     int argc;
+     char **argv;
+{
+  int dummy1, dummy2;
+  rtx desc;
+
+  progname = "genconstants";
+
+  if (argc <= 1)
+    fatal ("No input file name.");
+
+  if (init_md_reader (argv[1]) != SUCCESS_EXIT_CODE)
+    return (FATAL_EXIT_CODE);
+
+  /* Scan and discard the entire file.  This has the side effect
+     of loading up the constants table that we wish to scan.  */
+  do
+    desc = read_md_rtx (&dummy1, &dummy2);
+  while (desc);
+
+  puts ("/* Generated automatically by the program `genconstants'");
+  puts ("   from the machine description file `md'.  */\n");
+  puts ("#ifndef GCC_INSN_CONSTANTS_H");
+  puts ("#define GCC_INSN_CONSTANTS_H\n");
+
+  traverse_md_constants (print_md_constant, stdout);
+
+  puts ("\n#endif /* GCC_INSN_CONSTANTS_H */");
+
+  if (ferror (stdout) || fflush (stdout) || fclose (stdout))
+    return FATAL_EXIT_CODE;
+
+  return SUCCESS_EXIT_CODE;
+}
+
diff --git a/gcc/genpreds.c b/gcc/genpreds.c
new file mode 100644
index 00000000000..decf67a3918
--- /dev/null
+++ b/gcc/genpreds.c
@@ -0,0 +1,68 @@
+/* Generate from machine description:
+   - some macros CODE_FOR_... giving the insn_code_number value
+   for each of the defined standard insn names.
+   Copyright (C) 1987, 1991, 1995, 1998,
+   1999, 2000, 2001 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#include "hconfig.h"
+#include "system.h"
+
+#define NO_GENRTL_H
+#include "rtl.h"
+
+static void output_predicate_decls PARAMS ((void));
+extern int main PARAMS ((void));
+
+static void
+output_predicate_decls ()
+{
+#ifdef PREDICATE_CODES
+  static struct {
+    const char *name;
+    RTX_CODE codes[NUM_RTX_CODE];
+  } predicate[] = {
+    PREDICATE_CODES
+  };
+  size_t i;
+
+  puts ("#ifdef RTX_CODE\n");
+  for (i = 0; i < sizeof predicate / sizeof *predicate; i++)
+    printf ("extern int %s PARAMS ((rtx, enum machine_mode));\n",
+	    predicate[i].name);
+  puts ("\n#endif /* RTX_CODE */\n");
+#endif
+}
+
+int
+main ()
+{
+  puts ("/* Generated automatically by the program `genpreds'.  */\n");
+  puts ("#ifndef GCC_TM_PREDS_H");
+  puts ("#define GCC_TM_PREDS_H\n");
+
+  output_predicate_decls ();
+
+  puts ("#endif /* GCC_TM_PREDS_H */");
+
+  if (ferror (stdout) || fflush (stdout) || fclose (stdout))
+    return FATAL_EXIT_CODE;
+
+  return SUCCESS_EXIT_CODE;
+}
diff --git a/gcc/mkconfig.sh b/gcc/mkconfig.sh
index 03c1d9d4ffc..d43bc983d27 100644
--- a/gcc/mkconfig.sh
+++ b/gcc/mkconfig.sh
@@ -49,12 +49,25 @@ for def in $DEFINES; do
     echo "#endif"
 done
 
-# Include insn-codes.h last, because it includes machmode.h,
-# and we want EXTRA_CC_MODES to be taken into account.
-echo "#ifndef GENERATOR_FILE"
-echo "#include \"insn-codes.h\""
-echo "#include \"insn-flags.h\""
-echo "#endif"
+# If this is tm_p.h, include tm-preds.h unconditionally.
+# If this is tconfig.h or hconfig.h, include no more files.
+# Otherwise, include insn-constants.h, insn-flags.h, and insn-codes.h,
+# but only if GENERATOR_FILE is not defined. (The last of those is
+# slated to be removed.)
+case $output in
+    *tm_p.h)
+	echo "#include \"tm-preds.h\""
+    ;;
+    *tconfig.h | *hconfig.h)
+    ;;
+    *)
+	echo "#ifndef GENERATOR_FILE"
+	echo "# include \"insn-constants.h\""
+	echo "# include \"insn-codes.h\""
+	echo "# include \"insn-flags.h\""
+	echo "#endif"
+    ;;
+esac
 
 ) > $output.T
author	zack <zack@138bc75d-0d04-0410-961f-82ee72b054a4>	2001-08-09 17:11:00 +0000
committer	zack <zack@138bc75d-0d04-0410-961f-82ee72b054a4>	2001-08-09 17:11:00 +0000
commit	e23a6527d76e7d7d1e4b1a2d2787681b0202bc9a (patch)
tree	c707f6fbe6eee894928f18532faad363c22b3b19
parent	45c2202bc22116481baf8d8fd6cb3af45627a784 (diff)
download	gcc-e23a6527d76e7d7d1e4b1a2d2787681b0202bc9a.tar.gz