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author | Lulu Cheng <chenglulu@loongson.cn> | 2023-04-06 16:02:07 +0800 |
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committer | Lulu Cheng <chenglulu@loongson.cn> | 2023-04-21 17:46:08 +0800 |
commit | c5bfb2e08bd551539a2a6c686cf3020b1e8f6ad5 (patch) | |
tree | 46d29aa29b3e856e0ec4b6563c04a5196c35472f | |
parent | f980561c60b0446cc427595198d7f3f4f90e0924 (diff) | |
download | gcc-c5bfb2e08bd551539a2a6c686cf3020b1e8f6ad5.tar.gz |
LoongArch: Add built-in functions description of LoongArch Base instruction set instructions.
gcc/ChangeLog:
* doc/extend.texi: Add section for LoongArch Base Built-in functions.
(cherry picked from commit 5015cdf3155c80e5fd61f7b6ab8082ee849e3e90)
-rw-r--r-- | gcc/doc/extend.texi | 129 |
1 files changed, 129 insertions, 0 deletions
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 0be838489e3..ac476801ed8 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -14674,6 +14674,7 @@ instructions, but allow the compiler to schedule those calls. * Blackfin Built-in Functions:: * BPF Built-in Functions:: * FR-V Built-in Functions:: +* LoongArch Base Built-in Functions:: * MIPS DSP Built-in Functions:: * MIPS Paired-Single Support:: * MIPS Loongson Built-in Functions:: @@ -16203,6 +16204,134 @@ Use the @code{nldub} instruction to load the contents of address @var{x} into the data cache. The instruction is issued in slot I1@. @end table +@node LoongArch Base Built-in Functions +@subsection LoongArch Base Built-in Functions + +These built-in functions are available for LoongArch. + +Data Type Description: +@itemize +@item @code{imm0_31}, a compile-time constant in range 0 to 31; +@item @code{imm0_16383}, a compile-time constant in range 0 to 16383; +@item @code{imm0_32767}, a compile-time constant in range 0 to 32767; +@item @code{imm_n2048_2047}, a compile-time constant in range -2048 to 2047; +@end itemize + +The intrinsics provided are listed below: +@smallexample + unsigned int __builtin_loongarch_movfcsr2gr (imm0_31) + void __builtin_loongarch_movgr2fcsr (imm0_31, unsigned int) + void __builtin_loongarch_cacop_d (imm0_31, unsigned long int, imm_n2048_2047) + unsigned int __builtin_loongarch_cpucfg (unsigned int) + void __builtin_loongarch_asrtle_d (long int, long int) + void __builtin_loongarch_asrtgt_d (long int, long int) + long int __builtin_loongarch_lddir_d (long int, imm0_31) + void __builtin_loongarch_ldpte_d (long int, imm0_31) + + int __builtin_loongarch_crc_w_b_w (char, int) + int __builtin_loongarch_crc_w_h_w (short, int) + int __builtin_loongarch_crc_w_w_w (int, int) + int __builtin_loongarch_crc_w_d_w (long int, int) + int __builtin_loongarch_crcc_w_b_w (char, int) + int __builtin_loongarch_crcc_w_h_w (short, int) + int __builtin_loongarch_crcc_w_w_w (int, int) + int __builtin_loongarch_crcc_w_d_w (long int, int) + + unsigned int __builtin_loongarch_csrrd_w (imm0_16383) + unsigned int __builtin_loongarch_csrwr_w (unsigned int, imm0_16383) + unsigned int __builtin_loongarch_csrxchg_w (unsigned int, unsigned int, imm0_16383) + unsigned long int __builtin_loongarch_csrrd_d (imm0_16383) + unsigned long int __builtin_loongarch_csrwr_d (unsigned long int, imm0_16383) + unsigned long int __builtin_loongarch_csrxchg_d (unsigned long int, unsigned long int, imm0_16383) + + unsigned char __builtin_loongarch_iocsrrd_b (unsigned int) + unsigned short __builtin_loongarch_iocsrrd_h (unsigned int) + unsigned int __builtin_loongarch_iocsrrd_w (unsigned int) + unsigned long int __builtin_loongarch_iocsrrd_d (unsigned int) + void __builtin_loongarch_iocsrwr_b (unsigned char, unsigned int) + void __builtin_loongarch_iocsrwr_h (unsigned short, unsigned int) + void __builtin_loongarch_iocsrwr_w (unsigned int, unsigned int) + void __builtin_loongarch_iocsrwr_d (unsigned long int, unsigned int) + + void __builtin_loongarch_dbar (imm0_32767) + void __builtin_loongarch_ibar (imm0_32767) + + void __builtin_loongarch_syscall (imm0_32767) + void __builtin_loongarch_break (imm0_32767) +@end smallexample + +@emph{Note:}Since the control register is divided into 32-bit and 64-bit, +but the access instruction is not distinguished. So GCC renames the control +instructions when implementing intrinsics. + +Take the csrrd instruction as an example, built-in functions are implemented as follows: +@smallexample + __builtin_loongarch_csrrd_w // When reading the 32-bit control register use. + __builtin_loongarch_csrrd_d // When reading the 64-bit control register use. +@end smallexample + +For the convenience of use, the built-in functions are encapsulated, +the encapsulated functions and @code{__drdtime_t, __rdtime_t} are +defined in the @code{larchintrin.h}. So if you call the following +function you need to include @code{larchintrin.h}. + +@smallexample + typedef struct drdtime@{ + unsigned long dvalue; + unsigned long dtimeid; + @} __drdtime_t; + + typedef struct rdtime@{ + unsigned int value; + unsigned int timeid; + @} __rdtime_t; +@end smallexample + +@smallexample + __drdtime_t __rdtime_d (void) + __rdtime_t __rdtimel_w (void) + __rdtime_t __rdtimeh_w (void) + unsigned int __movfcsr2gr (imm0_31) + void __movgr2fcsr (imm0_31, unsigned int) + void __cacop_d (imm0_31, unsigned long, imm_n2048_2047) + unsigned int __cpucfg (unsigned int) + void __asrtle_d (long int, long int) + void __asrtgt_d (long int, long int) + long int __lddir_d (long int, imm0_31) + void __ldpte_d (long int, imm0_31) + + int __crc_w_b_w (char, int) + int __crc_w_h_w (short, int) + int __crc_w_w_w (int, int) + int __crc_w_d_w (long int, int) + int __crcc_w_b_w (char, int) + int __crcc_w_h_w (short, int) + int __crcc_w_w_w (int, int) + int __crcc_w_d_w (long int, int) + + unsigned int __csrrd_w (imm0_16383) + unsigned int __csrwr_w (unsigned int, imm0_16383) + unsigned int __csrxchg_w (unsigned int, unsigned int, imm0_16383) + unsigned long __csrrd_d (imm0_16383) + unsigned long __csrwr_d (unsigned long, imm0_16383) + unsigned long __csrxchg_d (unsigned long, unsigned long, imm0_16383) + + unsigned char __iocsrrd_b (unsigned int) + unsigned short __iocsrrd_h (unsigned int) + unsigned int __iocsrrd_w (unsigned int) + unsigned long __iocsrrd_d (unsigned int) + void __iocsrwr_b (unsigned char, unsigned int) + void __iocsrwr_h (unsigned short, unsigned int) + void __iocsrwr_w (unsigned int, unsigned int) + void __iocsrwr_d (unsigned long, unsigned int) + + void __dbar (imm0_32767) + void __ibar (imm0_32767) + + void __syscall (imm0_32767) + void __break (imm0_32767) +@end smallexample + @node MIPS DSP Built-in Functions @subsection MIPS DSP Built-in Functions |