rs6000.md (scc patterns): Disable most SImode variants if TARGET_POWERPC64.

        * rs6000.md (scc patterns): Disable most SImode variants if
        TARGET_POWERPC64.
        * rs6000.c (expand_block_move): Fix gen_movsi typos.

        Thu Oct  7 23:06:50 1999  Richard Henderson  <rth@cygnus.com>
        * rs6000.md (fix_truncdfsi2_internal+1): Emit a clobber
        before the fctiwz insn.

        Thu Oct  7 00:36:17 1999  Diego Novillo  <dnovillo@cygnus.com>
        * config/rs6000/rs6000.c (secondary_reload_class): For TARGET_ELF
        make sure that HIGH instructions are copied into BASE_REGS.

From-SVN: r29896

3 files changed, 310 insertions, 48 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index de90270a02a..eadf526b73d 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,17 @@
+Sun Oct 10 20:58:27 1999  David Edelsohn  <edelsohn@gnu.org>
+
+	* rs6000.md (scc patterns): Disable most SImode variants if
+	TARGET_POWERPC64.
+	* rs6000.c (expand_block_move): Fix gen_movsi typos.
+
+	Thu Oct  7 23:06:50 1999  Richard Henderson  <rth@cygnus.com>
+	* rs6000.md (fix_truncdfsi2_internal+1): Emit a clobber
+	before the fctiwz insn.
+
+	Thu Oct  7 00:36:17 1999  Diego Novillo  <dnovillo@cygnus.com>
+	* config/rs6000/rs6000.c (secondary_reload_class): For TARGET_ELF
+	make sure that HIGH instructions are copied into BASE_REGS.
+	
 Thu Sep 30 05:40:34 1999  Richard Earnshaw <rearnsha@arm.com>
 
 	* c-lang.c (finish_file case ndef ASM_OUTPUT_{CON,DE}STRUCTOR): 
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index d4968e381d2..4595866ac0d 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -2119,7 +2119,7 @@ expand_block_move (operands)
 	    {
 	      move_bytes = 2;
 	      tmp_reg = gen_reg_rtx (HImode);
-	      emit_insn (gen_movsi (tmp_reg,
+	      emit_insn (gen_movhi (tmp_reg,
 				    expand_block_move_mem (HImode,
 							   src_addr,
 							   orig_src)));
@@ -2132,7 +2132,7 @@ expand_block_move (operands)
 	    {
 	      move_bytes = 1;
 	      tmp_reg = gen_reg_rtx (QImode);
-	      emit_insn (gen_movsi (tmp_reg,
+	      emit_insn (gen_movqi (tmp_reg,
 				    expand_block_move_mem (QImode,
 							   src_addr,
 							   orig_src)));
@@ -2441,6 +2441,7 @@ secondary_reload_class (class, mode, in)
   if (TARGET_ELF
       && class != BASE_REGS
       && (GET_CODE (in) == SYMBOL_REF
+	  || GET_CODE (in) == HIGH
 	  || GET_CODE (in) == LABEL_REF
 	  || GET_CODE (in) == CONST))
     return BASE_REGS;
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index bb23a1a32a2..9b3c4306f77 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -4335,7 +4335,8 @@
    (clobber (match_operand 3 "gpc_reg_operand" ""))
    (clobber (reg:DI 76))]
   "TARGET_HARD_FLOAT"
-  [(set (subreg:SI (match_dup 2) 0)
+  [(clobber (match_dup 2))
+   (set (subreg:SI (match_dup 2) 0)
 	(fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
    (set (match_dup 3)
 	(unspec [(const_int 0)] 11))
@@ -9009,7 +9010,7 @@
 	(eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
 	       (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")))
    (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
-  ""
+  "! TARGET_POWERPC64"
   "@
    xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
    {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
@@ -9041,7 +9042,7 @@
    (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
 	(eq:SI (match_dup 1) (match_dup 2)))
    (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
-  ""
+  "! TARGET_POWERPC64"
   "@
    xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
    {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1
@@ -9091,7 +9092,7 @@
 			(match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
 		 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))
    (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
-  ""
+  "! TARGET_POWERPC64"
   "@
    xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
    {sfi|subfic} %4,%1,0\;{aze|addze} %0,%3
@@ -9109,7 +9110,7 @@
 	  (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))
 	 (const_int 0)))
    (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
-  ""
+  "! TARGET_POWERPC64"
   "@
    xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
    {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
@@ -9130,7 +9131,7 @@
    (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
 	(plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
    (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
-  ""
+  "! TARGET_POWERPC64"
   "@
    xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
    {sfi|subfic} %4,%1,0\;{aze.|addze.} %0,%3
@@ -9144,7 +9145,7 @@
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
 	(neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
 		       (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))))]
-  ""
+  "! TARGET_POWERPC64"
   "@
    xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
    {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
@@ -9181,7 +9182,7 @@
 		  (const_int 31))
 		 (match_operand:SI 2 "gpc_reg_operand" "r")))
    (clobber (match_scratch:SI 3 "=&r"))]
-  ""
+  "! TARGET_POWERPC64"
   "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
   [(set_attr "length" "8")])
 
@@ -9205,7 +9206,7 @@
 		  (match_operand:SI 2 "gpc_reg_operand" "r"))
 	 (const_int 0)))
    (clobber (match_scratch:SI 3 "=&r"))]
-  ""
+  "! TARGET_POWERPC64"
   "{ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2"
   [(set_attr "type" "compare")
    (set_attr "length" "8")])
@@ -9236,7 +9237,7 @@
 	(plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
 		 (match_dup 2)))
    (clobber (match_scratch:SI 3 "=&r"))]
-  ""
+  "! TARGET_POWERPC64"
   "{ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2"
   [(set_attr "type" "compare")
    (set_attr "length" "8")])
@@ -9343,11 +9344,32 @@
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		(match_operand:SI 2 "reg_or_short_operand" "rI")))]
-  ""
+  "! TARGET_POWERPC64"
   "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
   [(set_attr "length" "12")])
 
 (define_insn ""
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(leu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+		(match_operand:DI 2 "reg_or_short_operand" "rI")))]
+  "TARGET_POWERPC64"
+  "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
+  [(set_attr "length" "12")])
+
+(define_insn ""
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+	(compare:CC
+	 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+		 (match_operand:DI 2 "reg_or_short_operand" "rI"))
+	 (const_int 0)))
+   (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(leu:DI (match_dup 1) (match_dup 2)))]
+  "TARGET_POWERPC64"
+  "subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0"
+  [(set_attr "type" "compare")
+   (set_attr "length" "12")])
+
+(define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x")
 	(compare:CC
 	 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
@@ -9355,18 +9377,31 @@
 	 (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(leu:SI (match_dup 1) (match_dup 2)))]
-   ""
+  "! TARGET_POWERPC64"
   "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0"
   [(set_attr "type" "compare")
    (set_attr "length" "12")])
 
 (define_insn ""
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+	(compare:CC
+	 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+		 (match_operand:DI 2 "reg_or_short_operand" "rI"))
+	 (const_int 0)))
+   (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(leu:DI (match_dup 1) (match_dup 2)))]
+  "TARGET_POWERPC64"
+  "subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0"
+  [(set_attr "type" "compare")
+   (set_attr "length" "12")])
+
+(define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			 (match_operand:SI 2 "reg_or_short_operand" "rI"))
 		 (match_operand:SI 3 "gpc_reg_operand" "r")))
    (clobber (match_scratch:SI 4 "=&r"))]
-  ""
+  "! TARGET_POWERPC64"
   "{sf%I2|subf%I2c} %4,%1,%2\;{aze|addze} %0,%3"
   [(set_attr "length" "8")])
 
@@ -9378,7 +9413,7 @@
 		  (match_operand:SI 3 "gpc_reg_operand" "r"))
 	 (const_int 0)))
    (clobber (match_scratch:SI 4 "=&r"))]
-  ""
+  "! TARGET_POWERPC64"
   "{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3"
   [(set_attr "type" "compare")
    (set_attr "length" "8")])
@@ -9393,7 +9428,7 @@
    (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
    (clobber (match_scratch:SI 4 "=&r"))]
-  ""
+  "! TARGET_POWERPC64"
   "{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %0,%3"
   [(set_attr "type" "compare")
    (set_attr "length" "8")])
@@ -9402,7 +9437,7 @@
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			(match_operand:SI 2 "reg_or_short_operand" "rI"))))]
-  ""
+  "! TARGET_POWERPC64"
   "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
    [(set_attr "length" "12")])
 
@@ -9413,7 +9448,7 @@
 			 (match_operand:SI 2 "reg_or_short_operand" "rI")))
 		(match_operand:SI 3 "gpc_reg_operand" "r")))
    (clobber (match_scratch:SI 4 "=&r"))]
-  ""
+  "! TARGET_POWERPC64"
   "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4"
   [(set_attr "length" "12")])
 
@@ -9426,7 +9461,7 @@
 		 (match_operand:SI 3 "gpc_reg_operand" "r"))
 	 (const_int 0)))
    (clobber (match_scratch:SI 4 "=&r"))]
-  ""
+  "! TARGET_POWERPC64"
   "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4"
   [(set_attr "type" "compare")
    (set_attr "length" "12")])
@@ -9442,7 +9477,7 @@
    (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
    (clobber (match_scratch:SI 4 "=&r"))]
-  ""
+  "! TARGET_POWERPC64"
   "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4"
   [(set_attr "type" "compare")
    (set_attr "length" "12")])
@@ -9518,7 +9553,7 @@
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
 	(ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 		(match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
-  ""
+  "! TARGET_POWERPC64"
   "@
    {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0
    {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
@@ -9532,7 +9567,7 @@
 	 (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
 	(ltu:SI (match_dup 1) (match_dup 2)))]
-  ""
+  "! TARGET_POWERPC64"
   "@
    {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
    {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0"
@@ -9545,7 +9580,7 @@
 			 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
 		 (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))
    (clobber (match_scratch:SI 4 "=&r,&r"))]
-  ""
+  "! TARGET_POWERPC64"
   "@
   {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
   {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3"
@@ -9559,7 +9594,7 @@
 		  (match_operand:SI 3 "gpc_reg_operand" "r,r"))
 	 (const_int 0)))
    (clobber (match_scratch:SI 4 "=&r,&r"))]
-  ""
+  "! TARGET_POWERPC64"
   "@
    {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
    {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3"
@@ -9576,7 +9611,7 @@
    (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
 	(plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
    (clobber (match_scratch:SI 4 "=&r,&r"))]
-  ""
+  "! TARGET_POWERPC64"
   "@
    {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3
    {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3"
@@ -9587,7 +9622,7 @@
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
 	(neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 			(match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
-  ""
+  "! TARGET_POWERPC64"
   "@
    {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
    {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
@@ -9663,6 +9698,7 @@
   [(set_attr "length" "12")])
 
 ;; This is (and (neg (ge X (const_int 0))) Y).
+;; srawi sign-extends, so these patterrns are 64-bit safe.
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(and:SI (neg:SI
@@ -9676,6 +9712,18 @@
   [(set_attr "length" "8")])
 
 (define_insn ""
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(and:DI (neg:DI
+		 (lshiftrt:DI
+		  (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
+		  (const_int 63)))
+		(match_operand:DI 2 "gpc_reg_operand" "r")))
+   (clobber (match_scratch:DI 3 "=&r"))]
+  "TARGET_POWERPC64"
+  "sradi %3,%1,63\;andc %0,%2,%3"
+  [(set_attr "length" "8")])
+
+(define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
 	(compare:CC
 	 (and:SI (neg:SI
@@ -9691,6 +9739,21 @@
    (set_attr "length" "8")])
 
 (define_insn ""
+  [(set (match_operand:CC 0 "cc_reg_operand" "=x")
+	(compare:CC
+	 (and:DI (neg:DI
+		  (lshiftrt:DI
+		   (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
+		   (const_int 63)))
+		 (match_operand:DI 2 "gpc_reg_operand" "r"))
+	 (const_int 0)))
+   (clobber (match_scratch:DI 3 "=&r"))]
+  "TARGET_POWERPC64"
+  "sradi %3,%1,63\;andc. %3,%2,%3"
+  [(set_attr "type" "compare")
+   (set_attr "length" "8")])
+
+(define_insn ""
   [(set (match_operand:CC 4 "cc_reg_operand" "=x")
 	(compare:CC
 	 (and:SI (neg:SI
@@ -9710,16 +9773,45 @@
    (set_attr "length" "8")])
 
 (define_insn ""
+  [(set (match_operand:CC 4 "cc_reg_operand" "=x")
+	(compare:CC
+	 (and:DI (neg:DI
+		  (lshiftrt:DI
+		   (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
+		   (const_int 63)))
+		 (match_operand:DI 2 "gpc_reg_operand" "r"))
+	 (const_int 0)))
+   (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(and:DI (neg:DI (lshiftrt:SI (not:DI (match_dup 1))
+				     (const_int 63)))
+		(match_dup 2)))
+   (clobber (match_scratch:SI 3 "=&r"))]
+  "TARGET_POWERPC64"
+  "sradi %3,%1,63\;andc. %0,%2,%3"
+  [(set_attr "type" "compare")
+   (set_attr "length" "8")])
+
+(define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
 	(geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 		(match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
-  ""
+  "! TARGET_POWERPC64"
   "@
    {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
    {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
   [(set_attr "length" "12")])
 
 (define_insn ""
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
+	(geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
+		(match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
+  "TARGET_POWERPC64"
+  "@
+   subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
+   addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
+  [(set_attr "length" "12")])
+
+(define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
 	(compare:CC
 	 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
@@ -9727,7 +9819,7 @@
 	 (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
 	(geu:SI (match_dup 1) (match_dup 2)))]
-  ""
+  "! TARGET_POWERPC64"
   "@
    {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
    {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0"
@@ -9735,12 +9827,27 @@
    (set_attr "length" "12")])
 
 (define_insn ""
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
+	(compare:CC
+	 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
+		 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P"))
+	 (const_int 0)))
+   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
+	(geu:DI (match_dup 1) (match_dup 2)))]
+  "TARGET_POWERPC64"
+  "@
+   subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
+   addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0"
+  [(set_attr "type" "compare")
+   (set_attr "length" "12")])
+
+(define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
 	(plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 			 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
 		 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
    (clobber (match_scratch:SI 4 "=&r,&r"))]
-  ""
+  "! TARGET_POWERPC64"
   "@
    {sf|subfc} %4,%2,%1\;{aze|addze} %0,%3
    {ai|addic} %4,%1,%n2\;{aze|addze} %0,%3"
@@ -9754,7 +9861,7 @@
 		  (match_operand:SI 3 "gpc_reg_operand" "r,r"))
 	 (const_int 0)))
    (clobber (match_scratch:SI 4 "=&r,&r"))]
-  ""
+  "! TARGET_POWERPC64"
   "@
    {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
    {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3"
@@ -9771,7 +9878,7 @@
    (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
 	(plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
    (clobber (match_scratch:SI 4 "=&r,&r"))]
-  ""
+  "! TARGET_POWERPC64"
   "@
    {sf|subfc} %4,%2,%1\;{aze.|addze.} %0,%3
    {ai|addic} %4,%1,%n2\;{aze.|addze.} %0,%3"
@@ -9782,7 +9889,7 @@
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
 	(neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 			(match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
-  ""
+  "! TARGET_POWERPC64"
   "@
    {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
    {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
@@ -9795,7 +9902,7 @@
 			 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
 		(match_operand:SI 3 "gpc_reg_operand" "r,r")))
    (clobber (match_scratch:SI 4 "=&r,&r"))]
-  ""
+  "! TARGET_POWERPC64"
   "@
    {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4
    {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4"
@@ -9810,7 +9917,7 @@
 		 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
 	 (const_int 0)))
    (clobber (match_scratch:SI 4 "=&r,&r"))]
-  ""
+  "! TARGET_POWERPC64"
   "@
    {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
    {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4"
@@ -9828,7 +9935,7 @@
    (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
 	(and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
    (clobber (match_scratch:SI 4 "=&r,&r"))]
-  ""
+  "! TARGET_POWERPC64"
   "@
    {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4
    {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4"
@@ -9839,11 +9946,19 @@
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 	       (const_int 0)))]
-  ""
+  "! TARGET_POWERPC64"
   "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
   [(set_attr "length" "12")])
 
 (define_insn ""
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+	       (const_int 0)))]
+  "TARGET_POWERPC64"
+  "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63"
+  [(set_attr "length" "12")])
+
+(define_insn ""
   [(set (match_operand:CC 2 "cc_reg_operand" "=x")
 	(compare:CC
 	 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
@@ -9851,12 +9966,25 @@
 	 (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(gt:SI (match_dup 1) (const_int 0)))]
-  ""
+  "! TARGET_POWERPC64"
   "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31"
   [(set_attr "type" "delayed_compare")
    (set_attr "length" "12")])
 
 (define_insn ""
+  [(set (match_operand:CC 2 "cc_reg_operand" "=x")
+	(compare:CC
+	 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+		(const_int 0))
+	 (const_int 0)))
+   (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(gt:DI (match_dup 1) (const_int 0)))]
+  "TARGET_POWERPC64"
+  "subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63"
+  [(set_attr "type" "delayed_compare")
+   (set_attr "length" "12")])
+
+(define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 	       (match_operand:SI 2 "reg_or_short_operand" "r")))]
@@ -9883,11 +10011,21 @@
 			(const_int 0))
 		 (match_operand:SI 2 "gpc_reg_operand" "r")))
    (clobber (match_scratch:SI 3 "=&r"))]
-  ""
+  "! TARGET_POWERPC64"
   "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze|addze} %0,%2"
   [(set_attr "length" "12")])
 
 (define_insn ""
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+			(const_int 0))
+		 (match_operand:DI 2 "gpc_reg_operand" "r")))
+   (clobber (match_scratch:DI 3 "=&r"))]
+  "TARGET_POWERPC64"
+  "addc %3,%1,%1\;subfe %3,%1,%3\;addze %0,%2"
+  [(set_attr "length" "12")])
+
+(define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
 	(compare:CC
 	 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
@@ -9895,12 +10033,25 @@
 		  (match_operand:SI 2 "gpc_reg_operand" "r"))
 	 (const_int 0)))
    (clobber (match_scratch:SI 3 "=&r"))]
-  ""
+  "! TARGET_POWERPC64"
   "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2"
   [(set_attr "type" "compare")
    (set_attr "length" "12")])
 
 (define_insn ""
+  [(set (match_operand:CC 0 "cc_reg_operand" "=x")
+	(compare:CC
+	 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+			 (const_int 0))
+		  (match_operand:DI 2 "gpc_reg_operand" "r"))
+	 (const_int 0)))
+   (clobber (match_scratch:DI 3 "=&r"))]
+  "TARGET_POWERPC64"
+  "addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2"
+  [(set_attr "type" "compare")
+   (set_attr "length" "12")])
+
+(define_insn ""
   [(set (match_operand:CC 4 "cc_reg_operand" "=x")
 	(compare:CC
 	 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
@@ -9910,12 +10061,27 @@
    (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
    (clobber (match_scratch:SI 3 "=&r"))]
-  ""
+  "! TARGET_POWERPC64"
   "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %0,%2"
   [(set_attr "type" "compare")
    (set_attr "length" "12")])
 
 (define_insn ""
+  [(set (match_operand:CC 4 "cc_reg_operand" "=x")
+	(compare:CC
+	 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+			 (const_int 0))
+		  (match_operand:DI 2 "gpc_reg_operand" "r"))
+	 (const_int 0)))
+   (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
+   (clobber (match_scratch:DI 3 "=&r"))]
+  "TARGET_POWERPC64"
+  "addc %3,%1,%1\;subfe %3,%1,%3\;addze. %0,%2"
+  [(set_attr "type" "compare")
+   (set_attr "length" "12")])
+
+(define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			(match_operand:SI 2 "reg_or_short_operand" "r"))
@@ -9957,11 +10123,19 @@
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		       (const_int 0))))]
-  ""
+  "! TARGET_POWERPC64"
   "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
   [(set_attr "length" "12")])
 
 (define_insn ""
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+		       (const_int 0))))]
+  "TARGET_POWERPC64"
+  "subfic %0,%1,0\;addme %0,%0\;sradi} %0,%0,63"
+  [(set_attr "length" "12")])
+
+(define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		       (match_operand:SI 2 "reg_or_short_operand" "r"))))]
@@ -9973,11 +10147,19 @@
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		(match_operand:SI 2 "reg_or_short_operand" "rI")))]
-  ""
+  "! TARGET_POWERPC64"
   "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
   [(set_attr "length" "12")])
 
 (define_insn ""
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+		(match_operand:DI 2 "reg_or_short_operand" "rI")))]
+  "TARGET_POWERPC64"
+  "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg %0,%0"
+  [(set_attr "length" "12")])
+
+(define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x")
 	(compare:CC
 	 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
@@ -9985,24 +10167,49 @@
 	 (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(gtu:SI (match_dup 1) (match_dup 2)))]
-  ""
+  "! TARGET_POWERPC64"
   "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0"
   [(set_attr "type" "compare")
    (set_attr "length" "12")])
 
 (define_insn ""
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
+	(compare:CC
+	 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+		 (match_operand:DI 2 "reg_or_short_operand" "rI"))
+	 (const_int 0)))
+   (set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(gtu:DI (match_dup 1) (match_dup 2)))]
+  "TARGET_POWERPC64"
+  "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0"
+  [(set_attr "type" "compare")
+   (set_attr "length" "12")])
+
+(define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
 	(plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 			 (match_operand:SI 2 "reg_or_short_operand" "I,rI"))
 		 (match_operand:SI 3 "reg_or_short_operand" "r,rI")))
    (clobber (match_scratch:SI 4 "=&r,&r"))]
-  ""
+  "! TARGET_POWERPC64"
   "@
    {ai|addic} %4,%1,%k2\;{aze|addze} %0,%3
    {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3"
   [(set_attr "length" "8,12")])
 
 (define_insn ""
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
+	(plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
+			 (match_operand:DI 2 "reg_or_short_operand" "I,rI"))
+		 (match_operand:DI 3 "reg_or_short_operand" "r,rI")))
+   (clobber (match_scratch:DI 4 "=&r,&r"))]
+  "TARGET_POWERPC64"
+  "@
+   addic %4,%1,%k2\;addze %0,%3
+   subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subf%I3c %0,%4,%3"
+  [(set_attr "length" "8,12")])
+
+(define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
 	(compare:CC
 	 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
@@ -10010,7 +10217,7 @@
 		  (match_operand:SI 3 "gpc_reg_operand" "r,r"))
 	 (const_int 0)))
    (clobber (match_scratch:SI 4 "=&r,&r"))]
-  ""
+  "! TARGET_POWERPC64"
   "@
    {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3
    {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3"
@@ -10018,6 +10225,21 @@
    (set_attr "length" "8,12")])
 
 (define_insn ""
+  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
+	(compare:CC
+	 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
+			  (match_operand:DI 2 "reg_or_short_operand" "I,r"))
+		  (match_operand:DI 3 "gpc_reg_operand" "r,r"))
+	 (const_int 0)))
+   (clobber (match_scratch:DI 4 "=&r,&r"))]
+  "TARGET_POWERPC64"
+  "@
+   addic %4,%1,%k2\;addze. %4,%3
+   subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %4,%4,%3"
+  [(set_attr "type" "compare")
+   (set_attr "length" "8,12")])
+
+(define_insn ""
   [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
 	(compare:CC
 	 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
@@ -10027,7 +10249,7 @@
    (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
 	(plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
    (clobber (match_scratch:SI 4 "=&r,&r"))]
-  ""
+  "! TARGET_POWERPC64"
   "@
    {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3
    {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3"
@@ -10035,12 +10257,37 @@
    (set_attr "length" "8,12")])
 
 (define_insn ""
+  [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
+	(compare:CC
+	 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
+			  (match_operand:DI 2 "reg_or_short_operand" "I,r"))
+		  (match_operand:DI 3 "gpc_reg_operand" "r,r"))
+	 (const_int 0)))
+   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
+	(plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
+   (clobber (match_scratch:DI 4 "=&r,&r"))]
+  "TARGET_POWERPC64"
+  "@
+   addic %4,%1,%k2\;addze. %0,%3
+   subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %0,%4,%3"
+  [(set_attr "type" "compare")
+   (set_attr "length" "8,12")])
+
+(define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			(match_operand:SI 2 "reg_or_short_operand" "rI"))))]
-  ""
+  "! TARGET_POWERPC64"
   "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
   [(set_attr "length" "8")])
+
+(define_insn ""
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+			(match_operand:DI 2 "reg_or_short_operand" "rI"))))]
+  "TARGET_POWERPC64"
+  "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
+  [(set_attr "length" "8")])
 
 ;; Define both directions of branch and return.  If we need a reload
 ;; register, we'd rather use CR0 since it is much easier to copy a