Adding the missing LTGT to plug the ICE in PR81228.

This is a backport of r255625 of trunk.

*** gcc/ChangeLog ***

2018-02-22  Sudakshina Das  <sudi.das@arm.com>
	    Bin Cheng  <bin.cheng@arm.com>

	Backport from mainline:
	2017-12-14  Sudakshina Das  <sudi.das@arm.com>
		    Bin Cheng  <bin.cheng@arm.com>

	PR target/81228
	* config/aarch64/aarch64.c (aarch64_select_cc_mode): Move LTGT to
	CCFPEmode.
	* config/aarch64/aarch64-simd.md (vec_cmp<mode><v_cmp_result>): Add
	LTGT.

*** gcc/testsuite/ChangeLog ***

2017-02-22  Sudakshina Das  <sudi.das@arm.com>

	Backport from mainline:
	2017-12-14  Sudakshina Das  <sudi.das@arm.com>

	PR target/81228
	* gcc.dg/pr81228.c: New.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-7-branch@257901 138bc75d-0d04-0410-961f-82ee72b054a4

5 files changed, 53 insertions, 1 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 30d54a76ff9..4aa65b2f64d 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,16 @@
+2018-02-22  Sudakshina Das  <sudi.das@arm.com>
+	    Bin Cheng  <bin.cheng@arm.com>
+
+	Backport from mainline:
+	2017-12-14  Sudakshina Das  <sudi.das@arm.com>
+		    Bin Cheng  <bin.cheng@arm.com>
+
+	PR target/81228
+	* config/aarch64/aarch64.c (aarch64_select_cc_mode): Move LTGT to
+	CCFPEmode.
+	* config/aarch64/aarch64-simd.md (vec_cmp<mode><v_cmp_result>): Add
+	LTGT.
+
 2018-02-16  Jozef Lawrynowicz <jozefl.gcc@gmail.com>
 
 	PR target/79242
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index c4621643452..1e0a346e553 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -2490,6 +2490,7 @@
     case UNEQ:
     case ORDERED:
     case UNORDERED:
+    case LTGT:
       break;
     default:
       gcc_unreachable ();
@@ -2544,6 +2545,15 @@
       emit_insn (gen_one_cmpl<v_cmp_result>2 (operands[0], operands[0]));
       break;
 
+    case LTGT:
+      /* LTGT is not guranteed to not generate a FP exception.  So let's
+	 go the faster way : ((a > b) || (b > a)).  */
+      emit_insn (gen_aarch64_cmgt<mode> (operands[0],
+					 operands[2], operands[3]));
+      emit_insn (gen_aarch64_cmgt<mode> (tmp, operands[3], operands[2]));
+      emit_insn (gen_ior<v_cmp_result>3 (operands[0], operands[0], tmp));
+      break;
+
     case UNORDERED:
       /* Operands are ORDERED iff (a > b || b >= a), so we can compute
 	 UNORDERED as !ORDERED.  */
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 1ec0c7d705a..99f05d7d051 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -4664,13 +4664,13 @@ aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y)
 	case UNGT:
 	case UNGE:
 	case UNEQ:
-	case LTGT:
 	  return CCFPmode;
 
 	case LT:
 	case LE:
 	case GT:
 	case GE:
+	case LTGT:
 	  return CCFPEmode;
 
 	default:
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 2afecaae464..dd9e5675f70 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2017-02-22  Sudakshina Das  <sudi.das@arm.com>
+
+	Backport from mainline:
+	2017-12-14  Sudakshina Das  <sudi.das@arm.com>
+
+	PR target/81228
+	* gcc.dg/pr81228.c: New.
+
 2018-02-19  Jonathan Wakely  <jwakely@redhat.com>
 
 	Backport from mainline
diff --git a/gcc/testsuite/gcc.dg/pr81228.c b/gcc/testsuite/gcc.dg/pr81228.c
new file mode 100644
index 00000000000..f7eecc510ad
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr81228.c
@@ -0,0 +1,21 @@
+/* PR target/81228.  */
+/* { dg-do compile } */
+/* { dg-options "-O3 -fdump-tree-ssa" } */
+
+void *a;
+
+void b ()
+{
+  char c;
+  long d;
+  char *e = a;
+  for (; d; d++)
+  {
+    double f, g;
+    c = g < f || g > f;
+    e[d] = c;
+  }
+}
+
+/* Let's make sure we do have a LTGT.  */
+/* { dg-final { scan-tree-dump "<>" "ssa" } } */