diff options
| author | bstarynk <bstarynk@138bc75d-0d04-0410-961f-82ee72b054a4> | 2009-07-27 07:51:59 +0000 |
|---|---|---|
| committer | bstarynk <bstarynk@138bc75d-0d04-0410-961f-82ee72b054a4> | 2009-07-27 07:51:59 +0000 |
| commit | cb56012690ae1b8f203a61decdcb5d281db2431c (patch) | |
| tree | 58bc341cb04d6000b923fc1d7edb78289d9f2938 /boehm-gc | |
| parent | 84836637fcb8e7c3aea3b25f4cbf17a59cfca553 (diff) | |
| download | gcc-cb56012690ae1b8f203a61decdcb5d281db2431c.tar.gz | |
2009-07-27 Basile Starynkevitch <basile@starynkevitch.net>
MELT branch merged with trunk rev 150103
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/melt-branch@150104 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'boehm-gc')
| -rw-r--r-- | boehm-gc/ChangeLog | 9 | ||||
| -rw-r--r-- | boehm-gc/include/private/gc_locks.h | 36 |
2 files changed, 20 insertions, 25 deletions
diff --git a/boehm-gc/ChangeLog b/boehm-gc/ChangeLog index 14ba80a9a7a..fa53669ca2a 100644 --- a/boehm-gc/ChangeLog +++ b/boehm-gc/ChangeLog @@ -1,3 +1,12 @@ +2009-07-17 Michael Meissner <meissner@linux.vnet.ibm.com> + + PR boehm-gc/40785 + * include/private/gc_locks.h (GC_test_and_set): If GCC 4.4, use + the __sync_lock_test_and _set and __sync_lock_release builtins on + the powerpc. If not GCC 4.4, fix up the constraints so that it + builds without error. + (GC_clear): Ditto. + 2009-07-17 Kai Tietz <kai.tietz@onevision.com> * configure.ac: Add rule for mingw targets to add -DGC_BUILD=1 to diff --git a/boehm-gc/include/private/gc_locks.h b/boehm-gc/include/private/gc_locks.h index 4e2b641b78b..d1bb2e4521a 100644 --- a/boehm-gc/include/private/gc_locks.h +++ b/boehm-gc/include/private/gc_locks.h @@ -139,49 +139,35 @@ # define GC_TEST_AND_SET_DEFINED # endif # if defined(POWERPC) -# if 0 /* CPP_WORDSZ == 64 totally broken to use int locks with ldarx */ - inline static int GC_test_and_set(volatile unsigned int *addr) { - unsigned long oldval; - unsigned long temp = 1; /* locked value */ - - __asm__ __volatile__( - "1:\tldarx %0,0,%3\n" /* load and reserve */ - "\tcmpdi %0, 0\n" /* if load is */ - "\tbne 2f\n" /* non-zero, return already set */ - "\tstdcx. %2,0,%1\n" /* else store conditional */ - "\tbne- 1b\n" /* retry if lost reservation */ - "\tsync\n" /* import barrier */ - "2:\t\n" /* oldval is zero if we set */ - : "=&r"(oldval), "=p"(addr) - : "r"(temp), "1"(addr) - : "cr0","memory"); - return (int)oldval; - } +# define GC_TEST_AND_SET_DEFINED +# define GC_CLEAR_DEFINED +# if (__GNUC__>4)||((__GNUC__==4)&&(__GNUC_MINOR__>=4)) +# define GC_test_and_set(addr) __sync_lock_test_and_set (addr, 1) +# define GC_clear(addr) __sync_lock_release (addr) # else inline static int GC_test_and_set(volatile unsigned int *addr) { int oldval; int temp = 1; /* locked value */ __asm__ __volatile__( - "1:\tlwarx %0,0,%3\n" /* load and reserve */ + "\n1:\n" + "\tlwarx %0,%y3\n" /* load and reserve, 32-bits */ "\tcmpwi %0, 0\n" /* if load is */ "\tbne 2f\n" /* non-zero, return already set */ - "\tstwcx. %2,0,%1\n" /* else store conditional */ + "\tstwcx. %2,%y3\n" /* else store conditional */ "\tbne- 1b\n" /* retry if lost reservation */ "\tsync\n" /* import barrier */ "2:\t\n" /* oldval is zero if we set */ - : "=&r"(oldval), "=p"(addr) - : "r"(temp), "1"(addr) + : "=&r"(oldval), "=m"(addr) + : "r"(temp), "Z"(addr) : "cr0","memory"); return oldval; } -# endif -# define GC_TEST_AND_SET_DEFINED inline static void GC_clear(volatile unsigned int *addr) { __asm__ __volatile__("lwsync" : : : "memory"); *(addr) = 0; } -# define GC_CLEAR_DEFINED +# endif # endif # if defined(ALPHA) inline static int GC_test_and_set(volatile unsigned int * addr) |