PR/60825 Make float64x1_t in arm_neon.h a proper vector type

gcc/ChangeLog:
	PR target/60825
	* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Add entry for
	V1DFmode.
	* config/aarch64/aarch64-builtins.c (aarch64_simd_builtin_type_mode):
	add V1DFmode
	(BUILTIN_VD1): New.
	(BUILTIN_VD_RE): Remove.
	(aarch64_init_simd_builtins): Add V1DF to modes/modenames.
	(aarch64_fold_builtin): Update reinterpret patterns, df becomes v1df.
	* config/aarch64/aarch64-simd-builtins.def (create): Make a v1df
	variant but not df.
	(vreinterpretv1df*, vreinterpret*v1df): New.
	(vreinterpretdf*, vreinterpret*df): Remove.
	* config/aarch64/aarch64-simd.md (aarch64_create, aarch64_reinterpret*):
	Generate V1DFmode pattern not DFmode.
	* config/aarch64/iterators.md (VD_RE): Include V1DF, remove DF.
	(VD1): New.
	* config/aarch64/arm_neon.h (float64x1_t): typedef with gcc extensions.
	(vcreate_f64): Remove cast, use v1df builtin.
	(vcombine_f64): Remove cast, get elements with gcc vector extensions.
	(vget_low_f64, vabs_f64, vceq_f64, vceqz_f64, vcge_f64, vgfez_f64,
	vcgt_f64, vcgtz_f64, vcle_f64, vclez_f64, vclt_f64, vcltz_f64,
	vdup_n_f64, vdupq_lane_f64, vld1_f64, vld2_f64, vld3_f64, vld4_f64,
	vmov_n_f64, vst1_f64): Use gcc vector extensions.
	(vget_lane_f64, vdupd_lane_f64, vmulq_lane_f64, ): Use gcc extensions,
	add range check using __builtin_aarch64_im_lane_boundsi.
	(vfma_lane_f64, vfmad_lane_f64, vfma_laneq_f64, vfmaq_lane_f64,
	vfms_lane_f64, vfmsd_lane_f64, vfms_laneq_f64, vfmsq_lane_f64): Fix
	type signature, use gcc vector extensions.
	(vreinterpret_p8_f64, vreinterpret_p16_f64, vreinterpret_f32_f64,
	vreinterpret_f64_f32, vreinterpret_f64_p8, vreinterpret_f64_p16,
	vreinterpret_f64_s8, vreinterpret_f64_s16, vreinterpret_f64_s32,
	vreinterpret_f64_s64, vreinterpret_f64_u8, vreinterpret_f64_u16,
	vreinterpret_f64_u32, vreinterpret_f64_u64, vreinterpret_s8_f64,
	vreinterpret_s16_f64, vreinterpret_s32_f64, vreinterpret_s64_f64,
	vreinterpret_u8_f64, vreinterpret_u16_f64, vreinterpret_u32_f64,
	vreinterpret_u64_f64): Use v1df builtin not df.

gcc/testsuite/ChangeLog:
	* g++.dg/abi/mangle-neon-aarch64.C: Also test mangling of float64x1_t.
	* gcc.target/aarch64/aapcs/test_64x1_1.c: New test.
	* gcc.target/aarch64/aapcs/func-ret-64x1_1.c: New test.
	* gcc.target/aarch64/simd/ext_f64_1.c (main): Compare vector elements.
	* gcc.target/aarch64/vadd_f64.c: Rewrite with macro to use vector types.
	* gcc.target/aarch64/vsub_f64.c: Likewise.
	* gcc.target/aarch64/vdiv_f.c (INDEX*, RUN_TEST): Remove indexing scheme
	as now the same for all variants.
	* gcc.target/aarch64/vrnd_f64_1.c (compare_f64): Return float64_t not
	float64x1_t.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211892 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 24 insertions, 23 deletions

diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c
index a94ef52f71a..eebb7d3978d 100644
--- a/gcc/config/aarch64/aarch64-builtins.c
+++ b/gcc/config/aarch64/aarch64-builtins.c
@@ -53,6 +53,7 @@ enum aarch64_simd_builtin_type_mode
   T_V4HI,
   T_V2SI,
   T_V2SF,
+  T_V1DF,
   T_DI,
   T_DF,
   T_V16QI,
@@ -76,6 +77,7 @@ enum aarch64_simd_builtin_type_mode
 #define v4hi_UP  T_V4HI
 #define v2si_UP  T_V2SI
 #define v2sf_UP  T_V2SF
+#define v1df_UP  T_V1DF
 #define di_UP    T_DI
 #define df_UP    T_DF
 #define v16qi_UP T_V16QI
@@ -346,6 +348,8 @@ aarch64_types_storestruct_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
   VAR2 (T, N, MAP, v8qi, v16qi)
 #define BUILTIN_VD(T, N, MAP) \
   VAR4 (T, N, MAP, v8qi, v4hi, v2si, v2sf)
+#define BUILTIN_VD1(T, N, MAP) \
+  VAR5 (T, N, MAP, v8qi, v4hi, v2si, v2sf, v1df)
 #define BUILTIN_VDC(T, N, MAP) \
   VAR6 (T, N, MAP, v8qi, v4hi, v2si, v2sf, di, df)
 #define BUILTIN_VDIC(T, N, MAP) \
@@ -380,8 +384,6 @@ aarch64_types_storestruct_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
   VAR3 (T, N, MAP, v8qi, v4hi, v2si)
 #define BUILTIN_VD_HSI(T, N, MAP) \
   VAR2 (T, N, MAP, v4hi, v2si)
-#define BUILTIN_VD_RE(T, N, MAP) \
-  VAR6 (T, N, MAP, v8qi, v4hi, v2si, v2sf, di, df)
 #define BUILTIN_VQ(T, N, MAP) \
   VAR6 (T, N, MAP, v16qi, v8hi, v4si, v2di, v4sf, v2df)
 #define BUILTIN_VQN(T, N, MAP) \
@@ -729,13 +731,13 @@ aarch64_init_simd_builtins (void)
       aarch64_simd_builtin_datum *d = &aarch64_simd_builtin_data[i];
       const char *const modenames[] =
 	{
-	  "v8qi", "v4hi", "v2si", "v2sf", "di", "df",
+	  "v8qi", "v4hi", "v2si", "v2sf", "v1df", "di", "df",
 	  "v16qi", "v8hi", "v4si", "v4sf", "v2di", "v2df",
 	  "ti", "ei", "oi", "xi", "si", "sf", "hi", "qi"
 	};
       const enum machine_mode modes[] =
 	{
-	  V8QImode, V4HImode, V2SImode, V2SFmode, DImode, DFmode,
+	  V8QImode, V4HImode, V2SImode, V2SFmode, V1DFmode, DImode, DFmode,
 	  V16QImode, V8HImode, V4SImode, V4SFmode, V2DImode,
 	  V2DFmode, TImode, EImode, OImode, XImode, SImode,
 	  SFmode, HImode, QImode
@@ -1342,24 +1344,23 @@ aarch64_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED, tree *args,
 	  return fold_build2 (NE_EXPR, type, and_node, vec_zero_node);
 	  break;
 	}
-      VAR1 (REINTERP_SS, reinterpretdi, 0, df)
-      VAR1 (REINTERP_SS, reinterpretv8qi, 0, df)
-      VAR1 (REINTERP_SS, reinterpretv4hi, 0, df)
-      VAR1 (REINTERP_SS, reinterpretv2si, 0, df)
-      VAR1 (REINTERP_SS, reinterpretv2sf, 0, df)
-      BUILTIN_VD (REINTERP_SS, reinterpretdf, 0)
-      BUILTIN_VD (REINTERP_SU, reinterpretdf, 0)
-      VAR1 (REINTERP_US, reinterpretdi, 0, df)
-      VAR1 (REINTERP_US, reinterpretv8qi, 0, df)
-      VAR1 (REINTERP_US, reinterpretv4hi, 0, df)
-      VAR1 (REINTERP_US, reinterpretv2si, 0, df)
-      VAR1 (REINTERP_US, reinterpretv2sf, 0, df)
-      BUILTIN_VD (REINTERP_SP, reinterpretdf, 0)
-      VAR1 (REINTERP_PS, reinterpretdi, 0, df)
-      VAR1 (REINTERP_PS, reinterpretv8qi, 0, df)
-      VAR1 (REINTERP_PS, reinterpretv4hi, 0, df)
-      VAR1 (REINTERP_PS, reinterpretv2si, 0, df)
-      VAR1 (REINTERP_PS, reinterpretv2sf, 0, df)
+      VAR1 (REINTERP_SS, reinterpretdi, 0, v1df)
+      VAR1 (REINTERP_SS, reinterpretv8qi, 0, v1df)
+      VAR1 (REINTERP_SS, reinterpretv4hi, 0, v1df)
+      VAR1 (REINTERP_SS, reinterpretv2si, 0, v1df)
+      VAR1 (REINTERP_SS, reinterpretv2sf, 0, v1df)
+      BUILTIN_VD (REINTERP_SS, reinterpretv1df, 0)
+      BUILTIN_VD (REINTERP_SU, reinterpretv1df, 0)
+      VAR1 (REINTERP_US, reinterpretdi, 0, v1df)
+      VAR1 (REINTERP_US, reinterpretv8qi, 0, v1df)
+      VAR1 (REINTERP_US, reinterpretv4hi, 0, v1df)
+      VAR1 (REINTERP_US, reinterpretv2si, 0, v1df)
+      VAR1 (REINTERP_US, reinterpretv2sf, 0, v1df)
+      BUILTIN_VD (REINTERP_SP, reinterpretv1df, 0)
+      VAR1 (REINTERP_PS, reinterpretdi, 0, v1df)
+      VAR1 (REINTERP_PS, reinterpretv8qi, 0, v1df)
+      VAR1 (REINTERP_PS, reinterpretv4hi, 0, v1df)
+      VAR1 (REINTERP_PS, reinterpretv2sf, 0, v1df)
 	return fold_build1 (VIEW_CONVERT_EXPR, type, args[0]);
       VAR1 (UNOP, floatv2si, 2, v2sf)
       VAR1 (UNOP, floatv4si, 2, v4sf)
@@ -1539,6 +1540,7 @@ aarch64_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
 #undef BUILTIN_VALL
 #undef BUILTIN_VB
 #undef BUILTIN_VD
+#undef BUILTIN_VD1
 #undef BUILTIN_VDC
 #undef BUILTIN_VDIC
 #undef BUILTIN_VDN
@@ -1554,7 +1556,6 @@ aarch64_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
 #undef BUILTIN_VDW
 #undef BUILTIN_VD_BHSI
 #undef BUILTIN_VD_HSI
-#undef BUILTIN_VD_RE
 #undef BUILTIN_VQ
 #undef BUILTIN_VQN
 #undef BUILTIN_VQW