diff options
| author | wilco <wilco@138bc75d-0d04-0410-961f-82ee72b054a4> | 2016-12-08 19:18:33 +0000 |
|---|---|---|
| committer | wilco <wilco@138bc75d-0d04-0410-961f-82ee72b054a4> | 2016-12-08 19:18:33 +0000 |
| commit | 8da6e78e68cb290a046135f0d8c5b40e28805f5d (patch) | |
| tree | e2fecc79734bfc862c1cce548342eddf0fd76f1f /gcc/config/aarch64/aarch64.c | |
| parent | 64215350809ec3d3ed76ab210223819845b4e0cc (diff) | |
| download | gcc-8da6e78e68cb290a046135f0d8c5b40e28805f5d.tar.gz | |
This patch fixes an issue in aarch64_classify_address. TImode and TFmode
can either use a 64-bit LDP/STP or 128-bit LDR/STR. The addressing mode
must be carefully modelled as the intersection of both. This is done for
the immediate offsets, however load_store_pair_p must be set as well to
avoid LDP with a PC-relative address if aarch64_pcrelative_literal_loads
is true.
gcc/
PR target/78733
* config/aarch64/aarch64.c (aarch64_classify_address):
Set load_store_pair_p for TImode and TFmode.
testsuite/
* gcc.target/aarch64/pr78733.c: New test.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@243456 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/aarch64/aarch64.c')
| -rw-r--r-- | gcc/config/aarch64/aarch64.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 1a06432655e..e87831f56e9 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -4273,8 +4273,11 @@ aarch64_classify_address (struct aarch64_address_info *info, enum rtx_code code = GET_CODE (x); rtx op0, op1; - /* On BE, we use load/store pair for all large int mode load/stores. */ + /* On BE, we use load/store pair for all large int mode load/stores. + TI/TFmode may also use a load/store pair. */ bool load_store_pair_p = (outer_code == PARALLEL + || mode == TImode + || mode == TFmode || (BYTES_BIG_ENDIAN && aarch64_vect_struct_mode_p (mode))); |