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| author | jgreenhalgh <jgreenhalgh@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-11-26 10:03:14 +0000 |
|---|---|---|
| committer | jgreenhalgh <jgreenhalgh@138bc75d-0d04-0410-961f-82ee72b054a4> | 2013-11-26 10:03:14 +0000 |
| commit | 408987fbc17985e016a768a2a4dc2a99d18487d8 (patch) | |
| tree | b2fa6662c10162f57cba60f6459f47e49c4d4064 /gcc/config/aarch64/iterators.md | |
| parent | 777beb696ccd0bf125ae44894b2a839a6b51807d (diff) | |
| download | gcc-408987fbc17985e016a768a2a4dc2a99d18487d8.tar.gz | |
[AArch64] [3/4 Fix vtbx1]Implement bsl intrinsics using builtins
gcc/
* config/aarch64/aarch64-builtins.c
(aarch64_types_bsl_p_qualifiers): New.
(aarch64_types_bsl_s_qualifiers): Likewise.
(aarch64_types_bsl_u_qualifiers): Likewise.
(TYPES_BSL_P): Likewise.
(TYPES_BSL_S): Likewise.
(TYPES_BSL_U): Likewise.
(BUILTIN_VALLDIF): Likewise.
(BUILTIN_VDQQH): Likewise.
* config/aarch64/aarch64-simd-builtins.def (simd_bsl): New.
* config/aarch64/aarch64-simd.md
(aarch64_simd_bsl<mode>_internal): Handle more modes.
(aarch64_simd_bsl<mode>): Likewise.
* config/aarch64/arm_neon.h
(vbsl<q>_<fpsu><8,16,32,64): Implement using builtins.
* config/aarch64/iterators.md (VALLDIF): New.
(Vbtype): Handle more modes.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@205385 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/aarch64/iterators.md')
| -rw-r--r-- | gcc/config/aarch64/iterators.md | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index fd7152c8ff4..43279ad2c0c 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -107,6 +107,10 @@ ;; All vector modes and DI. (define_mode_iterator VALLDI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF DI]) +;; All vector modes and DI and DF. +(define_mode_iterator VALLDIF [V8QI V16QI V4HI V8HI V2SI V4SI + V2DI V2SF V4SF V2DF DI DF]) + ;; Vector modes for Integer reduction across lanes. (define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI V2DI]) @@ -363,7 +367,8 @@ (V4HI "8b") (V8HI "16b") (V2SI "8b") (V4SI "16b") (V2DI "16b") (V2SF "8b") - (V4SF "16b") (V2DF "16b")]) + (V4SF "16b") (V2DF "16b") + (DI "8b") (DF "8b")]) ;; Define element mode for each vector mode. (define_mode_attr VEL [(V8QI "QI") (V16QI "QI") |