[AArch64] Remove/merge redundant iterators

	* config/aarch64/aarch64-simd.md (aarch64_simd_dup<mode>, orn<mode>3,
	bic<mode>3, add<mode>3, sub<mode>3, neg<mode>2, abs<mode>2, and<mode>3,
	ior<mode>3, xor<mode>3, one_cmpl<mode>2,
	aarch64_simd_lshr<mode> ,arch64_simd_ashr<mode>,
	aarch64_simd_imm_shl<mode>, aarch64_simd_reg_sshl<mode>,
	aarch64_simd_reg_shl<mode>_unsigned, aarch64_simd_reg_shr<mode>_signed,
	ashl<mode>3, lshr<mode>3, ashr<mode>3, vashl<mode>3,
	reduc_plus_scal_<mode>, aarch64_vcond_internal<mode><mode>,
	vcondu<mode><mode>, aarch64_cm<optab><mode>, aarch64_cmtst<mode>):
	Change VDQ to VDQ_I.

	(mul<mode>3): Change VDQM to VDQ_BHSI.
	(aarch64_simd_vec_set<mode>,vashr<mode>3, vlshr<mode>3, vec_set<mode>,
	aarch64_mla<mode>, aarch64_mls<mode>, <su><maxmin><mode>3,
	aarch64_<sur>h<addsub><mode>): Change VQ_S to VDQ_BHSI.
	
	(*aarch64_<su>mlal<mode>, *aarch64_<su>mlsl<mode>,
	aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>,
	aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>, aarch64_<sur>shll_n<mode>):
	Change VDW to VD_BHSI.
	(*aarch64_combinez<mode>, *aarch64_combinez_be<mode>):
	Change VDIC to VD_BHSI.

	* config/aarch64/aarch64-simd-builtins.def (saddl, uaddl, ssubl, usubl,
	saddw, uaddw, ssubw, usubw, shadd, uhadd, srhadd, urhadd, sshll_n,
	ushll_n): Change BUILTIN_VDW to BUILTIN_VD_BHSI.

	* config/aarch64/iterators.md (SDQ_I, VDQ, VQ_S, VSDQ_I_BHSI, VDQM, VDW,
	VDIC, VDQQHS): Remove.
	(Vwtype): Update comment (changing VDW to VD_BHSI).


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@218310 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 1 insertions, 26 deletions

diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 8b9ff98ba12..76be6927eb2 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -32,9 +32,6 @@
 ;; Iterator for all integer modes (up to 64-bit)
 (define_mode_iterator ALLI [QI HI SI DI])
 
-;; Iterator scalar modes (up to 64-bit)
-(define_mode_iterator SDQ_I [QI HI SI DI])
-
 ;; Iterator for all integer modes that can be extended (up to 64-bit)
 (define_mode_iterator ALLX [QI HI SI])
 
@@ -42,9 +39,6 @@
 (define_mode_iterator GPF [SF DF])
 
 ;; Integer vector modes.
-(define_mode_iterator VDQ [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
-
-;; Integer vector modes.
 (define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
 
 ;; vector and scalar, 64 & 128-bit container, all integer modes
@@ -72,16 +66,6 @@
 ;; Quad vector with only 2 element modes.
 (define_mode_iterator VQ_2E [V2DI V2DF])
 
-;; All vector modes, except double.
-(define_mode_iterator VQ_S [V8QI V16QI V4HI V8HI V2SI V4SI])
-
-;; Vector and scalar, 64 & 128-bit container: all vector integer mode;
-;; 8, 16, 32-bit scalar integer modes
-(define_mode_iterator VSDQ_I_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI])
-
-;; Vector modes for moves.
-(define_mode_iterator VDQM [V8QI V16QI V4HI V8HI V2SI V4SI])
-
 ;; This mode iterator allows :P to be used for patterns that operate on
 ;; addresses in different modes.  In LP64, only DI will match, while in
 ;; ILP32, either can match.
@@ -132,9 +116,6 @@
 ;; All quad integer narrow-able modes.
 (define_mode_iterator VQN [V8HI V4SI V2DI])
 
-;; All double integer widen-able modes.
-(define_mode_iterator VDW [V8QI V4HI V2SI])
-
 ;; Vector and scalar 128-bit container: narrowable 16, 32, 64-bit integer modes
 (define_mode_iterator VSQN_HSDI [V8HI V4SI V2DI HI SI DI])
 
@@ -144,9 +125,6 @@
 ;; Double vector modes for combines.
 (define_mode_iterator VDC [V8QI V4HI V2SI V2SF DI DF])
 
-;; Double vector modes for combines.
-(define_mode_iterator VDIC [V8QI V4HI V2SI])
-
 ;; Vector modes except double int.
 (define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF])
 
@@ -159,9 +137,6 @@
 ;; Vector modes for H, S and D types.
 (define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI])
 
-;; Vector modes for Q, H and S types.
-(define_mode_iterator VDQQHS [V8QI V16QI V4HI V8HI V2SI V4SI])
-
 ;; Vector and scalar integer modes for H and S
 (define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI])
 
@@ -487,7 +462,7 @@
 
 )
 
-;; Widened mode register suffixes for VDW/VQW.
+;; Widened mode register suffixes for VD_BHSI/VQW.
 (define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s")
 			  (V2SI "2d") (V16QI "8h") 
 			  (V8HI "4s") (V4SI "2d")])